Lines Matching +full:phy +full:- +full:pma
1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell 10G 88x3310 PHY driver
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
30 #include <linux/phy.h>
104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
171 return phydev->drv->driver_data; in to_mv3310_chip()
209 temp = chip->hwmon_read_temp_reg(phydev); in mv3310_hwmon_read()
213 *value = ((temp & 0xff) - 75) * 1000; in mv3310_hwmon_read()
218 return -EOPNOTSUPP; in mv3310_hwmon_read()
262 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310) in mv3310_hwmon_config()
278 struct device *dev = &phydev->mdio.dev; in mv3310_hwmon_probe()
279 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_hwmon_probe()
282 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); in mv3310_hwmon_probe()
283 if (!priv->hwmon_name) in mv3310_hwmon_probe()
284 return -ENODEV; in mv3310_hwmon_probe()
286 for (i = j = 0; priv->hwmon_name[i]; i++) { in mv3310_hwmon_probe()
287 if (isalnum(priv->hwmon_name[i])) { in mv3310_hwmon_probe()
289 priv->hwmon_name[j] = priv->hwmon_name[i]; in mv3310_hwmon_probe()
293 priv->hwmon_name[j] = '\0'; in mv3310_hwmon_probe()
299 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, in mv3310_hwmon_probe()
300 priv->hwmon_name, phydev, in mv3310_hwmon_probe()
303 return PTR_ERR_OR_ZERO(priv->hwmon_dev); in mv3310_hwmon_probe()
325 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_power_up()
331 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || in mv3310_power_up()
332 priv->firmware_ver < 0x00030000) in mv3310_power_up()
356 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_get_downshift()
359 if (!priv->has_downshift) in mv3310_get_downshift()
360 return -EOPNOTSUPP; in mv3310_get_downshift()
377 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_set_downshift()
381 if (!priv->has_downshift) in mv3310_set_downshift()
382 return -EOPNOTSUPP; in mv3310_set_downshift()
389 * set the default settings for the PHY. However, it is used for in mv3310_set_downshift()
390 * "ethtool --set-phy-tunable ethN downshift on". The intention is in mv3310_set_downshift()
399 return -E2BIG; in mv3310_set_downshift()
401 ds -= 1; in mv3310_set_downshift()
461 return -EINVAL; in mv3310_set_edpd()
479 sfp_parse_support(phydev->sfp_bus, id, support, interfaces); in mv3310_sfp_insert()
480 iface = sfp_select_interface(phydev->sfp_bus, support); in mv3310_sfp_insert()
483 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); in mv3310_sfp_insert()
484 return -EINVAL; in mv3310_sfp_insert()
502 if (!phydev->is_c45 || in mv3310_probe()
503 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) in mv3310_probe()
504 return -ENODEV; in mv3310_probe()
511 dev_warn(&phydev->mdio.dev, in mv3310_probe()
512 "PHY failed to boot firmware, status=%04x\n", ret); in mv3310_probe()
513 return -ENODEV; in mv3310_probe()
516 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in mv3310_probe()
518 return -ENOMEM; in mv3310_probe()
520 dev_set_drvdata(&phydev->mdio.dev, priv); in mv3310_probe()
526 priv->firmware_ver = ret << 16; in mv3310_probe()
532 priv->firmware_ver |= ret; in mv3310_probe()
535 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255, in mv3310_probe()
536 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255); in mv3310_probe()
538 if (chip->has_downshift) in mv3310_probe()
539 priv->has_downshift = chip->has_downshift(phydev); in mv3310_probe()
550 chip->init_supported_interfaces(priv->supported_interfaces); in mv3310_probe()
577 * don't set bit 14 in PMA Extended Abilities (1.11), although they do
580 * the PMA device identifier, with a mask matching models known to have this
585 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) in mv3310_has_pma_ngbaset_quirk()
588 /* Only some revisions of the 88X3310 family PMA seem to be impacted */ in mv3310_has_pma_ngbaset_quirk()
589 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3310_has_pma_ngbaset_quirk()
644 return -1; in mv2110_select_mactype()
695 return -1; in mv3310_select_mactype()
700 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv2110_init_interface()
702 priv->rate_match = false; in mv2110_init_interface()
705 priv->rate_match = true; in mv2110_init_interface()
708 priv->const_interface = PHY_INTERFACE_MODE_USXGMII; in mv2110_init_interface()
710 priv->const_interface = PHY_INTERFACE_MODE_10GBASER; in mv2110_init_interface()
713 priv->const_interface = PHY_INTERFACE_MODE_NA; in mv2110_init_interface()
715 return -EINVAL; in mv2110_init_interface()
722 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_init_interface()
724 priv->rate_match = false; in mv3310_init_interface()
729 priv->rate_match = true; in mv3310_init_interface()
732 priv->const_interface = PHY_INTERFACE_MODE_USXGMII; in mv3310_init_interface()
736 priv->const_interface = PHY_INTERFACE_MODE_10GBASER; in mv3310_init_interface()
739 priv->const_interface = PHY_INTERFACE_MODE_RXAUI; in mv3310_init_interface()
742 priv->const_interface = PHY_INTERFACE_MODE_XAUI; in mv3310_init_interface()
744 return -EINVAL; in mv3310_init_interface()
751 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3340_init_interface()
754 priv->rate_match = false; in mv3340_init_interface()
757 priv->const_interface = PHY_INTERFACE_MODE_RXAUI; in mv3340_init_interface()
766 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_config_init()
770 /* Check that the PHY interface type is compatible */ in mv3310_config_init()
771 if (!test_bit(phydev->interface, priv->supported_interfaces)) in mv3310_config_init()
772 return -ENODEV; in mv3310_config_init()
774 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in mv3310_config_init()
784 if (!phy_interface_empty(phydev->host_interfaces)) { in mv3310_config_init()
785 mactype = chip->select_mactype(phydev->host_interfaces); in mv3310_config_init()
789 err = chip->set_mactype(phydev, mactype); in mv3310_config_init()
795 mactype = chip->get_mactype(phydev); in mv3310_config_init()
799 err = chip->init_interface(phydev, mactype); in mv3310_config_init()
805 /* Enable EDPD mode - saving 600mW */ in mv3310_config_init()
812 if (err && err != -EOPNOTSUPP) in mv3310_config_init()
833 phydev->supported, in mv3310_get_features()
837 phydev->supported, in mv3310_get_features()
849 switch (phydev->mdix_ctrl) { in mv3310_config_mdix()
860 return -EINVAL; in mv3310_config_mdix()
881 if (phydev->autoneg == AUTONEG_DISABLE) in mv3310_config_aneg()
893 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); in mv3310_config_aneg()
920 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_update_interface()
922 if (!phydev->link) in mv3310_update_interface()
925 /* In all of the "* with Rate Matching" modes the PHY interface is fixed in mv3310_update_interface()
926 * at 10Gb. The PHY adapts the rate to actual wire speed with help of in mv3310_update_interface()
929 * In USXGMII mode the PHY interface mode is also fixed. in mv3310_update_interface()
931 if (priv->rate_match || in mv3310_update_interface()
932 priv->const_interface == PHY_INTERFACE_MODE_USXGMII) { in mv3310_update_interface()
933 phydev->interface = priv->const_interface; in mv3310_update_interface()
937 /* The PHY automatically switches its serdes interface (and active PHYXS in mv3310_update_interface()
938 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R / in mv3310_update_interface()
940 * Florian suggests setting phydev->interface to communicate this to the in mv3310_update_interface()
943 switch (phydev->speed) { in mv3310_update_interface()
945 phydev->interface = priv->const_interface; in mv3310_update_interface()
948 phydev->interface = PHY_INTERFACE_MODE_5GBASER; in mv3310_update_interface()
951 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; in mv3310_update_interface()
956 phydev->interface = PHY_INTERFACE_MODE_SGMII; in mv3310_update_interface()
963 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
966 phydev->link = 1; in mv3310_read_status_10gbaser()
967 phydev->speed = SPEED_10000; in mv3310_read_status_10gbaser()
968 phydev->duplex = DUPLEX_FULL; in mv3310_read_status_10gbaser()
969 phydev->port = PORT_FIBRE; in mv3310_read_status_10gbaser()
992 phydev->link = 0; in mv3310_read_status_copper()
1003 phydev->speed = SPEED_10000; in mv3310_read_status_copper()
1007 phydev->speed = SPEED_5000; in mv3310_read_status_copper()
1011 phydev->speed = SPEED_2500; in mv3310_read_status_copper()
1015 phydev->speed = SPEED_1000; in mv3310_read_status_copper()
1019 phydev->speed = SPEED_100; in mv3310_read_status_copper()
1023 phydev->speed = SPEED_10; in mv3310_read_status_copper()
1027 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? in mv3310_read_status_copper()
1029 phydev->port = PORT_TP; in mv3310_read_status_copper()
1030 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? in mv3310_read_status_copper()
1043 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); in mv3310_read_status_copper()
1056 phydev->speed = SPEED_UNKNOWN; in mv3310_read_status()
1057 phydev->duplex = DUPLEX_UNKNOWN; in mv3310_read_status()
1058 linkmode_zero(phydev->lp_advertising); in mv3310_read_status()
1059 phydev->link = 0; in mv3310_read_status()
1060 phydev->pause = 0; in mv3310_read_status()
1061 phydev->asym_pause = 0; in mv3310_read_status()
1062 phydev->mdix = ETH_TP_MDI_INVALID; in mv3310_read_status()
1075 if (phydev->link) in mv3310_read_status()
1084 switch (tuna->id) { in mv3310_get_tunable()
1090 return -EOPNOTSUPP; in mv3310_get_tunable()
1097 switch (tuna->id) { in mv3310_set_tunable()
1103 return -EOPNOTSUPP; in mv3310_set_tunable()
1109 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_has_downshift()
1112 return priv->firmware_ver >= MV_VERSION(0,3,5,0); in mv3310_has_downshift()
1219 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3310_match_phy_device()
1228 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3340_match_phy_device()
1239 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv211x_match_phy_device()
1265 wol->supported = WAKE_MAGIC; in mv3110_get_wol()
1266 wol->wolopts = 0; in mv3110_get_wol()
1273 wol->wolopts |= WAKE_MAGIC; in mv3110_get_wol()
1281 if (wol->wolopts & WAKE_MAGIC) { in mv3110_set_wol()
1292 ((phydev->attached_dev->dev_addr[5] << 8) | in mv3110_set_wol()
1293 phydev->attached_dev->dev_addr[4])); in mv3110_set_wol()
1299 ((phydev->attached_dev->dev_addr[3] << 8) | in mv3110_set_wol()
1300 phydev->attached_dev->dev_addr[2])); in mv3110_set_wol()
1306 ((phydev->attached_dev->dev_addr[1] << 8) | in mv3110_set_wol()
1307 phydev->attached_dev->dev_addr[0])); in mv3110_set_wol()
1328 /* Reset the clear WOL status bit as it does not self-clear */ in mv3110_set_wol()
1423 MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");