Lines Matching +full:rx +full:- +full:internal +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/delay.h>
17 #include <linux/nvmem-consumer.h>
19 #include <dt-bindings/net/ti-dp83867.h>
185 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
192 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
197 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
198 mac = (const u8 *)ndev->dev_addr; in dp83867_set_wol()
201 return -EINVAL; in dp83867_set_wol()
215 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
217 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol()
219 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83867_set_wol()
221 (wol->sopass[5] << 8) | wol->sopass[4]); in dp83867_set_wol()
228 if (wol->wolopts & WAKE_UCAST) in dp83867_set_wol()
233 if (wol->wolopts & WAKE_BCAST) in dp83867_set_wol()
253 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | in dp83867_get_wol()
255 wol->wolopts = 0; in dp83867_get_wol()
260 wol->wolopts |= WAKE_UCAST; in dp83867_get_wol()
263 wol->wolopts |= WAKE_BCAST; in dp83867_get_wol()
266 wol->wolopts |= WAKE_MAGIC; in dp83867_get_wol()
271 wol->sopass[0] = (sopass_val & 0xff); in dp83867_get_wol()
272 wol->sopass[1] = (sopass_val >> 8); in dp83867_get_wol()
276 wol->sopass[2] = (sopass_val & 0xff); in dp83867_get_wol()
277 wol->sopass[3] = (sopass_val >> 8); in dp83867_get_wol()
281 wol->sopass[4] = (sopass_val & 0xff); in dp83867_get_wol()
282 wol->sopass[5] = (sopass_val >> 8); in dp83867_get_wol()
284 wol->wolopts |= WAKE_MAGICSECURE; in dp83867_get_wol()
288 wol->wolopts = 0; in dp83867_get_wol()
295 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in dp83867_config_intr()
362 phydev->duplex = DUPLEX_FULL; in dp83867_read_status()
364 phydev->duplex = DUPLEX_HALF; in dp83867_read_status()
367 phydev->speed = SPEED_1000; in dp83867_read_status()
369 phydev->speed = SPEED_100; in dp83867_read_status()
371 phydev->speed = SPEED_10; in dp83867_read_status()
401 return -EINVAL; in dp83867_get_downshift()
414 return -E2BIG; in dp83867_set_downshift()
436 return -EINVAL; in dp83867_set_downshift()
450 switch (tuna->id) { in dp83867_get_tunable()
454 return -EOPNOTSUPP; in dp83867_get_tunable()
461 switch (tuna->id) { in dp83867_set_tunable()
465 return -EOPNOTSUPP; in dp83867_set_tunable()
472 (struct dp83867_private *)phydev->priv; in dp83867_config_port_mirroring()
474 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) in dp83867_config_port_mirroring()
485 struct dp83867_private *dp83867 = phydev->priv; in dp83867_verify_rgmii_cfg()
487 /* Existing behavior was to use default pin strapping delay in rgmii in dp83867_verify_rgmii_cfg()
488 * mode, but rgmii should have meant no delay. Warn existing users. in dp83867_verify_rgmii_cfg()
490 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { in dp83867_verify_rgmii_cfg()
501 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" in dp83867_verify_rgmii_cfg()
502 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n", in dp83867_verify_rgmii_cfg()
506 /* RX delay *must* be specified if internal delay of RX is used. */ in dp83867_verify_rgmii_cfg()
507 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in dp83867_verify_rgmii_cfg()
508 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && in dp83867_verify_rgmii_cfg()
509 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) { in dp83867_verify_rgmii_cfg()
510 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
511 return -EINVAL; in dp83867_verify_rgmii_cfg()
514 /* TX delay *must* be specified if internal delay of TX is used. */ in dp83867_verify_rgmii_cfg()
515 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in dp83867_verify_rgmii_cfg()
516 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && in dp83867_verify_rgmii_cfg()
517 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) { in dp83867_verify_rgmii_cfg()
518 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
519 return -EINVAL; in dp83867_verify_rgmii_cfg()
528 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init_io_impedance()
529 struct device *dev = &phydev->mdio.dev; in dp83867_of_init_io_impedance()
530 struct device_node *of_node = dev->of_node; in dp83867_of_init_io_impedance()
538 if (ret != -ENOENT && ret != -EOPNOTSUPP) in dp83867_of_init_io_impedance()
543 if (of_property_read_bool(of_node, "ti,max-output-impedance")) in dp83867_of_init_io_impedance()
544 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; in dp83867_of_init_io_impedance()
545 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) in dp83867_of_init_io_impedance()
546 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; in dp83867_of_init_io_impedance()
548 dp83867->io_impedance = -1; /* leave at default */ in dp83867_of_init_io_impedance()
564 return -ERANGE; in dp83867_of_init_io_impedance()
566 dp83867->io_impedance = val; in dp83867_of_init_io_impedance()
573 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init()
574 struct device *dev = &phydev->mdio.dev; in dp83867_of_init()
575 struct device_node *of_node = dev->of_node; in dp83867_of_init()
579 return -ENODEV; in dp83867_of_init()
582 ret = of_property_read_u32(of_node, "ti,clk-output-sel", in dp83867_of_init()
583 &dp83867->clk_output_sel); in dp83867_of_init()
586 dp83867->set_clk_output = true; in dp83867_of_init()
590 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && in dp83867_of_init()
591 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { in dp83867_of_init()
592 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", in dp83867_of_init()
593 dp83867->clk_output_sel); in dp83867_of_init()
594 return -EINVAL; in dp83867_of_init()
602 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, in dp83867_of_init()
603 "ti,dp83867-rxctrl-strap-quirk"); in dp83867_of_init()
605 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, in dp83867_of_init()
606 "ti,sgmii-ref-clock-output-enable"); in dp83867_of_init()
608 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV; in dp83867_of_init()
609 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", in dp83867_of_init()
610 &dp83867->rx_id_delay); in dp83867_of_init()
611 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { in dp83867_of_init()
613 "ti,rx-internal-delay value of %u out of range\n", in dp83867_of_init()
614 dp83867->rx_id_delay); in dp83867_of_init()
615 return -EINVAL; in dp83867_of_init()
618 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV; in dp83867_of_init()
619 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", in dp83867_of_init()
620 &dp83867->tx_id_delay); in dp83867_of_init()
621 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { in dp83867_of_init()
623 "ti,tx-internal-delay value of %u out of range\n", in dp83867_of_init()
624 dp83867->tx_id_delay); in dp83867_of_init()
625 return -EINVAL; in dp83867_of_init()
628 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) in dp83867_of_init()
629 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; in dp83867_of_init()
631 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) in dp83867_of_init()
632 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; in dp83867_of_init()
634 ret = of_property_read_u32(of_node, "ti,fifo-depth", in dp83867_of_init()
635 &dp83867->tx_fifo_depth); in dp83867_of_init()
637 ret = of_property_read_u32(of_node, "tx-fifo-depth", in dp83867_of_init()
638 &dp83867->tx_fifo_depth); in dp83867_of_init()
640 dp83867->tx_fifo_depth = in dp83867_of_init()
644 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
645 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", in dp83867_of_init()
646 dp83867->tx_fifo_depth); in dp83867_of_init()
647 return -EINVAL; in dp83867_of_init()
650 ret = of_property_read_u32(of_node, "rx-fifo-depth", in dp83867_of_init()
651 &dp83867->rx_fifo_depth); in dp83867_of_init()
653 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
655 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
656 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", in dp83867_of_init()
657 dp83867->rx_fifo_depth); in dp83867_of_init()
658 return -EINVAL; in dp83867_of_init()
666 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init()
667 u16 delay; in dp83867_of_init() local
669 /* For non-OF device, the RX and TX ID values are either strapped in dp83867_of_init()
670 * or take from default value. So, we init RX & TX ID values here in dp83867_of_init()
674 delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL); in dp83867_of_init()
675 dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX; in dp83867_of_init()
676 dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) & in dp83867_of_init()
679 /* Per datasheet, IO impedance is default to 50-ohm, so we set the in dp83867_of_init()
683 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2; in dp83867_of_init()
685 /* For non-OF device, the RX and TX FIFO depths are taken from in dp83867_of_init()
686 * default value. So, we init RX & TX FIFO depths here in dp83867_of_init()
689 dp83867->tx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
690 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
700 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), in dp83867_probe()
703 return -ENOMEM; in dp83867_probe()
705 phydev->priv = dp83867; in dp83867_probe()
712 struct dp83867_private *dp83867 = phydev->priv; in dp83867_config_init()
714 u16 delay; in dp83867_config_init() local
727 if (dp83867->rxctrl_strap_quirk) in dp83867_config_init()
734 * be set to 0x2. This may causes the PHY link to be unstable - in dp83867_config_init()
746 phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
752 val |= (dp83867->tx_fifo_depth << in dp83867_config_init()
755 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
757 val |= (dp83867->rx_fifo_depth << in dp83867_config_init()
775 * internal testing mode and disable RGMII transmission. in dp83867_config_init()
789 /* If rgmii mode with no internal delay is selected, we do NOT use in dp83867_config_init()
792 * internal delay with a value of 7 (2.00 ns). in dp83867_config_init()
799 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in dp83867_config_init()
802 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) in dp83867_config_init()
805 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) in dp83867_config_init()
810 delay = 0; in dp83867_config_init()
811 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV) in dp83867_config_init()
812 delay |= dp83867->rx_id_delay; in dp83867_config_init()
813 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV) in dp83867_config_init()
814 delay |= dp83867->tx_id_delay << in dp83867_config_init()
818 delay); in dp83867_config_init()
822 if (dp83867->io_impedance >= 0) in dp83867_config_init()
825 dp83867->io_impedance); in dp83867_config_init()
827 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
854 /* SGMII type is set to 4-wire mode by default. in dp83867_config_init()
856 * switch on 6-wire mode. in dp83867_config_init()
858 if (dp83867->sgmii_ref_clk_en) in dp83867_config_init()
868 if (dp83867->rxctrl_strap_quirk) in dp83867_config_init()
881 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) in dp83867_config_init()
885 if (dp83867->set_clk_output) { in dp83867_config_init()
888 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { in dp83867_config_init()
892 val = dp83867->clk_output_sel << in dp83867_config_init()
922 * hence no new in-band message from PHY to MAC side SGMII. in dp83867_link_change_notify()
925 * SGMII wouldn`t receive new in-band message from TI PHY with in dp83867_link_change_notify()
927 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg in dp83867_link_change_notify()
930 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_link_change_notify()