80 	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);  in bcm7xxx_28nm_d0_afe_config_init()
108 	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);  in bcm7xxx_28nm_e0_plus_afe_config_init()
266 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);  in bcm7xxx_28nm_ephy_01_afe_config_init()
271 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_01_afe_config_init()
281 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_01_afe_config_init()
337 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
341 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
347 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
351 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
356 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
360 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
366 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,  in bcm7xxx_28nm_ephy_eee_enable()
370 	ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,  in bcm7xxx_28nm_ephy_eee_enable()
383 	phy_write(phydev, MII_BMCR,  in bcm7xxx_28nm_ephy_eee_enable()
706 	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);  in bcm7xxx_config_init()
716 	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);  in bcm7xxx_config_init()
720 	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);  in bcm7xxx_config_init()
722 	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);  in bcm7xxx_config_init()
752 		ret = phy_write(phydev,  in bcm7xxx_suspend()