1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/pcs-rzn1-miic.h>
16 #include <dt-bindings/net/pcs-rzn1-miic.h>
51 #define MIIC_MODCTRL_CONF_NONE		-1
54  * struct modctrl_match - Matching table entry for  convctrl configuration
58  *	  then index 1 - 5 are CONV1 - CONV5.
121  * struct miic - MII converter structure
126  * @lock: Lock used for read-modify-write access
137  * struct miic_port - Per port MII converter struct
157 	writel(value, miic->base + offset);  in miic_reg_writel()
162 	return readl(miic->base + offset);  in miic_reg_readl()
169 	spin_lock(&miic->lock);  in miic_reg_rmw()
176 	spin_unlock(&miic->lock);  in miic_reg_rmw()
194 	struct miic *miic = miic_port->miic;  in miic_config()
196 	int port = miic_port->port;  in miic_config()
218 		return -EOPNOTSUPP;  in miic_config()
228 	if (interface != miic_port->interface) {  in miic_config()
231 		miic_port->interface = interface;  in miic_config()
235 	miic_converter_enable(miic_port->miic, miic_port->port, 1);  in miic_config()
244 	struct miic *miic = miic_port->miic;  in miic_link_up()
246 	int port = miic_port->port;  in miic_link_up()
251 	/* No speed in MII through-mode */  in miic_link_up()
277 	if (phy_interface_mode_is_rgmii(state->interface) ||  in miic_validate()
278 	    state->interface == PHY_INTERFACE_MODE_RMII ||  in miic_validate()
279 	    state->interface == PHY_INTERFACE_MODE_MII)  in miic_validate()
282 	return -EINVAL;  in miic_validate()
300 		return ERR_PTR(-ENODEV);  in miic_create()
303 		return ERR_PTR(-EINVAL);  in miic_create()
306 		return ERR_PTR(-EINVAL);  in miic_create()
311 		return ERR_PTR(-ENODEV);  in miic_create()
315 		return ERR_PTR(-ENODEV);  in miic_create()
321 		return ERR_PTR(-EPROBE_DEFER);  in miic_create()
325 		return ERR_PTR(-ENOMEM);  in miic_create()
328 	device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER);  in miic_create()
330 	miic_port->miic = miic;  in miic_create()
331 	miic_port->port = port - 1;  in miic_create()
332 	miic_port->pcs.ops = &miic_phylink_ops;  in miic_create()
334 	return &miic_port->pcs;  in miic_create()
342 	miic_converter_enable(miic_port->miic, miic_port->port, 0);  in miic_destroy()
352 	 * is going to be used in conjunction with the Cortex-M3, this sequence  in miic_init_hw()
418 		if (miic_modctrl_match(table_entry->conv, dt_val)) {  in miic_match_dt_conf()
419 			*mode_cfg = table_entry->mode_cfg;  in miic_match_dt_conf()
427 	return -EINVAL;  in miic_match_dt_conf()
433 	struct device_node *np = dev->of_node;  in miic_parse_dt()
440 	if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0)  in miic_parse_dt()
450 		if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0)  in miic_parse_dt()
459 	struct device *dev = &pdev->dev;  in miic_probe()
470 		return -ENOMEM;  in miic_probe()
472 	spin_lock_init(&miic->lock);  in miic_probe()
473 	miic->dev = dev;  in miic_probe()
474 	miic->base = devm_platform_ioremap_resource(pdev, 0);  in miic_probe()
475 	if (IS_ERR(miic->base))  in miic_probe()
476 		return PTR_ERR(miic->base);  in miic_probe()
507 	pm_runtime_put(&pdev->dev);  in miic_remove()
513 	{ .compatible = "renesas,rzn1-miic" },