Lines Matching +full:0 +full:x4000
53 #define GSI_EE_REG_ADJUST 0x0000d000 /* IPA v4.5+ */
58 (0x0000c020 + 0x1000 * GSI_EE_AP)
61 (0x0000c024 + 0x1000 * GSI_EE_AP)
67 GSI_CHANNEL_TYPE_MHI = 0x0,
68 GSI_CHANNEL_TYPE_XHCI = 0x1,
69 GSI_CHANNEL_TYPE_GPI = 0x2,
70 GSI_CHANNEL_TYPE_XDCI = 0x3,
71 GSI_CHANNEL_TYPE_WDI2 = 0x4,
72 GSI_CHANNEL_TYPE_GCI = 0x5,
73 GSI_CHANNEL_TYPE_WDI3 = 0x6,
74 GSI_CHANNEL_TYPE_MHIP = 0x7,
75 GSI_CHANNEL_TYPE_AQC = 0x8,
76 GSI_CHANNEL_TYPE_11AD = 0x9,
80 (0x0001c000 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
81 #define CHTYPE_PROTOCOL_FMASK GENMASK(2, 0)
109 (0x0001c004 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
115 return u32_encode_bits(length, GENMASK(15, 0)); in r_length_encoded()
116 return u32_encode_bits(length, GENMASK(19, 0)); in r_length_encoded()
120 (0x0001c008 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
123 (0x0001c00c + 0x4000 * GSI_EE_AP + 0x80 * (ch))
126 (0x0001c05c + 0x4000 * GSI_EE_AP + 0x80 * (ch))
127 #define WRR_WEIGHT_FMASK GENMASK(3, 0)
130 /* The next field is only present for IPA v4.0, v4.1, and v4.2 */
140 GSI_USE_PREFETCH_BUFS = 0x0,
141 GSI_ESCAPE_BUF_ONLY = 0x1,
142 GSI_SMART_PREFETCH = 0x2,
143 GSI_FREE_PREFETCH = 0x3,
147 (0x0001c060 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
150 (0x0001c064 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
153 (0x0001c068 + 0x4000 * GSI_EE_AP + 0x80 * (ch))
156 (0x0001c06c + 0x4000 * GSI_EE_AP + 0x80 * (ch))
159 (0x0001d000 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
161 #define EV_CHTYPE_FMASK GENMASK(3, 0)
169 (0x0001d004 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
174 return u32_encode_bits(length, GENMASK(15, 0)); in ev_r_length_encoded()
175 return u32_encode_bits(length, GENMASK(19, 0)); in ev_r_length_encoded()
179 (0x0001d008 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
182 (0x0001d00c + 0x4000 * GSI_EE_AP + 0x80 * (ev))
185 (0x0001d010 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
188 (0x0001d020 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
189 #define MODT_FMASK GENMASK(15, 0)
194 (0x0001d024 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
197 (0x0001d028 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
200 (0x0001d02c + 0x4000 * GSI_EE_AP + 0x80 * (ev))
203 (0x0001d030 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
206 (0x0001d034 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
209 (0x0001d048 + 0x4000 * GSI_EE_AP + 0x80 * (ev))
212 (0x0001d04c + 0x4000 * GSI_EE_AP + 0x80 * (ev))
215 (0x0001e000 + 0x4000 * GSI_EE_AP + 0x08 * (ch))
218 (0x0001e100 + 0x4000 * GSI_EE_AP + 0x08 * (ev))
221 (0x0001f000 + 0x4000 * GSI_EE_AP)
222 #define ENABLED_FMASK GENMASK(0, 0)
225 (0x0001f008 + 0x4000 * GSI_EE_AP)
226 #define CH_CHID_FMASK GENMASK(7, 0)
231 GSI_CH_ALLOCATE = 0x0,
232 GSI_CH_START = 0x1,
233 GSI_CH_STOP = 0x2,
234 GSI_CH_RESET = 0x9,
235 GSI_CH_DE_ALLOC = 0xa,
236 GSI_CH_DB_STOP = 0xb,
240 (0x0001f010 + 0x4000 * GSI_EE_AP)
241 #define EV_CHID_FMASK GENMASK(7, 0)
246 GSI_EVT_ALLOCATE = 0x0,
247 GSI_EVT_RESET = 0x9,
248 GSI_EVT_DE_ALLOC = 0xa,
252 (0x0001f018 + 0x4000 * GSI_EE_AP)
253 #define GENERIC_OPCODE_FMASK GENMASK(4, 0)
260 GSI_GENERIC_HALT_CHANNEL = 0x1,
261 GSI_GENERIC_ALLOCATE_CHANNEL = 0x2,
262 GSI_GENERIC_ENABLE_FLOW_CONTROL = 0x3, /* IPA v4.2+ */
263 GSI_GENERIC_DISABLE_FLOW_CONTROL = 0x4, /* IPA v4.2+ */
264 GSI_GENERIC_QUERY_FLOW_CONTROL = 0x5, /* IPA v4.11+ */
269 (0x0001f040 + 0x4000 * GSI_EE_AP)
270 #define IRAM_SIZE_FMASK GENMASK(2, 0)
275 /* Fields below are present for IPA v4.0 and above */
286 IRAM_SIZE_ONE_KB = 0x0,
287 IRAM_SIZE_TWO_KB = 0x1,
288 /* The next two values are available for IPA v4.0 and above */
289 IRAM_SIZE_TWO_N_HALF_KB = 0x2,
290 IRAM_SIZE_THREE_KB = 0x3,
292 IRAM_SIZE_THREE_N_HALF_KB = 0x4,
293 IRAM_SIZE_FOUR_KB = 0x5,
298 (0x0001f080 + 0x4000 * GSI_EE_AP)
300 (0x0001f088 + 0x4000 * GSI_EE_AP)
304 GSI_CH_CTRL = 0x0, /* channel allocation, etc. */
305 GSI_EV_CTRL = 0x1, /* event ring allocation, etc. */
306 GSI_GLOB_EE = 0x2, /* global/general event */
307 GSI_IEOB = 0x3, /* TRE completion */
308 GSI_INTER_EE_CH_CTRL = 0x4, /* remote-issued stop/reset (unused) */
309 GSI_INTER_EE_EV_CTRL = 0x5, /* remote-issued event reset (unused) */
310 GSI_GENERAL = 0x6, /* general-purpose event */
314 (0x0001f090 + 0x4000 * GSI_EE_AP)
317 (0x0001f094 + 0x4000 * GSI_EE_AP)
320 (0x0001f098 + 0x4000 * GSI_EE_AP)
323 (0x0001f09c + 0x4000 * GSI_EE_AP)
326 (0x0001f0a0 + 0x4000 * GSI_EE_AP)
329 (0x0001f0a4 + 0x4000 * GSI_EE_AP)
332 (0x0001f0b0 + 0x4000 * GSI_EE_AP)
335 (0x0001f0b8 + 0x4000 * GSI_EE_AP)
338 (0x0001f0c0 + 0x4000 * GSI_EE_AP)
341 (0x0001f100 + 0x4000 * GSI_EE_AP)
343 (0x0001f108 + 0x4000 * GSI_EE_AP)
345 (0x0001f110 + 0x4000 * GSI_EE_AP)
348 ERROR_INT = 0x0,
349 GP_INT1 = 0x1,
350 GP_INT2 = 0x2,
351 GP_INT3 = 0x3,
355 (0x0001f118 + 0x4000 * GSI_EE_AP)
357 (0x0001f120 + 0x4000 * GSI_EE_AP)
359 (0x0001f128 + 0x4000 * GSI_EE_AP)
362 BREAK_POINT = 0x0,
363 BUS_ERROR = 0x1,
364 CMD_FIFO_OVRFLOW = 0x2,
365 MCS_STACK_OVRFLOW = 0x3,
369 (0x0001f180 + 0x4000 * GSI_EE_AP)
370 #define INTYPE_FMASK GENMASK(0, 0)
373 (0x0001f200 + 0x4000 * GSI_EE_AP)
376 #define ERR_ARG3_FMASK GENMASK(3, 0)
386 GSI_INVALID_TRE = 0x1,
387 GSI_OUT_OF_BUFFERS = 0x2,
388 GSI_OUT_OF_RESOURCES = 0x3,
389 GSI_UNSUPPORTED_INTER_EE_OP = 0x4,
390 GSI_EVT_RING_EMPTY = 0x5,
391 GSI_NON_ALLOCATED_EVT_ACCESS = 0x6,
393 GSI_HWO_1 = 0x8,
398 GSI_ERR_TYPE_GLOB = 0x1,
399 GSI_ERR_TYPE_CHAN = 0x2,
400 GSI_ERR_TYPE_EVT = 0x3,
404 (0x0001f210 + 0x4000 * GSI_EE_AP)
407 (0x0001f400 + 0x4000 * GSI_EE_AP)
408 #define INTER_EE_RESULT_FMASK GENMASK(2, 0)
413 GENERIC_EE_SUCCESS = 0x1,
414 GENERIC_EE_INCORRECT_CHANNEL_STATE = 0x2,
415 GENERIC_EE_INCORRECT_DIRECTION = 0x3,
416 GENERIC_EE_INCORRECT_CHANNEL_TYPE = 0x4,
417 GENERIC_EE_INCORRECT_CHANNEL = 0x5,
418 GENERIC_EE_RETRY = 0x6,
419 GENERIC_EE_NO_RESOURCES = 0x7,