Lines Matching +full:ipa +full:- +full:ap +full:- +full:to +full:- +full:modem
1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2022 Linaro Ltd.
27 * DOC: The IPA Generic Software Interface
29 * The generic software interface (GSI) is an integral component of the IPA,
30 * providing a well-defined communication layer between the AP subsystem
31 * and the IPA core. The modem uses the GSI layer as well.
33 * -------- ---------
35 * | AP +<---. .----+ Modem |
36 * | +--. | | .->+ |
38 * -------- | | | | ---------
40 * --+-+---+-+--
42 * |-----------|
44 * | IPA |
46 * -------------
48 * In the above diagram, the AP and Modem represent "execution environments"
49 * (EEs), which are independent operating environments that use the IPA for
53 * of data to or from the IPA. A channel is implemented as a ring buffer,
54 * with a DRAM-resident array of "transfer elements" (TREs) available to
55 * describe transfers to or from other EEs through the IPA. A transfer
56 * element can also contain an immediate command, requesting the IPA perform
59 * Each TRE refers to a block of data--also located in DRAM. After writing
60 * one or more TREs to a channel, the writer (either the IPA or an EE) writes
61 * a doorbell register to inform the receiving side how many elements have
66 * the IPA to an EE. The IPA notifies an EE (such as the AP) about channel
67 * events by adding an entry to the event ring associated with the channel.
69 * EE to be interrupted. Each entry in an event ring contains a pointer
70 * to the channel TRE whose completion the event represents.
75 * elements to be chained together, forming a single logical transaction.
76 * TRE flags are used to control whether and when interrupts are generated
77 * to signal completion of channel transfers.
84 * Note that all GSI registers are little-endian, which is the assumed
89 /* Delay period for interrupt moderation (in 32KHz IPA internal timer ticks) */
114 /** gsi_channel_scratch_gpi - GPI protocol scratch register
118 * performed by the hardware. We configure this to equal the size of
122 * should update the channel doorbell. We configure this to equal
133 /** gsi_channel_scratch - channel scratch configuration area
135 * The exact interpretation of this register is protocol-specific.
176 return channel - &channel->gsi->channel[0]; in gsi_channel_id()
179 /* An initialized channel has a non-null GSI pointer */
182 return !!channel->gsi; in gsi_channel_initialized()
188 gsi->type_enabled_bitmap = val; in gsi_irq_type_update()
189 iowrite32(val, gsi->virt + GSI_CNTXT_TYPE_IRQ_MSK_OFFSET); in gsi_irq_type_update()
194 gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(type_id)); in gsi_irq_type_enable()
199 gsi_irq_type_update(gsi, gsi->type_enabled_bitmap & ~BIT(type_id)); in gsi_irq_type_disable()
215 iowrite32(~0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET); in gsi_irq_ev_ctrl_enable()
217 iowrite32(val, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET); in gsi_irq_ev_ctrl_enable()
225 iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET); in gsi_irq_ev_ctrl_disable()
241 iowrite32(~0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET); in gsi_irq_ch_ctrl_enable()
243 iowrite32(val, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET); in gsi_irq_ch_ctrl_enable()
251 iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET); in gsi_irq_ch_ctrl_disable()
256 bool enable_ieob = !gsi->ieob_enabled_bitmap; in gsi_irq_ieob_enable_one()
259 gsi->ieob_enabled_bitmap |= BIT(evt_ring_id); in gsi_irq_ieob_enable_one()
260 val = gsi->ieob_enabled_bitmap; in gsi_irq_ieob_enable_one()
261 iowrite32(val, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); in gsi_irq_ieob_enable_one()
272 gsi->ieob_enabled_bitmap &= ~event_mask; in gsi_irq_ieob_disable()
275 if (!gsi->ieob_enabled_bitmap) in gsi_irq_ieob_disable()
278 val = gsi->ieob_enabled_bitmap; in gsi_irq_ieob_disable()
279 iowrite32(val, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); in gsi_irq_ieob_disable()
295 iowrite32(BIT(ERROR_INT), gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); in gsi_irq_enable()
296 gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(GSI_GLOB_EE)); in gsi_irq_enable()
298 /* General GSI interrupts are reported to all EEs; if they occur in gsi_irq_enable()
300 * also exists, but we don't support that. We want to be notified in gsi_irq_enable()
306 iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); in gsi_irq_enable()
307 gsi_irq_type_update(gsi, gsi->type_enabled_bitmap | BIT(GSI_GENERAL)); in gsi_irq_enable()
315 /* Clear the type-specific interrupt masks set by gsi_irq_enable() */ in gsi_irq_disable()
316 iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); in gsi_irq_disable()
317 iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); in gsi_irq_disable()
324 return ring->virt + (index % ring->count) * GSI_RING_ELEMENT_SIZE; in gsi_ring_virt()
327 /* Return the 32-bit DMA address associated with a ring index */
330 return lower_32_bits(ring->addr) + index * GSI_RING_ELEMENT_SIZE; in gsi_ring_addr()
333 /* Return the ring index of a 32-bit ring offset */
336 return (offset - gsi_ring_addr(ring, 0)) / GSI_RING_ELEMENT_SIZE; in gsi_ring_index()
339 /* Issue a GSI command by writing a value to a register, then wait for
340 * completion to be signaled. Returns true if the command completes
346 struct completion *completion = &gsi->completion; in gsi_command()
350 iowrite32(val, gsi->virt + reg); in gsi_command()
361 val = ioread32(gsi->virt + GSI_EV_CH_E_CNTXT_0_OFFSET(evt_ring_id)); in gsi_evt_ring_state()
366 /* Issue an event ring command and wait for it to complete */
370 struct device *dev = gsi->dev; in gsi_evt_ring_command()
399 dev_err(gsi->dev, "event ring %u bad state %u before alloc\n", in gsi_evt_ring_alloc_command()
401 return -EINVAL; in gsi_evt_ring_alloc_command()
411 dev_err(gsi->dev, "event ring %u bad state %u after alloc\n", in gsi_evt_ring_alloc_command()
414 return -EIO; in gsi_evt_ring_alloc_command()
425 dev_err(gsi->dev, "event ring %u bad state %u before reset\n", in gsi_evt_ring_reset_command()
437 dev_err(gsi->dev, "event ring %u bad state %u after reset\n", in gsi_evt_ring_reset_command()
441 /* Issue a hardware de-allocation request for an allocated event ring */
448 dev_err(gsi->dev, "event ring %u state %u before dealloc\n", in gsi_evt_ring_de_alloc_command()
460 dev_err(gsi->dev, "event ring %u bad state %u after dealloc\n", in gsi_evt_ring_de_alloc_command()
468 void __iomem *virt = channel->gsi->virt; in gsi_channel_state()
476 /* Issue a channel command and wait for it to complete */
481 struct gsi *gsi = channel->gsi; in gsi_channel_command()
482 struct device *dev = gsi->dev; in gsi_channel_command()
505 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_alloc_command()
506 struct device *dev = gsi->dev; in gsi_channel_alloc_command()
514 return -EINVAL; in gsi_channel_alloc_command()
527 return -EIO; in gsi_channel_alloc_command()
533 struct device *dev = channel->gsi->dev; in gsi_channel_start_command()
541 return -EINVAL; in gsi_channel_start_command()
554 return -EIO; in gsi_channel_start_command()
560 struct device *dev = channel->gsi->dev; in gsi_channel_stop_command()
575 return -EINVAL; in gsi_channel_stop_command()
585 /* We may have to try again if stop is in progress */ in gsi_channel_stop_command()
587 return -EAGAIN; in gsi_channel_stop_command()
592 return -EIO; in gsi_channel_stop_command()
598 struct device *dev = channel->gsi->dev; in gsi_channel_reset_command()
607 /* No need to reset a channel already in ALLOCATED state */ in gsi_channel_reset_command()
626 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_de_alloc_command()
627 struct device *dev = gsi->dev; in gsi_channel_de_alloc_command()
647 /* Ring an event ring doorbell, reporting the last entry processed by the AP.
654 struct gsi_ring *ring = &gsi->evt_ring[evt_ring_id].ring; in gsi_evt_ring_doorbell()
657 ring->index = index; /* Next unused entry */ in gsi_evt_ring_doorbell()
660 val = gsi_ring_addr(ring, (index - 1) % ring->count); in gsi_evt_ring_doorbell()
661 iowrite32(val, gsi->virt + GSI_EV_CH_E_DOORBELL_0_OFFSET(evt_ring_id)); in gsi_evt_ring_doorbell()
667 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_evt_ring_program()
668 struct gsi_ring *ring = &evt_ring->ring; in gsi_evt_ring_program()
676 iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_0_OFFSET(evt_ring_id)); in gsi_evt_ring_program()
678 size = ring->count * GSI_RING_ELEMENT_SIZE; in gsi_evt_ring_program()
679 val = ev_r_length_encoded(gsi->version, size); in gsi_evt_ring_program()
680 iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_1_OFFSET(evt_ring_id)); in gsi_evt_ring_program()
682 /* The context 2 and 3 registers store the low-order and in gsi_evt_ring_program()
683 * high-order 32 bits of the address of the event ring, in gsi_evt_ring_program()
686 val = lower_32_bits(ring->addr); in gsi_evt_ring_program()
687 iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_2_OFFSET(evt_ring_id)); in gsi_evt_ring_program()
688 val = upper_32_bits(ring->addr); in gsi_evt_ring_program()
689 iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_3_OFFSET(evt_ring_id)); in gsi_evt_ring_program()
694 iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_8_OFFSET(evt_ring_id)); in gsi_evt_ring_program()
697 iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_9_OFFSET(evt_ring_id)); in gsi_evt_ring_program()
698 iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_10_OFFSET(evt_ring_id)); in gsi_evt_ring_program()
699 iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_11_OFFSET(evt_ring_id)); in gsi_evt_ring_program()
701 /* We don't need to get event read pointer updates */ in gsi_evt_ring_program()
702 iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_12_OFFSET(evt_ring_id)); in gsi_evt_ring_program()
703 iowrite32(0, gsi->virt + GSI_EV_CH_E_CNTXT_13_OFFSET(evt_ring_id)); in gsi_evt_ring_program()
706 gsi_evt_ring_doorbell(gsi, evt_ring_id, ring->index); in gsi_evt_ring_program()
712 struct gsi_trans_info *trans_info = &channel->trans_info; in gsi_channel_trans_last()
713 u32 pending_id = trans_info->pending_id; in gsi_channel_trans_last()
717 if (channel->toward_ipa && pending_id != trans_info->free_id) { in gsi_channel_trans_last()
723 trans_id = trans_info->free_id - 1; in gsi_channel_trans_last()
724 } else if (trans_info->polled_id != pending_id) { in gsi_channel_trans_last()
725 /* Otherwise (TX or RX) we want to wait for anything that in gsi_channel_trans_last()
731 trans_id = pending_id - 1; in gsi_channel_trans_last()
737 trans = &trans_info->trans[trans_id % channel->tre_count]; in gsi_channel_trans_last()
738 refcount_inc(&trans->refcount); in gsi_channel_trans_last()
743 /* Wait for transaction activity on a channel to complete */
748 /* Get the last transaction, and wait for it to complete */ in gsi_channel_trans_quiesce()
751 wait_for_completion(&trans->completion); in gsi_channel_trans_quiesce()
759 size_t size = channel->tre_ring.count * GSI_RING_ELEMENT_SIZE; in gsi_channel_program()
763 struct gsi *gsi = channel->gsi; in gsi_channel_program()
768 val = chtype_protocol_encoded(gsi->version, GSI_CHANNEL_TYPE_GPI); in gsi_channel_program()
769 if (channel->toward_ipa) in gsi_channel_program()
771 val |= u32_encode_bits(channel->evt_ring_id, ERINDEX_FMASK); in gsi_channel_program()
773 iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_0_OFFSET(channel_id)); in gsi_channel_program()
775 val = r_length_encoded(gsi->version, size); in gsi_channel_program()
776 iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_1_OFFSET(channel_id)); in gsi_channel_program()
778 /* The context 2 and 3 registers store the low-order and in gsi_channel_program()
779 * high-order 32 bits of the address of the channel ring, in gsi_channel_program()
782 val = lower_32_bits(channel->tre_ring.addr); in gsi_channel_program()
783 iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_2_OFFSET(channel_id)); in gsi_channel_program()
784 val = upper_32_bits(channel->tre_ring.addr); in gsi_channel_program()
785 iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_3_OFFSET(channel_id)); in gsi_channel_program()
787 /* Command channel gets low weighted round-robin priority */ in gsi_channel_program()
788 if (channel->command) in gsi_channel_program()
794 /* No need to use the doorbell engine starting at IPA v4.0 */ in gsi_channel_program()
795 if (gsi->version < IPA_VERSION_4_0 && doorbell) in gsi_channel_program()
799 * on all but the AP command channel. in gsi_channel_program()
801 if (gsi->version >= IPA_VERSION_4_0 && !channel->command) { in gsi_channel_program()
803 if (gsi->version < IPA_VERSION_4_5) in gsi_channel_program()
810 if (gsi->version >= IPA_VERSION_4_9) in gsi_channel_program()
813 iowrite32(val, gsi->virt + GSI_CH_C_QOS_OFFSET(channel_id)); in gsi_channel_program()
817 gpi->max_outstanding_tre = channel->trans_tre_max * in gsi_channel_program()
819 gpi->outstanding_threshold = 2 * GSI_RING_ELEMENT_SIZE; in gsi_channel_program()
822 iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_0_OFFSET(channel_id)); in gsi_channel_program()
825 iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_1_OFFSET(channel_id)); in gsi_channel_program()
828 iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_2_OFFSET(channel_id)); in gsi_channel_program()
834 val = ioread32(gsi->virt + GSI_CH_C_SCRATCH_3_OFFSET(channel_id)); in gsi_channel_program()
836 iowrite32(val, gsi->virt + GSI_CH_C_SCRATCH_3_OFFSET(channel_id)); in gsi_channel_program()
843 struct gsi *gsi = channel->gsi; in __gsi_channel_start()
846 /* Prior to IPA v4.0 suspend/resume is not implemented by GSI */ in __gsi_channel_start()
847 if (resume && gsi->version < IPA_VERSION_4_0) in __gsi_channel_start()
850 mutex_lock(&gsi->mutex); in __gsi_channel_start()
854 mutex_unlock(&gsi->mutex); in __gsi_channel_start()
862 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_start()
866 napi_enable(&channel->napi); in gsi_channel_start()
867 gsi_irq_ieob_enable_one(gsi, channel->evt_ring_id); in gsi_channel_start()
871 gsi_irq_ieob_disable_one(gsi, channel->evt_ring_id); in gsi_channel_start()
872 napi_disable(&channel->napi); in gsi_channel_start()
885 if (ret != -EAGAIN) in gsi_channel_stop_retry()
888 } while (retries--); in gsi_channel_stop_retry()
895 struct gsi *gsi = channel->gsi; in __gsi_channel_stop()
898 /* Wait for any underway transactions to complete before stopping. */ in __gsi_channel_stop()
901 /* Prior to IPA v4.0 suspend/resume is not implemented by GSI */ in __gsi_channel_stop()
902 if (suspend && gsi->version < IPA_VERSION_4_0) in __gsi_channel_stop()
905 mutex_lock(&gsi->mutex); in __gsi_channel_stop()
909 mutex_unlock(&gsi->mutex); in __gsi_channel_stop()
917 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_stop()
925 gsi_irq_ieob_disable_one(gsi, channel->evt_ring_id); in gsi_channel_stop()
926 napi_disable(&channel->napi); in gsi_channel_stop()
934 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_reset()
936 mutex_lock(&gsi->mutex); in gsi_channel_reset()
939 /* Due to a hardware quirk we may need to reset RX channels twice. */ in gsi_channel_reset()
940 if (gsi->version < IPA_VERSION_4_0 && !channel->toward_ipa) in gsi_channel_reset()
944 channel->tre_ring.index = 0; in gsi_channel_reset()
948 mutex_unlock(&gsi->mutex); in gsi_channel_reset()
954 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_suspend()
962 napi_synchronize(&channel->napi); in gsi_channel_suspend()
970 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_resume()
978 disable_irq(gsi->irq); in gsi_suspend()
984 enable_irq(gsi->irq); in gsi_resume()
989 struct gsi_channel *channel = &trans->gsi->channel[trans->channel_id]; in gsi_trans_tx_committed()
991 channel->trans_count++; in gsi_trans_tx_committed()
992 channel->byte_count += trans->len; in gsi_trans_tx_committed()
994 trans->trans_count = channel->trans_count; in gsi_trans_tx_committed()
995 trans->byte_count = channel->byte_count; in gsi_trans_tx_committed()
1000 u32 channel_id = trans->channel_id; in gsi_trans_tx_queued()
1001 struct gsi *gsi = trans->gsi; in gsi_trans_tx_queued()
1006 channel = &gsi->channel[channel_id]; in gsi_trans_tx_queued()
1008 byte_count = channel->byte_count - channel->queued_byte_count; in gsi_trans_tx_queued()
1009 trans_count = channel->trans_count - channel->queued_trans_count; in gsi_trans_tx_queued()
1010 channel->queued_byte_count = channel->byte_count; in gsi_trans_tx_queued()
1011 channel->queued_trans_count = channel->trans_count; in gsi_trans_tx_queued()
1017 * gsi_trans_tx_completed() - Report completed TX transactions
1028 * We report this information to the network stack, which uses it to manage
1029 * the rate at which data is sent to hardware.
1033 u32 channel_id = trans->channel_id; in gsi_trans_tx_completed()
1034 struct gsi *gsi = trans->gsi; in gsi_trans_tx_completed()
1039 channel = &gsi->channel[channel_id]; in gsi_trans_tx_completed()
1040 trans_count = trans->trans_count - channel->compl_trans_count; in gsi_trans_tx_completed()
1041 byte_count = trans->byte_count - channel->compl_byte_count; in gsi_trans_tx_completed()
1043 channel->compl_trans_count += trans_count; in gsi_trans_tx_completed()
1044 channel->compl_byte_count += byte_count; in gsi_trans_tx_completed()
1054 channel_mask = ioread32(gsi->virt + GSI_CNTXT_SRC_CH_IRQ_OFFSET); in gsi_isr_chan_ctrl()
1055 iowrite32(channel_mask, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET); in gsi_isr_chan_ctrl()
1062 complete(&gsi->completion); in gsi_isr_chan_ctrl()
1071 event_mask = ioread32(gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET); in gsi_isr_evt_ctrl()
1072 iowrite32(event_mask, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET); in gsi_isr_evt_ctrl()
1079 complete(&gsi->completion); in gsi_isr_evt_ctrl()
1088 dev_err(gsi->dev, "channel %u out of resources\n", channel_id); in gsi_isr_glob_chan_err()
1089 complete(&gsi->completion); in gsi_isr_glob_chan_err()
1094 dev_err(gsi->dev, "channel %u global error ee 0x%08x code 0x%08x\n", in gsi_isr_glob_chan_err()
1103 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_isr_glob_evt_err()
1104 u32 channel_id = gsi_channel_id(evt_ring->channel); in gsi_isr_glob_evt_err()
1106 complete(&gsi->completion); in gsi_isr_glob_evt_err()
1107 dev_err(gsi->dev, "evt_ring for channel %u out of resources\n", in gsi_isr_glob_evt_err()
1113 dev_err(gsi->dev, "event ring %u global error ee %u code 0x%08x\n", in gsi_isr_glob_evt_err()
1127 val = ioread32(gsi->virt + GSI_ERROR_LOG_OFFSET); in gsi_isr_glob_err()
1128 iowrite32(0, gsi->virt + GSI_ERROR_LOG_OFFSET); in gsi_isr_glob_err()
1129 iowrite32(~0, gsi->virt + GSI_ERROR_LOG_CLR_OFFSET); in gsi_isr_glob_err()
1141 dev_err(gsi->dev, "unexpected global error 0x%08x\n", type); in gsi_isr_glob_err()
1150 /* This interrupt is used to handle completions of GENERIC GSI in gsi_isr_gp_int1()
1151 * commands. We use these to allocate and halt channels on the in gsi_isr_gp_int1()
1152 * modem's behalf due to a hardware quirk on IPA v4.2. The modem in gsi_isr_gp_int1()
1153 * "owns" channels even when the AP allocates them, and have no in gsi_isr_gp_int1()
1154 * way of knowing whether a modem channel's state has been changed. in gsi_isr_gp_int1()
1156 * We also use GENERIC commands to enable/disable channel flow in gsi_isr_gp_int1()
1157 * control for IPA v4.2+. in gsi_isr_gp_int1()
1159 * It is recommended that we halt the modem channels we allocated in gsi_isr_gp_int1()
1169 val = ioread32(gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET); in gsi_isr_gp_int1()
1175 gsi->result = 0; in gsi_isr_gp_int1()
1179 gsi->result = -EAGAIN; in gsi_isr_gp_int1()
1183 dev_err(gsi->dev, "global INT1 generic result %u\n", result); in gsi_isr_gp_int1()
1184 gsi->result = -EIO; in gsi_isr_gp_int1()
1188 complete(&gsi->completion); in gsi_isr_gp_int1()
1191 /* Inter-EE interrupt handler */
1196 val = ioread32(gsi->virt + GSI_CNTXT_GLOB_IRQ_STTS_OFFSET); in gsi_isr_glob_ee()
1201 iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_CLR_OFFSET); in gsi_isr_glob_ee()
1211 dev_err(gsi->dev, "unexpected global interrupt 0x%08x\n", val); in gsi_isr_glob_ee()
1219 event_mask = ioread32(gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_OFFSET); in gsi_isr_ieob()
1221 iowrite32(event_mask, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET); in gsi_isr_ieob()
1228 napi_schedule(&gsi->evt_ring[evt_ring_id].channel->napi); in gsi_isr_ieob()
1235 struct device *dev = gsi->dev; in gsi_isr_general()
1238 val = ioread32(gsi->virt + GSI_CNTXT_GSI_IRQ_STTS_OFFSET); in gsi_isr_general()
1239 iowrite32(val, gsi->virt + GSI_CNTXT_GSI_IRQ_CLR_OFFSET); in gsi_isr_general()
1245 * gsi_isr() - Top level GSI interrupt service routine
1247 * @dev_id: GSI pointer supplied to request_irq()
1259 while ((intr_mask = ioread32(gsi->virt + GSI_CNTXT_TYPE_IRQ_OFFSET))) { in gsi_isr()
1283 dev_err(gsi->dev, in gsi_isr()
1291 dev_err(gsi->dev, "interrupt flood\n"); in gsi_isr()
1306 return ret ? : -EINVAL; in gsi_irq_init()
1308 gsi->irq = ret; in gsi_irq_init()
1317 u32 channel_id = event->chid; in gsi_event_trans()
1323 channel = &gsi->channel[channel_id]; in gsi_event_trans()
1324 if (WARN(!channel->gsi, "event has bad channel %u\n", channel_id)) in gsi_event_trans()
1328 tre_offset = lower_32_bits(le64_to_cpu(event->xfer_ptr)); in gsi_event_trans()
1329 tre_index = gsi_ring_index(&channel->tre_ring, tre_offset); in gsi_event_trans()
1340 * gsi_evt_ring_update() - Update transaction state from hardware
1347 * we update transactions to record their actual received lengths.
1350 * transaction to report the number of requests and bytes that have
1361 * Note that @index always refers to an element *within* the event ring.
1365 struct gsi_evt_ring *evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_evt_ring_update()
1366 struct gsi_ring *ring = &evt_ring->ring; in gsi_evt_ring_update()
1372 /* Starting with the oldest un-processed event, determine which in gsi_evt_ring_update()
1376 * associated with a network device, report to the network stack in gsi_evt_ring_update()
1379 old_index = ring->index; in gsi_evt_ring_update()
1382 /* Compute the number of events to process before we wrap, in gsi_evt_ring_update()
1385 event_avail = ring->count - old_index % ring->count; in gsi_evt_ring_update()
1394 if (trans->direction == DMA_FROM_DEVICE) in gsi_evt_ring_update()
1395 trans->len = __le16_to_cpu(event->len); in gsi_evt_ring_update()
1401 /* Move on to the next event and transaction */ in gsi_evt_ring_update()
1402 if (--event_avail) in gsi_evt_ring_update()
1416 struct device *dev = gsi->dev; in gsi_ring_alloc()
1419 /* Hardware requires a 2^n ring size, with alignment equal to size. in gsi_ring_alloc()
1420 * The DMA address returned by dma_alloc_coherent() is guaranteed to in gsi_ring_alloc()
1421 * be a power-of-2 number of pages, which satisfies the requirement. in gsi_ring_alloc()
1423 ring->virt = dma_alloc_coherent(dev, size, &addr, GFP_KERNEL); in gsi_ring_alloc()
1424 if (!ring->virt) in gsi_ring_alloc()
1425 return -ENOMEM; in gsi_ring_alloc()
1427 ring->addr = addr; in gsi_ring_alloc()
1428 ring->count = count; in gsi_ring_alloc()
1429 ring->index = 0; in gsi_ring_alloc()
1434 /* Free a previously-allocated ring */
1437 size_t size = ring->count * GSI_RING_ELEMENT_SIZE; in gsi_ring_free()
1439 dma_free_coherent(gsi->dev, size, ring->virt, ring->addr); in gsi_ring_free()
1447 if (gsi->event_bitmap == ~0U) { in gsi_evt_ring_id_alloc()
1448 dev_err(gsi->dev, "event rings exhausted\n"); in gsi_evt_ring_id_alloc()
1449 return -ENOSPC; in gsi_evt_ring_id_alloc()
1452 evt_ring_id = ffz(gsi->event_bitmap); in gsi_evt_ring_id_alloc()
1453 gsi->event_bitmap |= BIT(evt_ring_id); in gsi_evt_ring_id_alloc()
1458 /* Free a previously-allocated event ring id */
1461 gsi->event_bitmap &= ~BIT(evt_ring_id); in gsi_evt_ring_id_free()
1464 /* Ring a channel doorbell, reporting the first un-filled entry */
1467 struct gsi_ring *tre_ring = &channel->tre_ring; in gsi_channel_doorbell()
1469 struct gsi *gsi = channel->gsi; in gsi_channel_doorbell()
1473 val = gsi_ring_addr(tre_ring, tre_ring->index % tre_ring->count); in gsi_channel_doorbell()
1474 iowrite32(val, gsi->virt + GSI_CH_C_DOORBELL_0_OFFSET(channel_id)); in gsi_channel_doorbell()
1477 /* Consult hardware, move newly completed transactions to completed state */
1480 u32 evt_ring_id = channel->evt_ring_id; in gsi_channel_update()
1481 struct gsi *gsi = channel->gsi; in gsi_channel_update()
1488 evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_channel_update()
1489 ring = &evt_ring->ring; in gsi_channel_update()
1491 /* See if there's anything new to process; if not, we're done. Note in gsi_channel_update()
1492 * that index always refers to an entry *within* the event ring. in gsi_channel_update()
1495 index = gsi_ring_index(ring, ioread32(gsi->virt + offset)); in gsi_channel_update()
1496 if (index == ring->index % ring->count) in gsi_channel_update()
1500 trans = gsi_event_trans(gsi, gsi_ring_virt(ring, index - 1)); in gsi_channel_update()
1513 * gsi_channel_poll_one() - Return a single completed transaction on a channel
1514 * @channel: Channel to be polled
1519 * If no transactions are in completed state, the hardware is consulted to
1521 * moved to completed state and the first such transaction is returned.
1537 * gsi_channel_poll() - NAPI poll function for a channel
1545 * polled is passed to gsi_trans_complete(), to perform remaining
1564 gsi_irq_ieob_enable_one(channel->gsi, channel->evt_ring_id); in gsi_channel_poll()
1576 u32 event_bitmap = GENMASK(BITS_PER_LONG - 1, evt_ring_max); in gsi_event_bitmap_init()
1586 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_setup_one()
1587 u32 evt_ring_id = channel->evt_ring_id; in gsi_channel_setup_one()
1605 if (channel->toward_ipa) in gsi_channel_setup_one()
1606 netif_napi_add_tx(&gsi->dummy_dev, &channel->napi, in gsi_channel_setup_one()
1609 netif_napi_add(&gsi->dummy_dev, &channel->napi, in gsi_channel_setup_one()
1624 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_teardown_one()
1625 u32 evt_ring_id = channel->evt_ring_id; in gsi_channel_teardown_one()
1630 netif_napi_del(&channel->napi); in gsi_channel_teardown_one()
1637 /* We use generic commands only to operate on modem channels. We don't have
1638 * the ability to determine channel state for a modem channel, so we simply
1639 * issue the command and wait for it to complete.
1653 * (to allocate, halt, or enable/disable flow control on a modem in gsi_generic_command()
1658 iowrite32(val, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); in gsi_generic_command()
1661 val = ioread32(gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET); in gsi_generic_command()
1663 iowrite32(val, gsi->virt + GSI_CNTXT_SCRATCH_0_OFFSET); in gsi_generic_command()
1674 iowrite32(BIT(ERROR_INT), gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); in gsi_generic_command()
1677 return gsi->result; in gsi_generic_command()
1679 dev_err(gsi->dev, "GSI generic command %u to channel %u timed out\n", in gsi_generic_command()
1682 return -ETIMEDOUT; in gsi_generic_command()
1699 while (ret == -EAGAIN && retries--); in gsi_modem_channel_halt()
1702 dev_err(gsi->dev, "error %d halting modem channel %u\n", in gsi_modem_channel_halt()
1706 /* Enable or disable flow control for a modem GSI TX channel (IPA v4.2+) */
1716 /* Disabling flow control on IPA v4.11+ can return -EAGAIN if enable in gsi_modem_channel_flow_control()
1717 * is underway. In this case we need to retry the command. in gsi_modem_channel_flow_control()
1719 if (!enable && gsi->version >= IPA_VERSION_4_11) in gsi_modem_channel_flow_control()
1724 while (ret == -EAGAIN && retries--); in gsi_modem_channel_flow_control()
1727 dev_err(gsi->dev, in gsi_modem_channel_flow_control()
1741 mutex_lock(&gsi->mutex); in gsi_channel_setup()
1747 } while (++channel_id < gsi->channel_count); in gsi_channel_setup()
1751 struct gsi_channel *channel = &gsi->channel[channel_id++]; in gsi_channel_setup()
1756 ret = -EINVAL; in gsi_channel_setup()
1757 dev_err(gsi->dev, "channel %u not supported by hardware\n", in gsi_channel_setup()
1758 channel_id - 1); in gsi_channel_setup()
1759 channel_id = gsi->channel_count; in gsi_channel_setup()
1763 /* Allocate modem channels if necessary */ in gsi_channel_setup()
1764 mask = gsi->modem_channel_bitmap; in gsi_channel_setup()
1776 mutex_unlock(&gsi->mutex); in gsi_channel_setup()
1781 /* Compute which modem channels need to be deallocated */ in gsi_channel_setup()
1782 mask ^= gsi->modem_channel_bitmap; in gsi_channel_setup()
1792 while (channel_id--) in gsi_channel_setup()
1795 mutex_unlock(&gsi->mutex); in gsi_channel_setup()
1805 u32 mask = gsi->modem_channel_bitmap; in gsi_channel_teardown()
1808 mutex_lock(&gsi->mutex); in gsi_channel_teardown()
1818 channel_id = gsi->channel_count - 1; in gsi_channel_teardown()
1821 while (channel_id--); in gsi_channel_teardown()
1823 mutex_unlock(&gsi->mutex); in gsi_channel_teardown()
1834 iowrite32(1, gsi->virt + GSI_CNTXT_INTSET_OFFSET); in gsi_irq_setup()
1839 /* Clear all type-specific interrupt masks */ in gsi_irq_setup()
1840 iowrite32(0, gsi->virt + GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET); in gsi_irq_setup()
1841 iowrite32(0, gsi->virt + GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET); in gsi_irq_setup()
1842 iowrite32(0, gsi->virt + GSI_CNTXT_GLOB_IRQ_EN_OFFSET); in gsi_irq_setup()
1843 iowrite32(0, gsi->virt + GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET); in gsi_irq_setup()
1845 /* The inter-EE interrupts are not supported for IPA v3.0-v3.1 */ in gsi_irq_setup()
1846 if (gsi->version > IPA_VERSION_3_1) { in gsi_irq_setup()
1849 /* These registers are in the non-adjusted address range */ in gsi_irq_setup()
1851 iowrite32(0, gsi->virt_raw + offset); in gsi_irq_setup()
1853 iowrite32(0, gsi->virt_raw + offset); in gsi_irq_setup()
1856 iowrite32(0, gsi->virt + GSI_CNTXT_GSI_IRQ_EN_OFFSET); in gsi_irq_setup()
1858 ret = request_irq(gsi->irq, gsi_isr, 0, "gsi", gsi); in gsi_irq_setup()
1860 dev_err(gsi->dev, "error %d requesting \"gsi\" IRQ\n", ret); in gsi_irq_setup()
1867 free_irq(gsi->irq, gsi); in gsi_irq_teardown()
1873 struct device *dev = gsi->dev; in gsi_ring_setup()
1877 if (gsi->version < IPA_VERSION_3_5_1) { in gsi_ring_setup()
1878 /* No HW_PARAM_2 register prior to IPA v3.5.1, assume the max */ in gsi_ring_setup()
1879 gsi->channel_count = GSI_CHANNEL_COUNT_MAX; in gsi_ring_setup()
1880 gsi->evt_ring_count = GSI_EVT_RING_COUNT_MAX; in gsi_ring_setup()
1885 val = ioread32(gsi->virt + GSI_GSI_HW_PARAM_2_OFFSET); in gsi_ring_setup()
1890 return -EINVAL; in gsi_ring_setup()
1893 dev_warn(dev, "limiting to %u channels; hardware supports %u\n", in gsi_ring_setup()
1897 gsi->channel_count = count; in gsi_ring_setup()
1902 return -EINVAL; in gsi_ring_setup()
1906 "limiting to %u event rings; hardware supports %u\n", in gsi_ring_setup()
1910 gsi->evt_ring_count = count; in gsi_ring_setup()
1922 val = ioread32(gsi->virt + GSI_GSI_STATUS_OFFSET); in gsi_setup()
1924 dev_err(gsi->dev, "GSI has not been enabled\n"); in gsi_setup()
1925 return -EIO; in gsi_setup()
1937 iowrite32(0, gsi->virt + GSI_ERROR_LOG_OFFSET); in gsi_setup()
1961 struct gsi *gsi = channel->gsi; in gsi_channel_evt_ring_init()
1968 channel->evt_ring_id = ret; in gsi_channel_evt_ring_init()
1970 evt_ring = &gsi->evt_ring[channel->evt_ring_id]; in gsi_channel_evt_ring_init()
1971 evt_ring->channel = channel; in gsi_channel_evt_ring_init()
1973 ret = gsi_ring_alloc(gsi, &evt_ring->ring, channel->event_count); in gsi_channel_evt_ring_init()
1977 dev_err(gsi->dev, "error %d allocating channel %u event ring\n", in gsi_channel_evt_ring_init()
1980 gsi_evt_ring_id_free(gsi, channel->evt_ring_id); in gsi_channel_evt_ring_init()
1988 u32 evt_ring_id = channel->evt_ring_id; in gsi_channel_evt_ring_exit()
1989 struct gsi *gsi = channel->gsi; in gsi_channel_evt_ring_exit()
1992 evt_ring = &gsi->evt_ring[evt_ring_id]; in gsi_channel_evt_ring_exit()
1993 gsi_ring_free(gsi, &evt_ring->ring); in gsi_channel_evt_ring_exit()
2001 u32 channel_id = data->channel_id; in gsi_channel_data_valid()
2002 struct device *dev = gsi->dev; in gsi_channel_data_valid()
2011 if (data->ee_id != GSI_EE_AP && data->ee_id != GSI_EE_MODEM) { in gsi_channel_data_valid()
2012 dev_err(dev, "bad EE id %u; not AP or modem\n", data->ee_id); in gsi_channel_data_valid()
2016 if (command && !data->toward_ipa) { in gsi_channel_data_valid()
2021 channel_data = &data->channel; in gsi_channel_data_valid()
2023 if (!channel_data->tlv_count || in gsi_channel_data_valid()
2024 channel_data->tlv_count > GSI_TLV_MAX) { in gsi_channel_data_valid()
2026 channel_id, channel_data->tlv_count, GSI_TLV_MAX); in gsi_channel_data_valid()
2030 if (command && IPA_COMMAND_TRANS_TRE_MAX > channel_data->tlv_count) { in gsi_channel_data_valid()
2033 channel_data->tlv_count); in gsi_channel_data_valid()
2037 /* We have to allow at least one maximally-sized transaction to in gsi_channel_data_valid()
2039 * gsi_channel_tre_max() is computed, tre_count has to be almost in gsi_channel_data_valid()
2040 * twice the TLV FIFO size to satisfy this requirement. in gsi_channel_data_valid()
2042 if (channel_data->tre_count < 2 * channel_data->tlv_count - 1) { in gsi_channel_data_valid()
2044 channel_id, channel_data->tlv_count, in gsi_channel_data_valid()
2045 channel_data->tre_count); in gsi_channel_data_valid()
2049 if (!is_power_of_2(channel_data->tre_count)) { in gsi_channel_data_valid()
2051 channel_id, channel_data->tre_count); in gsi_channel_data_valid()
2055 if (!is_power_of_2(channel_data->event_count)) { in gsi_channel_data_valid()
2057 channel_id, channel_data->event_count); in gsi_channel_data_valid()
2074 return -EINVAL; in gsi_channel_init_one()
2077 if (data->channel.tre_count > data->channel.event_count) { in gsi_channel_init_one()
2078 tre_count = data->channel.event_count; in gsi_channel_init_one()
2079 dev_warn(gsi->dev, "channel %u limited to %u TREs\n", in gsi_channel_init_one()
2080 data->channel_id, tre_count); in gsi_channel_init_one()
2082 tre_count = data->channel.tre_count; in gsi_channel_init_one()
2085 channel = &gsi->channel[data->channel_id]; in gsi_channel_init_one()
2088 channel->gsi = gsi; in gsi_channel_init_one()
2089 channel->toward_ipa = data->toward_ipa; in gsi_channel_init_one()
2090 channel->command = command; in gsi_channel_init_one()
2091 channel->trans_tre_max = data->channel.tlv_count; in gsi_channel_init_one()
2092 channel->tre_count = tre_count; in gsi_channel_init_one()
2093 channel->event_count = data->channel.event_count; in gsi_channel_init_one()
2099 ret = gsi_ring_alloc(gsi, &channel->tre_ring, data->channel.tre_count); in gsi_channel_init_one()
2101 dev_err(gsi->dev, "error %d allocating channel %u ring\n", in gsi_channel_init_one()
2102 ret, data->channel_id); in gsi_channel_init_one()
2106 ret = gsi_channel_trans_init(gsi, data->channel_id); in gsi_channel_init_one()
2111 u32 tre_max = gsi_channel_tre_max(gsi, data->channel_id); in gsi_channel_init_one()
2120 gsi_ring_free(gsi, &channel->tre_ring); in gsi_channel_init_one()
2124 channel->gsi = NULL; /* Mark it not (fully) initialized */ in gsi_channel_init_one()
2135 if (channel->command) in gsi_channel_exit_one()
2138 gsi_ring_free(channel->gsi, &channel->tre_ring); in gsi_channel_exit_one()
2150 /* IPA v4.2 requires the AP to allocate channels for the modem */ in gsi_channel_init()
2151 modem_alloc = gsi->version == IPA_VERSION_4_2; in gsi_channel_init()
2153 gsi->event_bitmap = gsi_event_bitmap_init(GSI_EVT_RING_COUNT_MAX); in gsi_channel_init()
2154 gsi->ieob_enabled_bitmap = 0; in gsi_channel_init()
2163 /* Mark modem channels to be allocated (hardware workaround) */ in gsi_channel_init()
2166 gsi->modem_channel_bitmap |= in gsi_channel_init()
2179 while (i--) { in gsi_channel_init()
2183 gsi->modem_channel_bitmap &= ~BIT(data[i].channel_id); in gsi_channel_init()
2186 gsi_channel_exit_one(&gsi->channel[data->channel_id]); in gsi_channel_init()
2195 u32 channel_id = GSI_CHANNEL_COUNT_MAX - 1; in gsi_channel_exit()
2198 gsi_channel_exit_one(&gsi->channel[channel_id]); in gsi_channel_exit()
2199 while (channel_id--); in gsi_channel_exit()
2200 gsi->modem_channel_bitmap = 0; in gsi_channel_exit()
2203 /* Init function for GSI. GSI hardware does not need to be "ready" */
2208 struct device *dev = &pdev->dev; in gsi_init()
2216 gsi->dev = dev; in gsi_init()
2217 gsi->version = version; in gsi_init()
2220 * for the channel NAPI contexts to be associated with. in gsi_init()
2222 init_dummy_netdev(&gsi->dummy_dev); in gsi_init()
2228 return -ENODEV; in gsi_init()
2232 if (res->start > U32_MAX || size > U32_MAX - res->start) { in gsi_init()
2234 return -EINVAL; in gsi_init()
2238 adjust = gsi->version < IPA_VERSION_4_5 ? 0 : GSI_EE_REG_ADJUST; in gsi_init()
2239 if (res->start < adjust) { in gsi_init()
2242 return -EINVAL; in gsi_init()
2245 gsi->virt_raw = ioremap(res->start, size); in gsi_init()
2246 if (!gsi->virt_raw) { in gsi_init()
2247 dev_err(dev, "unable to remap \"gsi\" memory\n"); in gsi_init()
2248 return -ENOMEM; in gsi_init()
2251 gsi->virt = gsi->virt_raw - adjust; in gsi_init()
2253 init_completion(&gsi->completion); in gsi_init()
2263 mutex_init(&gsi->mutex); in gsi_init()
2268 iounmap(gsi->virt_raw); in gsi_init()
2276 mutex_destroy(&gsi->mutex); in gsi_exit()
2278 iounmap(gsi->virt_raw); in gsi_exit()
2287 * doing that led to the hardware reporting exhaustion of event ring
2289 * would be (tre_count - 1).
2292 * sized to be a little larger than this maximum, to allow resource
2293 * allocations to always be contiguous. The number of entries in a
2295 * tends to nearly double the memory allocated for it. Reducing the
2297 * a pool to avoid crossing that power-of-2 boundary, and this can
2303 struct gsi_channel *channel = &gsi->channel[channel_id]; in gsi_channel_tre_max()
2305 /* Hardware limit is channel->tre_count - 1 */ in gsi_channel_tre_max()
2306 return channel->tre_count - (channel->trans_tre_max - 1); in gsi_channel_tre_max()