Lines Matching +full:xs +full:- +full:phy
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
41 /* 0x0001 - 0x0003: reserved */
49 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
55 #define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */
59 #define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */
60 #define B0_MDRL 0x002c /* r/w lower 16-bit of mem. data reg */
63 #define B0_ST3U 0x0034 /* read upper 16-bit of status reg 3 */
64 #define B0_ST3L 0x0038 /* read lower 16-bit of status reg 3 */
65 #define B0_IMSK3U 0x003c /* r/w upper 16-bit of IMSK reg 3 */
66 #define B0_IMSK3L 0x0040 /* r/w lower 16-bit of IMSK reg 3 */
88 * - completely empty (this is the RAP Block window)
106 /* 0x010a - 0x010b: reserved */
112 #define B2_FAR 0x0110 /* 32 bit Flash-Prom Address Register/Counter */
113 #define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */
114 /* 0x0115 - 0x0117: reserved */
117 /* 0x011a - 0x011f: reserved */
122 /* 0x012a - 0x012f: reserved */
127 /* 0x013a - 0x013f: reserved */
146 /* 0x016a - 0x017f: reserved */
174 /* 0x0238 - 0x023f: reserved */
189 /* 0x0270 - 0x027c: reserved */
209 /* 0x02b8 - 0x02bc: reserved */
210 #define B5_XS_D 0x02c0 /* 4*32 bit current transmit Descriptor (xs) */
211 #define B5_XS_DA 0x02d0 /* 32 bit current tx desc address (xs) */
212 #define B5_XS_AC 0x02d4 /* 32 bit current transmit Address Count(xs) */
213 #define B5_XS_BC 0x02d8 /* 32 bit current transmit Byte Counter (xs) */
214 #define B5_XS_CSR 0x02dc /* 32 bit BMU Control/Status Register (xs) */
215 #define B5_XS_F 0x02e0 /* 32 bit flag register (xs) */
216 #define B5_XS_T1 0x02e4 /* 32 bit Test Register 1 (xs) */
217 #define B5_XS_T1_TR 0x02e4 /* 8 bit Test Register 1 TR (xs) */
218 #define B5_XS_T1_WR 0x02e5 /* 8 bit Test Register 1 WR (xs) */
219 #define B5_XS_T1_RD 0x02e6 /* 8 bit Test Register 1 RD (xs) */
220 #define B5_XS_T1_SV 0x02e7 /* 8 bit Test Register 1 SV (xs) */
221 #define B5_XS_T2 0x02e8 /* 32 bit Test Register 2 (xs) */
222 #define B5_XS_T3 0x02ec /* 32 bit Test Register 3 (xs) */
225 /* 0x02f8 - 0x02fc: reserved */
230 /* External PLC-S registers (SN2 compatibility for DV) */
237 /* DAS PLC-S Registers */
240 * Bank 8 - 15
244 /*---------------------------------------------------------------------------*/
332 #define IS_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */
333 #define IS_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */
334 #define IS_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */
381 #define IRQ_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */
382 #define IRQ_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */
383 #define IRQ_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */
385 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
411 /* B2_FAR 32 bit Flash-Prom Address Register/Counter */
414 /* B2_FDP 8 bit Flash-Prom Data Port */
534 /* B5_XS_D 4*32 bit current receive Descriptor (xs) */
535 /* B5_XS_DA 32 bit current rec desc address (xs) */
536 /* B5_XS_AC 32 bit current receive Address Count (xs) */
537 /* B5_XS_BC 32 bit current receive Byte Counter (xs) */
538 /* B5_XS_CSR 32 bit BMU Control/Status Register (xs) */
539 /* B5_XS_F 32 bit flag register (xs) */
540 /* B5_XS_T1 32 bit Test Register 1 (xs) */
541 /* B5_XS_T2 32 bit Test Register 2 (xs) */
542 /* B5_XS_T3 32 bit Test Register 3 (xs) */
694 * physical address offset + IO-Port base address
697 #define ADDR(a) (char far *) smc->hw.iop+(a)
698 #define ADDRS(smc,a) (char far *) (smc)->hw.iop+(a)
700 #define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \
701 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
702 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
703 #define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \
704 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
705 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
759 #define STI_FBI() outpd(ADDR(B0_IMSK),smc->hw.is_imask)
761 #define STI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask)
765 #define STI_FBI_SMP(smc,iop) outpd((iop)+B0_IMSK,(smc)->hw.is_imask)
768 /*--------------------------------------------------------------------------*/
810 * PHY Port A (PA) = PLC 1
811 * With SuperNet 3 PHY-A and PHY S are identical.
832 /* read FORMAC+ 32-bit status register */
842 /* read FORMAC+ 32-bit status register */