Lines Matching +full:a +full:- +full:8
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
31 * Note: The temperature and voltage sensors are relocated on a different
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
49 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
55 #define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */
59 #define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */
60 #define B0_MDRL 0x002c /* r/w lower 16-bit of mem. data reg */
63 #define B0_ST3U 0x0034 /* read upper 16-bit of status reg 3 */
64 #define B0_ST3L 0x0038 /* read lower 16-bit of status reg 3 */
65 #define B0_IMSK3U 0x003c /* r/w upper 16-bit of IMSK reg 3 */
66 #define B0_IMSK3L 0x0040 /* r/w lower 16-bit of IMSK reg 3 */
71 #define B0_CNTRL_A 0x0050 /* control register A (r/w) */
76 #define B0_STATUS_A 0x0060 /* status register A (read only) */
83 #define B0_XA_CSR 0x0078 /* 32 bit BMU control/status reg (a xmit q) */
88 * - completely empty (this is the RAP Block window)
95 #define B2_MAC_0 0x0100 /* 8 bit MAC address Byte 0 */
96 #define B2_MAC_1 0x0101 /* 8 bit MAC address Byte 1 */
97 #define B2_MAC_2 0x0102 /* 8 bit MAC address Byte 2 */
98 #define B2_MAC_3 0x0103 /* 8 bit MAC address Byte 3 */
99 #define B2_MAC_4 0x0104 /* 8 bit MAC address Byte 4 */
100 #define B2_MAC_5 0x0105 /* 8 bit MAC address Byte 5 */
101 #define B2_MAC_6 0x0106 /* 8 bit MAC address Byte 6 (== 0) (DV) */
102 #define B2_MAC_7 0x0107 /* 8 bit MAC address Byte 7 (== 0) (DV) */
104 #define B2_CONN_TYP 0x0108 /* 8 bit Connector type */
105 #define B2_PMD_TYP 0x0109 /* 8 bit PMD type */
106 /* 0x010a - 0x010b: reserved */
108 #define B2_E_0 0x010c /* 8 bit EPROM Byte 0 */
109 #define B2_E_1 0x010d /* 8 bit EPROM Byte 1 */
110 #define B2_E_2 0x010e /* 8 bit EPROM Byte 2 */
111 #define B2_E_3 0x010f /* 8 bit EPROM Byte 3 */
112 #define B2_FAR 0x0110 /* 32 bit Flash-Prom Address Register/Counter */
113 #define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */
114 /* 0x0115 - 0x0117: reserved */
115 #define B2_LD_CRTL 0x0118 /* 8 bit loader control */
116 #define B2_LD_TEST 0x0119 /* 8 bit loader test */
117 /* 0x011a - 0x011f: reserved */
120 #define B2_TI_CRTL 0x0128 /* 8 bit Timer control */
121 #define B2_TI_TEST 0x0129 /* 8 Bit Timer Test */
122 /* 0x012a - 0x012f: reserved */
125 #define B2_WDOG_CRTL 0x0138 /* 8 bit Watchdog control */
126 #define B2_WDOG_TEST 0x0139 /* 8 Bit Watchdog Test */
127 /* 0x013a - 0x013f: reserved */
130 #define B2_RTM_CRTL 0x0148 /* 8 bit RTM control */
131 #define B2_RTM_TEST 0x0149 /* 8 Bit RTM Test */
135 #define B2_CTRL_2 0x0154 /* (ML) 8 bit Control Register 2 */
136 #define B2_IFACE_REG 0x0155 /* (ML) 8 bit Interface Register */
138 #define B2_TST_CTRL_2 0x0157 /* (ML) 8 bit Test Control Register 2 */
144 #define B2_IRQ_MOD_CTRL 0x0168 /* (ML) 8 bit IRQ Moderation Timer Control */
145 #define B2_IRQ_MOD_TEST 0x0169 /* (ML) 8 bit IRQ Moderation Timer Test */
146 /* 0x016a - 0x017f: reserved */
152 * This is a copy of the Configuration register file (lower half)
166 #define B4_R1_T1_TR 0x0224 /* 8 bit Test Register 1 TR */
167 #define B4_R1_T1_WR 0x0225 /* 8 bit Test Register 1 WR */
168 #define B4_R1_T1_RD 0x0226 /* 8 bit Test Register 1 RD */
169 #define B4_R1_T1_SV 0x0227 /* 8 bit Test Register 1 SV */
174 /* 0x0238 - 0x023f: reserved */
183 #define B4_R2_T1_TR 0x0264 /* 8 bit Test Register 1 TR (q2) */
184 #define B4_R2_T1_WR 0x0265 /* 8 bit Test Register 1 WR (q2) */
185 #define B4_R2_T1_RD 0x0266 /* 8 bit Test Register 1 RD (q2) */
186 #define B4_R2_T1_SV 0x0267 /* 8 bit Test Register 1 SV (q2) */
189 /* 0x0270 - 0x027c: reserved */
201 #define B5_XA_T1_TR 0x02a4 /* 8 bit Test Register 1 TR (xa) */
202 #define B5_XA_T1_WR 0x02a5 /* 8 bit Test Register 1 WR (xa) */
203 #define B5_XA_T1_RD 0x02a6 /* 8 bit Test Register 1 RD (xa) */
204 #define B5_XA_T1_SV 0x02a7 /* 8 bit Test Register 1 SV (xa) */
209 /* 0x02b8 - 0x02bc: reserved */
217 #define B5_XS_T1_TR 0x02e4 /* 8 bit Test Register 1 TR (xs) */
218 #define B5_XS_T1_WR 0x02e5 /* 8 bit Test Register 1 WR (xs) */
219 #define B5_XS_T1_RD 0x02e6 /* 8 bit Test Register 1 RD (xs) */
220 #define B5_XS_T1_SV 0x02e7 /* 8 bit Test Register 1 SV (xs) */
225 /* 0x02f8 - 0x02fc: reserved */
230 /* External PLC-S registers (SN2 compatibility for DV) */
237 /* DAS PLC-S Registers */
240 * Bank 8 - 15
244 /*---------------------------------------------------------------------------*/
250 /* B0_CTRL 8 bit control register */
260 /* B0_DAS 8 Bit control register (DAS) */
269 /* B0_LED 8 Bit LED register */
279 #define LED_GA_ON LED_2_ON /* S port = A port */
280 #define LED_GA_OFF LED_2_OFF /* S port = A port */
286 /* B0_TST_CTRL 8 bit test control register */
324 #define IS_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */
373 #define IRQ_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */
385 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
388 /* B0_XA_CSR 32 bit BMU control/status reg (a xmit q ) */
392 /* B2_MAC_0 8 bit MAC address Byte 0 */
393 /* B2_MAC_1 8 bit MAC address Byte 1 */
394 /* B2_MAC_2 8 bit MAC address Byte 2 */
395 /* B2_MAC_3 8 bit MAC address Byte 3 */
396 /* B2_MAC_4 8 bit MAC address Byte 4 */
397 /* B2_MAC_5 8 bit MAC address Byte 5 */
398 /* B2_MAC_6 8 bit MAC address Byte 6 (== 0) (DV) */
399 /* B2_MAC_7 8 bit MAC address Byte 7 (== 0) (DV) */
401 /* B2_CONN_TYP 8 bit Connector type */
402 /* B2_PMD_TYP 8 bit PMD type */
406 /* B2_E_0 8 bit EPROM Byte 0 */
407 /* B2_E_1 8 bit EPROM Byte 1 */
408 /* B2_E_2 8 bit EPROM Byte 2 */
409 /* B2_E_3 8 bit EPROM Byte 3 */
411 /* B2_FAR 32 bit Flash-Prom Address Register/Counter */
414 /* B2_FDP 8 bit Flash-Prom Data Port */
416 /* B2_LD_CRTL 8 bit loader control */
419 /* B2_LD_TEST 8 bit loader test */
427 /* B2_TI_CRTL 8 bit Timer control */
428 /* B2_TI_TEST 8 Bit Timer Test */
431 /* B2_WDOG_CRTL 8 bit Watchdog control */
432 /* B2_WDOG_TEST 8 Bit Watchdog Test */
435 /* B2_RTM_CRTL 8 bit RTM control */
436 /* B2_RTM_TEST 8 Bit RTM Test */
437 /* B2_<TIM>_CRTL 8 bit <TIM> control */
440 /* B2_IRQ_MOD_CTRL 8 bit IRQ Moderation Timer Control (ML) */
441 /* B2_IRQ_MOD_TEST 8 bit IRQ Moderation Timer Test (ML) */
448 /* B2_<TIM>_TEST 8 Bit <TIM> Test */
455 /* B2_CTRL_2 0x0154 (ML) 8 bit Control Register 2 */
463 /* B2_IFACE_REG 0x0155 (ML) 8 bit Interface Register */
470 /* B2_TST_CTRL_2 0x0157 (ML) 8 bit Test Control Register 2 */
483 /* Bit 5.. 8: reserved */
557 #define CSR_TRANS_RST (1L<<8) /* Bit 8: Reset Transfer SM */
579 /* Bit 8..15: reserved */
587 #define SM_CRTL_WR (0xffL<<8) /* Bit 15..8: Control Write Desc SM */
590 /* B4_<xx>_T1_TR 8 bit Test Register 1 TR (xx) */
591 /* B4_<xx>_T1_WR 8 bit Test Register 1 WR (xx) */
592 /* B4_<xx>_T1_RD 8 bit Test Register 1 RD (xx) */
593 /* B4_<xx>_T1_SV 8 bit Test Register 1 SV (xx) */
642 /* Bit 31..8: reserved */
654 /* Bit 31..8: reserved */
666 #define FMA(a) (0x0400|((a)<<2)) /* FORMAC+ (r/w) (SN3) */ argument
667 #define P1(a) (0x0380|((a)<<2)) /* PLC1 (r/w) (DAS) */ argument
668 #define P2(a) (0x0600|((a)<<2)) /* PLC2 (r/w) (covered by the SN3) */ argument
669 #define PRA(a) (B2_MAC_0 + (a)) /* configuration PROM (MAC address) */ argument
674 #define MAX_PAGES 0x20000L /* Every byte has a single page */
694 * physical address offset + IO-Port base address
697 #define ADDR(a) (char far *) smc->hw.iop+(a) argument
698 #define ADDRS(smc,a) (char far *) (smc)->hw.iop+(a) argument
700 #define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \ argument
701 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
702 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
703 #define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \ argument
704 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
705 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
709 * Define a macro to access the configuration space
711 #define PCI_C(a) ADDR(B3_CFG_SPC + (a)) /* PCI Config Space */ argument
713 #define EXT_R(a) ADDR(B6_EXT_REG + (a)) /* External Registers */ argument
721 #define SKFDDI_PSZ 8 /* address PROM size */
723 #define FM_A(a) ADDR(FMA(a)) /* FORMAC Plus physical addr */ argument
724 #define P1_A(a) ADDR(P1(a)) /* PLC1 (r/w) */ argument
725 #define P2_A(a) ADDR(P2(a)) /* PLC2 (r/w) (DAS) */ argument
726 #define PR_A(a) ADDR(PRA(a)) /* config. PROM (MAC address) */ argument
731 #define READ_PROM(a) ((u_char)inp(a)) argument
759 #define STI_FBI() outpd(ADDR(B0_IMSK),smc->hw.is_imask)
761 #define STI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask)
765 #define STI_FBI_SMP(smc,iop) outpd((iop)+B0_IMSK,(smc)->hw.is_imask)
768 /*--------------------------------------------------------------------------*/
810 * PHY Port A (PA) = PLC 1
811 * With SuperNet 3 PHY-A and PHY S are identical.
832 /* read FORMAC+ 32-bit status register */
842 /* read FORMAC+ 32-bit status register */
851 /* timer access over data bus bit 8..15 */
852 #define OUT_82c54_TIMER(port,val) outpw(TI_A(port),(val)<<8)
853 #define IN_82c54_TIMER(port) ((inpw(TI_A(port))>>8) & 0xff)
869 (p == PA) ? "A" : "B", iev) ;\