Lines Matching +full:0 +full:- +full:32
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
34 #define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */
38 * Bank 0
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
47 #define B0_IMSK 0x000c /* 32 bit Interrupt mask register */
49 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
50 #define B0_CMDREG1 0x0010 /* write command reg 1 instruction */
51 #define B0_CMDREG2 0x0014 /* write command reg 2 instruction */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
55 #define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */
57 #define B0_MARR 0x0020 /* r/w the memory read addr register */
58 #define B0_MARW 0x0024 /* r/w the memory write addr register*/
59 #define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */
60 #define B0_MDRL 0x002c /* r/w lower 16-bit of mem. data reg */
62 #define B0_MDREG3 0x0030 /* r/w Mode Register 3 */
63 #define B0_ST3U 0x0034 /* read upper 16-bit of status reg 3 */
64 #define B0_ST3L 0x0038 /* read lower 16-bit of status reg 3 */
65 #define B0_IMSK3U 0x003c /* r/w upper 16-bit of IMSK reg 3 */
66 #define B0_IMSK3L 0x0040 /* r/w lower 16-bit of IMSK reg 3 */
67 #define B0_IVR 0x0044 /* read Interrupt Vector register */
68 #define B0_IMR 0x0048 /* r/w Interrupt mask register */
69 /* 0x4c Hidden */
71 #define B0_CNTRL_A 0x0050 /* control register A (r/w) */
72 #define B0_CNTRL_B 0x0054 /* control register B (r/w) */
73 #define B0_INTR_MASK 0x0058 /* interrupt mask (r/w) */
74 #define B0_XMIT_VECTOR 0x005c /* transmit vector register (r/w) */
76 #define B0_STATUS_A 0x0060 /* status register A (read only) */
77 #define B0_STATUS_B 0x0064 /* status register B (read only) */
78 #define B0_CNTRL_C 0x0068 /* control register C (r/w) */
79 #define B0_MDREG1 0x006c /* r/w Mode Register 1 */
81 #define B0_R1_CSR 0x0070 /* 32 bit BMU control/status reg (rec q 1) */
82 #define B0_R2_CSR 0x0074 /* 32 bit BMU control/status reg (rec q 2)(DV)*/
83 #define B0_XA_CSR 0x0078 /* 32 bit BMU control/status reg (a xmit q) */
84 #define B0_XS_CSR 0x007c /* 32 bit BMU control/status reg (s xmit q) */
88 * - completely empty (this is the RAP Block window)
95 #define B2_MAC_0 0x0100 /* 8 bit MAC address Byte 0 */
96 #define B2_MAC_1 0x0101 /* 8 bit MAC address Byte 1 */
97 #define B2_MAC_2 0x0102 /* 8 bit MAC address Byte 2 */
98 #define B2_MAC_3 0x0103 /* 8 bit MAC address Byte 3 */
99 #define B2_MAC_4 0x0104 /* 8 bit MAC address Byte 4 */
100 #define B2_MAC_5 0x0105 /* 8 bit MAC address Byte 5 */
101 #define B2_MAC_6 0x0106 /* 8 bit MAC address Byte 6 (== 0) (DV) */
102 #define B2_MAC_7 0x0107 /* 8 bit MAC address Byte 7 (== 0) (DV) */
104 #define B2_CONN_TYP 0x0108 /* 8 bit Connector type */
105 #define B2_PMD_TYP 0x0109 /* 8 bit PMD type */
106 /* 0x010a - 0x010b: reserved */
108 #define B2_E_0 0x010c /* 8 bit EPROM Byte 0 */
109 #define B2_E_1 0x010d /* 8 bit EPROM Byte 1 */
110 #define B2_E_2 0x010e /* 8 bit EPROM Byte 2 */
111 #define B2_E_3 0x010f /* 8 bit EPROM Byte 3 */
112 #define B2_FAR 0x0110 /* 32 bit Flash-Prom Address Register/Counter */
113 #define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */
114 /* 0x0115 - 0x0117: reserved */
115 #define B2_LD_CRTL 0x0118 /* 8 bit loader control */
116 #define B2_LD_TEST 0x0119 /* 8 bit loader test */
117 /* 0x011a - 0x011f: reserved */
118 #define B2_TI_INI 0x0120 /* 32 bit Timer init value */
119 #define B2_TI_VAL 0x0124 /* 32 bit Timer value */
120 #define B2_TI_CRTL 0x0128 /* 8 bit Timer control */
121 #define B2_TI_TEST 0x0129 /* 8 Bit Timer Test */
122 /* 0x012a - 0x012f: reserved */
123 #define B2_WDOG_INI 0x0130 /* 32 bit Watchdog init value */
124 #define B2_WDOG_VAL 0x0134 /* 32 bit Watchdog value */
125 #define B2_WDOG_CRTL 0x0138 /* 8 bit Watchdog control */
126 #define B2_WDOG_TEST 0x0139 /* 8 Bit Watchdog Test */
127 /* 0x013a - 0x013f: reserved */
128 #define B2_RTM_INI 0x0140 /* 32 bit RTM init value */
129 #define B2_RTM_VAL 0x0144 /* 32 bit RTM value */
130 #define B2_RTM_CRTL 0x0148 /* 8 bit RTM control */
131 #define B2_RTM_TEST 0x0149 /* 8 Bit RTM Test */
133 #define B2_TOK_COUNT 0x014c /* (ML) 32 bit Token Counter */
134 #define B2_DESC_ADDR_H 0x0150 /* (ML) 32 bit Desciptor Base Addr Reg High */
135 #define B2_CTRL_2 0x0154 /* (ML) 8 bit Control Register 2 */
136 #define B2_IFACE_REG 0x0155 /* (ML) 8 bit Interface Register */
137 /* 0x0156: reserved */
138 #define B2_TST_CTRL_2 0x0157 /* (ML) 8 bit Test Control Register 2 */
139 #define B2_I2C_CTRL 0x0158 /* (ML) 32 bit I2C Control Register */
140 #define B2_I2C_DATA 0x015c /* (ML) 32 bit I2C Data Register */
142 #define B2_IRQ_MOD_INI 0x0160 /* (ML) 32 bit IRQ Moderation Timer Init Reg. */
143 #define B2_IRQ_MOD_VAL 0x0164 /* (ML) 32 bit IRQ Moderation Timer Value */
144 #define B2_IRQ_MOD_CTRL 0x0168 /* (ML) 8 bit IRQ Moderation Timer Control */
145 #define B2_IRQ_MOD_TEST 0x0169 /* (ML) 8 bit IRQ Moderation Timer Test */
146 /* 0x016a - 0x017f: reserved */
154 #define B3_CFG_SPC 0x180
159 #define B4_R1_D 0x0200 /* 4*32 bit current receive Descriptor */
160 #define B4_R1_DA 0x0210 /* 32 bit current rec desc address */
161 #define B4_R1_AC 0x0214 /* 32 bit current receive Address Count */
162 #define B4_R1_BC 0x0218 /* 32 bit current receive Byte Counter */
163 #define B4_R1_CSR 0x021c /* 32 bit BMU Control/Status Register */
164 #define B4_R1_F 0x0220 /* 32 bit flag register */
165 #define B4_R1_T1 0x0224 /* 32 bit Test Register 1 */
166 #define B4_R1_T1_TR 0x0224 /* 8 bit Test Register 1 TR */
167 #define B4_R1_T1_WR 0x0225 /* 8 bit Test Register 1 WR */
168 #define B4_R1_T1_RD 0x0226 /* 8 bit Test Register 1 RD */
169 #define B4_R1_T1_SV 0x0227 /* 8 bit Test Register 1 SV */
170 #define B4_R1_T2 0x0228 /* 32 bit Test Register 2 */
171 #define B4_R1_T3 0x022c /* 32 bit Test Register 3 */
172 #define B4_R1_DA_H 0x0230 /* (ML) 32 bit Curr Rx Desc Address High */
173 #define B4_R1_AC_H 0x0234 /* (ML) 32 bit Curr Addr Counter High dword */
174 /* 0x0238 - 0x023f: reserved */
176 #define B4_R2_D 0x0240 /* 4*32 bit current receive Descriptor (q2) */
177 #define B4_R2_DA 0x0250 /* 32 bit current rec desc address (q2) */
178 #define B4_R2_AC 0x0254 /* 32 bit current receive Address Count (q2) */
179 #define B4_R2_BC 0x0258 /* 32 bit current receive Byte Counter (q2) */
180 #define B4_R2_CSR 0x025c /* 32 bit BMU Control/Status Register (q2) */
181 #define B4_R2_F 0x0260 /* 32 bit flag register (q2) */
182 #define B4_R2_T1 0x0264 /* 32 bit Test Register 1 (q2) */
183 #define B4_R2_T1_TR 0x0264 /* 8 bit Test Register 1 TR (q2) */
184 #define B4_R2_T1_WR 0x0265 /* 8 bit Test Register 1 WR (q2) */
185 #define B4_R2_T1_RD 0x0266 /* 8 bit Test Register 1 RD (q2) */
186 #define B4_R2_T1_SV 0x0267 /* 8 bit Test Register 1 SV (q2) */
187 #define B4_R2_T2 0x0268 /* 32 bit Test Register 2 (q2) */
188 #define B4_R2_T3 0x026c /* 32 bit Test Register 3 (q2) */
189 /* 0x0270 - 0x027c: reserved */
194 #define B5_XA_D 0x0280 /* 4*32 bit current transmit Descriptor (xa) */
195 #define B5_XA_DA 0x0290 /* 32 bit current tx desc address (xa) */
196 #define B5_XA_AC 0x0294 /* 32 bit current tx Address Count (xa) */
197 #define B5_XA_BC 0x0298 /* 32 bit current tx Byte Counter (xa) */
198 #define B5_XA_CSR 0x029c /* 32 bit BMU Control/Status Register (xa) */
199 #define B5_XA_F 0x02a0 /* 32 bit flag register (xa) */
200 #define B5_XA_T1 0x02a4 /* 32 bit Test Register 1 (xa) */
201 #define B5_XA_T1_TR 0x02a4 /* 8 bit Test Register 1 TR (xa) */
202 #define B5_XA_T1_WR 0x02a5 /* 8 bit Test Register 1 WR (xa) */
203 #define B5_XA_T1_RD 0x02a6 /* 8 bit Test Register 1 RD (xa) */
204 #define B5_XA_T1_SV 0x02a7 /* 8 bit Test Register 1 SV (xa) */
205 #define B5_XA_T2 0x02a8 /* 32 bit Test Register 2 (xa) */
206 #define B5_XA_T3 0x02ac /* 32 bit Test Register 3 (xa) */
207 #define B5_XA_DA_H 0x02b0 /* (ML) 32 bit Curr Tx Desc Address High */
208 #define B5_XA_AC_H 0x02b4 /* (ML) 32 bit Curr Addr Counter High dword */
209 /* 0x02b8 - 0x02bc: reserved */
210 #define B5_XS_D 0x02c0 /* 4*32 bit current transmit Descriptor (xs) */
211 #define B5_XS_DA 0x02d0 /* 32 bit current tx desc address (xs) */
212 #define B5_XS_AC 0x02d4 /* 32 bit current transmit Address Count(xs) */
213 #define B5_XS_BC 0x02d8 /* 32 bit current transmit Byte Counter (xs) */
214 #define B5_XS_CSR 0x02dc /* 32 bit BMU Control/Status Register (xs) */
215 #define B5_XS_F 0x02e0 /* 32 bit flag register (xs) */
216 #define B5_XS_T1 0x02e4 /* 32 bit Test Register 1 (xs) */
217 #define B5_XS_T1_TR 0x02e4 /* 8 bit Test Register 1 TR (xs) */
218 #define B5_XS_T1_WR 0x02e5 /* 8 bit Test Register 1 WR (xs) */
219 #define B5_XS_T1_RD 0x02e6 /* 8 bit Test Register 1 RD (xs) */
220 #define B5_XS_T1_SV 0x02e7 /* 8 bit Test Register 1 SV (xs) */
221 #define B5_XS_T2 0x02e8 /* 32 bit Test Register 2 (xs) */
222 #define B5_XS_T3 0x02ec /* 32 bit Test Register 3 (xs) */
223 #define B5_XS_DA_H 0x02f0 /* (ML) 32 bit Curr Tx Desc Address High */
224 #define B5_XS_AC_H 0x02f4 /* (ML) 32 bit Curr Addr Counter High dword */
225 /* 0x02f8 - 0x02fc: reserved */
230 /* External PLC-S registers (SN2 compatibility for DV) */
232 #define B6_EXT_REG 0x300
237 /* DAS PLC-S Registers */
240 * Bank 8 - 15
244 /*---------------------------------------------------------------------------*/
248 #define RAP_RAP 0x0f /* Bit 3..0: 0 = block0, .., f = block15 */
258 #define CTRL_RST_SET (1<<0) /* Bit 0: Set Software reset */
261 #define BUS_CLOCK (1<<7) /* Bit 7: (ML) Bus Clock 0/1 = 33/66MHz */
262 #define BUS_SLOT_SZ (1<<6) /* Bit 6: (ML) Slot Size 0/1 = 32/64 bit slot*/
264 #define DAS_AVAIL (1<<3) /* Bit 3: 1 = DAS, 0 = SAS */
265 #define DAS_BYP_ST (1<<2) /* Bit 2: 1 = avail,SAS, 0 = not avail */
267 #define DAS_BYP_RMV (1<<0) /* Bit 0: 1 = remove Bypass */
276 #define LED_0_OFF (1<<0) /* Bit 0: 1 = switch LED_0 off */
294 #define TST_CFG_WRITE_OFF (1<<0) /* Bit 0: dis configuration reg. WR */
296 /* B0_ISRC 32 bit Interrupt source register */
334 #define IS_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */
339 #define ALL_IRSR 0x01ffff77L /* (DV) */
340 #define ALL_IRSR_ML 0x0ffff077L /* (ML) */
343 /* B0_IMSK 32 bit Interrupt mask register */
383 #define IRQ_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */
385 /* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
386 /* B0_R1_CSR 32 bit BMU control/status reg (rec q 1 ) */
387 /* B0_R2_CSR 32 bit BMU control/status reg (rec q 2 ) */
388 /* B0_XA_CSR 32 bit BMU control/status reg (a xmit q ) */
389 /* B0_XS_CSR 32 bit BMU control/status reg (s xmit q ) */
392 /* B2_MAC_0 8 bit MAC address Byte 0 */
398 /* B2_MAC_6 8 bit MAC address Byte 6 (== 0) (DV) */
399 /* B2_MAC_7 8 bit MAC address Byte 7 (== 0) (DV) */
406 /* B2_E_0 8 bit EPROM Byte 0 */
411 /* B2_FAR 32 bit Flash-Prom Address Register/Counter */
412 #define FAR_ADDR 0x1ffffL /* Bit 16..0: FPROM Address mask */
414 /* B2_FDP 8 bit Flash-Prom Data Port */
423 #define LD_START (1<<0) /* Bit 0: Start loading FPROM */
425 /* B2_TI_INI 32 bit Timer init value */
426 /* B2_TI_VAL 32 bit Timer value */
429 /* B2_WDOG_INI 32 bit Watchdog init value */
430 /* B2_WDOG_VAL 32 bit Watchdog value */
433 /* B2_RTM_INI 32 bit RTM init value */
434 /* B2_RTM_VAL 32 bit RTM value */
438 /* B2_IRQ_MOD_INI 32 bit IRQ Moderation Timer Init Reg. (ML) */
439 /* B2_IRQ_MOD_VAL 32 bit IRQ Moderation Timer Value (ML) */
447 #define TIM_CL_IRQ (1<<0) /* Bit 0: Clear Timer IRQ (TI,WDOG,RTM) */
451 #define TIM_T_STEP (1<<0) /* Bit 0: Test step (TI,WDOG,RTM,IRQ_MOD) */
453 /* B2_TOK_COUNT 0x014c (ML) 32 bit Token Counter */
454 /* B2_DESC_ADDR_H 0x0150 (ML) 32 bit Desciptor Base Addr Reg High */
455 /* B2_CTRL_2 0x0154 (ML) 8 bit Control Register 2 */
461 #define CTRL_STOP_MAST (1<<0) /* Bit 0: Command Bit to stop the master*/
463 /* B2_IFACE_REG 0x0155 (ML) 8 bit Interface Register */
467 #define IF_I2C_CLK (1<<0) /* Bit 0: I2C Clock Port */
469 /* 0x0156: reserved */
470 /* B2_TST_CTRL_2 0x0157 (ML) 8 bit Test Control Register 2 */
477 #define TST_FRC_APERR_2M64 (1<<0) /* Bit 0: AddrPERR on 2. phase */
479 /* B2_I2C_CTRL 0x0158 (ML) 32 bit I2C Control Register */
481 #define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be read/written*/
482 #define I2C_DEV_SEL (0x7fL<<9) /* Bit 9..15: I2C Device Select */
486 #define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smaller*/
494 #define I2C_STOP_BIT (1<<0) /* Bit 0: Interrupt I2C transfer */
503 #define I2C_ADDR_TEMP 0x90 /* I2C Address Temperature Sensor */
505 /* B2_I2C_DATA 0x015c (ML) 32 bit I2C Data Register */
507 /* B4_R1_D 4*32 bit current receive Descriptor (q1) */
508 /* B4_R1_DA 32 bit current rec desc address (q1) */
509 /* B4_R1_AC 32 bit current receive Address Count (q1) */
510 /* B4_R1_BC 32 bit current receive Byte Counter (q1) */
511 /* B4_R1_CSR 32 bit BMU Control/Status Register (q1) */
512 /* B4_R1_F 32 bit flag register (q1) */
513 /* B4_R1_T1 32 bit Test Register 1 (q1) */
514 /* B4_R1_T2 32 bit Test Register 2 (q1) */
515 /* B4_R1_T3 32 bit Test Register 3 (q1) */
516 /* B4_R2_D 4*32 bit current receive Descriptor (q2) */
517 /* B4_R2_DA 32 bit current rec desc address (q2) */
518 /* B4_R2_AC 32 bit current receive Address Count (q2) */
519 /* B4_R2_BC 32 bit current receive Byte Counter (q2) */
520 /* B4_R2_CSR 32 bit BMU Control/Status Register (q2) */
521 /* B4_R2_F 32 bit flag register (q2) */
522 /* B4_R2_T1 32 bit Test Register 1 (q2) */
523 /* B4_R2_T2 32 bit Test Register 2 (q2) */
524 /* B4_R2_T3 32 bit Test Register 3 (q2) */
525 /* B5_XA_D 4*32 bit current receive Descriptor (xa) */
526 /* B5_XA_DA 32 bit current rec desc address (xa) */
527 /* B5_XA_AC 32 bit current receive Address Count (xa) */
528 /* B5_XA_BC 32 bit current receive Byte Counter (xa) */
529 /* B5_XA_CSR 32 bit BMU Control/Status Register (xa) */
530 /* B5_XA_F 32 bit flag register (xa) */
531 /* B5_XA_T1 32 bit Test Register 1 (xa) */
532 /* B5_XA_T2 32 bit Test Register 2 (xa) */
533 /* B5_XA_T3 32 bit Test Register 3 (xa) */
534 /* B5_XS_D 4*32 bit current receive Descriptor (xs) */
535 /* B5_XS_DA 32 bit current rec desc address (xs) */
536 /* B5_XS_AC 32 bit current receive Address Count (xs) */
537 /* B5_XS_BC 32 bit current receive Byte Counter (xs) */
538 /* B5_XS_CSR 32 bit BMU Control/Status Register (xs) */
539 /* B5_XS_F 32 bit flag register (xs) */
540 /* B5_XS_T1 32 bit Test Register 1 (xs) */
541 /* B5_XS_T2 32 bit Test Register 2 (xs) */
542 /* B5_XS_T3 32 bit Test Register 3 (xs) */
543 /* B5_<xx>_CSR 32 bit BMU Control/Status Register (xx) */
563 #define CSR_IRQ_CL_C (1L<<0) /* Bit 0: Clear ERR IRQ */
571 /* B5_<xx>_F 32 bit flag register (xx) */
578 #define F_FIFO_LEVEL (0x1fL<<16) /* Bit 16..22:(ML) # of Qwords in FIFO*/
580 #define F_ML_WATER_M 0x0000ffL /* Bit 0.. 7:(ML) Watermark */
581 #define FLAG_WATER 0x00001fL /* Bit 4..0:(DV) Level of req data tr.*/
583 /* B5_<xx>_T1 32 bit Test Register 1 (xx) */
585 #define SM_CRTL_SV (0xffL<<24) /* Bit 31..24: Control Supervisor SM */
586 #define SM_CRTL_RD (0xffL<<16) /* Bit 23..16: Control Read Desc SM */
587 #define SM_CRTL_WR (0xffL<<8) /* Bit 15..8: Control Write Desc SM */
588 #define SM_CRTL_TR (0xffL<<0) /* Bit 7..0: Control Transfer SM */
595 #define SM_STATE 0xf0 /* Bit 7..4: State which shall be loaded */
596 #define SM_LOAD 0x08 /* Bit 3: Load the SM with SM_STATE */
597 #define SM_TEST_ON 0x04 /* Bit 2: Switch on SM Test Mode */
598 #define SM_TEST_OFF 0x02 /* Bit 1: Go off the Test Mode */
599 #define SM_STEP 0x01 /* Bit 0: Step the State Machine */
602 #define SM_SV_IDLE 0x0 /* Supervisor Idle Tr/Re */
603 #define SM_SV_RES_START 0x1 /* Supervisor Res_Start Tr/Re */
604 #define SM_SV_GET_DESC 0x3 /* Supervisor Get_Desc Tr/Re */
605 #define SM_SV_CHECK 0x2 /* Supervisor Check Tr/Re */
606 #define SM_SV_MOV_DATA 0x6 /* Supervisor Move_Data Tr/Re */
607 #define SM_SV_PUT_DESC 0x7 /* Supervisor Put_Desc Tr/Re */
608 #define SM_SV_SET_IRQ 0x5 /* Supervisor Set_Irq Tr/Re */
610 #define SM_RD_IDLE 0x0 /* Read Desc. Idle Tr/Re */
611 #define SM_RD_LOAD 0x1 /* Read Desc. Load Tr/Re */
612 #define SM_RD_WAIT_TC 0x3 /* Read Desc. Wait_TC Tr/Re */
613 #define SM_RD_RST_EOF 0x6 /* Read Desc. Reset_EOF Re */
614 #define SM_RD_WDONE_R 0x2 /* Read Desc. Wait_Done Re */
615 #define SM_RD_WDONE_T 0x4 /* Read Desc. Wait_Done Tr */
617 #define SM_TR_IDLE 0x0 /* Trans. Data Idle Tr/Re */
618 #define SM_TR_LOAD 0x3 /* Trans. Data Load Tr/Re */
619 #define SM_TR_LOAD_R_ML 0x1 /* Trans. Data Load /Re (ML) */
620 #define SM_TR_WAIT_TC 0x2 /* Trans. Data Wait_TC Tr/Re */
621 #define SM_TR_WDONE 0x4 /* Trans. Data Wait_Done Tr/Re */
623 #define SM_WR_IDLE 0x0 /* Write Desc. Idle Tr/Re */
624 #define SM_WR_ABLEN 0x1 /* Write Desc. Act_Buf_Length Tr/Re */
625 #define SM_WR_LD_A4 0x2 /* Write Desc. Load_A4 Re */
626 #define SM_WR_RES_OWN 0x2 /* Write Desc. Res_OWN Tr */
627 #define SM_WR_WAIT_EOF 0x3 /* Write Desc. Wait_EOF Re */
628 #define SM_WR_LD_N2C_R 0x4 /* Write Desc. Load_N2C Re */
629 #define SM_WR_WAIT_TC_R 0x5 /* Write Desc. Wait_TC Re */
630 #define SM_WR_WAIT_TC4 0x6 /* Write Desc. Wait_TC4 Re */
631 #define SM_WR_LD_A_T 0x6 /* Write Desc. Load_A Tr */
632 #define SM_WR_LD_A_R 0x7 /* Write Desc. Load_A Re */
633 #define SM_WR_WAIT_TC_T 0x7 /* Write Desc. Wait_TC Tr */
634 #define SM_WR_LD_N2C_T 0xc /* Write Desc. Load_N2C Tr */
635 #define SM_WR_WDONE_T 0x9 /* Write Desc. Wait_Done Tr */
636 #define SM_WR_WDONE_R 0xc /* Write Desc. Wait_Done Re */
637 #define SM_WR_LD_D_AD 0xe /* Write Desc. Load_Dumr_A Re (ML) */
638 #define SM_WR_WAIT_D_TC 0xf /* Write Desc. Wait_Dumr_TC Re (ML) */
640 /* B5_<xx>_T2 32 bit Test Register 2 (xx) */
650 #define TEST_STEP01 (1<<0) /* Bit 0: Inc AC/Dec BC by 1 */
652 /* B5_<xx>_T3 32 bit Test Register 3 (xx) */
660 #define T3_VRAM (3<<0) /* Bit 1..0: Virtual RAM buffer Address */
666 #define FMA(a) (0x0400|((a)<<2)) /* FORMAC+ (r/w) (SN3) */
667 #define P1(a) (0x0380|((a)<<2)) /* PLC1 (r/w) (DAS) */
668 #define P2(a) (0x0600|((a)<<2)) /* PLC2 (r/w) (covered by the SN3) */
674 #define MAX_PAGES 0x20000L /* Every byte has a single page */
680 #define BMU_OWN (1UL<<31) /* OWN bit: 0 == host, 1 == adapter */
690 #define BMU_CHECK 0x00550000L /* To identify the control word */
691 #define BMU_BBC 0x0000FFFFL /* R/T Buffer Byte Count */
694 * physical address offset + IO-Port base address
697 #define ADDR(a) (char far *) smc->hw.iop+(a)
698 #define ADDRS(smc,a) (char far *) (smc)->hw.iop+(a)
700 #define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \
701 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
702 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
703 #define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \
704 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
705 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
718 #define SA_MAC (0) /* start addr. MAC_AD within the PROM */
719 #define PRA_OFF (0) /* offset correction when 4th byte reading */
753 #define CLI_FBI() outpd(ADDR(B0_IMSK),0)
755 #define CLI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),0)
759 #define STI_FBI() outpd(ADDR(B0_IMSK),smc->hw.is_imask)
761 #define STI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask)
764 #define CLI_FBI_SMP(iop) outpd((iop)+B0_IMSK,0)
765 #define STI_FBI_SMP(smc,iop) outpd((iop)+B0_IMSK,(smc)->hw.is_imask)
768 /*--------------------------------------------------------------------------*/
776 #define MAX_TRANS (0x0fff)
781 #define MST_8259 (0x20)
782 #define SLV_8259 (0xA0)
792 #define MAC_AD 0x405a0000
811 * With SuperNet 3 PHY-A and PHY S are identical.
832 /* read FORMAC+ 32-bit status register */
842 /* read FORMAC+ 32-bit status register */
853 #define IN_82c54_TIMER(port) ((inpw(TI_A(port))>>8) & 0xff)
857 #define DB_MAC(mac,st) {if (debug_mac & 0x1)\
859 if (debug_mac & 0x2)\
860 printf("\tMAC %d status 0x%08lx\n",mac,st) ;\
861 if (debug_mac & 0x4)\
865 #define DB_PLC(p,iev) { if (debug_plc & 0x1)\
867 if (debug_plc & 0x2)\
868 printf("\tPLC %s Int 0x%04x\n", \
870 if (debug_plc & 0x4)\
874 #define DB_TIMER() { if (debug_timer & 0x1)\
876 if (debug_timer & 0x2)\