1 // SPDX-License-Identifier: GPL-2.0
3  * MDIO bus driver for the Xilinx Axi Ethernet device
6  * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
7  * Copyright (c) 2010 - 2011 PetaLogix
9  * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
37 		    ((u32)lp->mii_clk_div | XAE_MDIO_MC_MDIOEN_MASK));  in axienet_mdio_mdc_enable()
51  * axienet_mdio_read - MDIO interface read function
52  * @bus:	Pointer to mii bus structure
56  * Return:	The register contents on success, -ETIMEDOUT on a timeout
62 static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg)  in axienet_mdio_read()  argument
66 	struct axienet_local *lp = bus->priv;  in axienet_mdio_read()
92 	dev_dbg(lp->dev, "axienet_mdio_read(phy_id=%i, reg=%x) == %x\n",  in axienet_mdio_read()
100  * axienet_mdio_write - MDIO interface write function
101  * @bus:	Pointer to mii bus structure
106  * Return:	0 on success, -ETIMEDOUT on a timeout
112 static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg,  in axienet_mdio_write()  argument
116 	struct axienet_local *lp = bus->priv;  in axienet_mdio_write()
118 	dev_dbg(lp->dev, "axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n",  in axienet_mdio_write()
148  * axienet_mdio_enable - MDIO hardware setup function
151  * Return:	0 on success, -ETIMEDOUT on a timeout.
160 	lp->mii_clk_div = 0;  in axienet_mdio_enable()
162 	if (lp->axi_clk) {  in axienet_mdio_enable()
163 		host_clock = clk_get_rate(lp->axi_clk);  in axienet_mdio_enable()
167 		/* Legacy fallback: detect CPU clock frequency and use as AXI  in axienet_mdio_enable()
168 		 * bus clock frequency. This only works on certain platforms.  in axienet_mdio_enable()
172 			netdev_warn(lp->ndev, "Could not find CPU device node.\n");  in axienet_mdio_enable()
175 			int ret = of_property_read_u32(np1, "clock-frequency",  in axienet_mdio_enable()
178 				netdev_warn(lp->ndev, "CPU clock-frequency property not found.\n");  in axienet_mdio_enable()
183 		netdev_info(lp->ndev, "Setting assumed host clock to %u\n",  in axienet_mdio_enable()
206 	 * clk_div >= (fHOST / 5000000) - 1  in axienet_mdio_enable()
209 	 * "clock-frequency" from the CPU  in axienet_mdio_enable()
212 	lp->mii_clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;  in axienet_mdio_enable()
218 		lp->mii_clk_div++;  in axienet_mdio_enable()
220 	netdev_dbg(lp->ndev,  in axienet_mdio_enable()
222 		   lp->mii_clk_div, host_clock);  in axienet_mdio_enable()
224 	axienet_iow(lp, XAE_MDIO_MC_OFFSET, lp->mii_clk_div | XAE_MDIO_MC_MDIOEN_MASK);  in axienet_mdio_enable()
230  * axienet_mdio_disable - MDIO hardware disable function
241  * axienet_mdio_setup - MDIO setup function
244  * Return:	0 on success, -ETIMEDOUT on a timeout, -ENOMEM when
245  *		mdiobus_alloc (to allocate memory for mii bus structure) fails.
253 	struct mii_bus *bus;  in axienet_mdio_setup()  local
260 	bus = mdiobus_alloc();  in axienet_mdio_setup()
261 	if (!bus)  in axienet_mdio_setup()
262 		return -ENOMEM;  in axienet_mdio_setup()
264 	snprintf(bus->id, MII_BUS_ID_SIZE, "axienet-%.8llx",  in axienet_mdio_setup()
265 		 (unsigned long long)lp->regs_start);  in axienet_mdio_setup()
267 	bus->priv = lp;  in axienet_mdio_setup()
268 	bus->name = "Xilinx Axi Ethernet MDIO";  in axienet_mdio_setup()
269 	bus->read = axienet_mdio_read;  in axienet_mdio_setup()
270 	bus->write = axienet_mdio_write;  in axienet_mdio_setup()
271 	bus->parent = lp->dev;  in axienet_mdio_setup()
272 	lp->mii_bus = bus;  in axienet_mdio_setup()
274 	mdio_node = of_get_child_by_name(lp->dev->of_node, "mdio");  in axienet_mdio_setup()
275 	ret = of_mdiobus_register(bus, mdio_node);  in axienet_mdio_setup()
278 		mdiobus_free(bus);  in axienet_mdio_setup()
279 		lp->mii_bus = NULL;  in axienet_mdio_setup()
287  * axienet_mdio_teardown - MDIO remove function
290  * Unregisters the MDIO and frees any associate memory for mii bus.
294 	mdiobus_unregister(lp->mii_bus);  in axienet_mdio_teardown()
295 	mdiobus_free(lp->mii_bus);  in axienet_mdio_teardown()
296 	lp->mii_bus = NULL;  in axienet_mdio_teardown()