Lines Matching +full:phy +full:- +full:pma

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
147 #define XAE_IFGP_OFFSET		0x00000008 /* Tx Inter-frame gap adjustment*/
157 #define XAE_PPST_OFFSET		0x00000030 /* PCS PMA Soft Temac Status Reg */
200 /* Transmit inter-frame gap adjustment value */
216 #define XAE_INT_PHYRSTCMPLT_MASK	0x00000100 /* Phy Reset complete */
234 /* In-Band FCS enable (FCS not stripped) */
250 /* In-Band FCS enable (FCS not generated) */
254 /* Inter-frame gap adjustment enable */
276 #define XAE_PHYC_RGMIIHD_MASK		0x00000002 /* RGMII Half-duplex */
290 #define XAE_MDIO_MCR_PHYAD_MASK		0x1F000000 /* Phy Address Mask */
291 #define XAE_MDIO_MCR_PHYAD_SHIFT	24	   /* Phy Address Shift */
342 /* Xilinx PCS/PMA PHY register for switching 1000BaseX or SGMII */
347  * struct axidma_bd - Axi Dma buffer descriptor layout
382  * struct axienet_local - axienet private per device data
388  * @pcs_phy:	Reference to PCS/PMA PHY if used
389  * @pcs:	phylink pcs structure for PCS PHY
391  * @axi_clk:	AXI4-Lite bus clock
392  * @misc_clks:	Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
424  * @phy_mode:	Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
505  * struct axiethernet_option - Used to set axi ethernet hardware options
517  * axienet_ior - Memory mapped Axi Ethernet register read
527 	return ioread32(lp->regs + offset);  in axienet_ior()
537 	if (lp->mii_bus)  in axienet_lock_mii()
538 		mutex_lock(&lp->mii_bus->mdio_lock);  in axienet_lock_mii()
543 	if (lp->mii_bus)  in axienet_unlock_mii()
544 		mutex_unlock(&lp->mii_bus->mdio_lock);  in axienet_unlock_mii()
548  * axienet_iow - Memory mapped Axi Ethernet register write
559 	iowrite32(value, lp->regs + offset);  in axienet_iow()
563  * axienet_dma_out32 - Memory mapped Axi DMA register write.
575 	iowrite32(value, lp->dma_regs + reg);  in axienet_dma_out32()
580  * axienet_dma_out64 - Memory mapped Axi DMA register write.
591 	iowrite64(value, lp->dma_regs + reg);  in axienet_dma_out64()
597 	if (lp->features & XAE_FEATURE_DMA_64BIT)  in axienet_dma_out_addr()