Lines Matching +full:12 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define MAX_NETDEV_NUM 2 /* Maximum # of net-device */
12 #define MAC_INT_DAISY_MODE_CHG BIT(31) /* Daisy Mode Change */
13 #define MAC_INT_IP_CHKSUM_ERR BIT(23) /* IP Checksum Append Error */
14 #define MAC_INT_WDOG_TIMER1_EXP BIT(22) /* Watchdog Timer1 Expired */
15 #define MAC_INT_WDOG_TIMER0_EXP BIT(21) /* Watchdog Timer0 Expired */
16 #define MAC_INT_INTRUDER_ALERT BIT(20) /* Atruder Alert */
17 #define MAC_INT_PORT_ST_CHG BIT(19) /* Port Status Change */
18 #define MAC_INT_BC_STORM BIT(18) /* Broad Cast Storm */
19 #define MAC_INT_MUST_DROP_LAN BIT(17) /* Global Queue Exhausted */
20 #define MAC_INT_GLOBAL_QUE_FULL BIT(16) /* Global Queue Full */
21 #define MAC_INT_TX_SOC_PAUSE_ON BIT(15) /* Soc Port TX Pause On */
22 #define MAC_INT_RX_SOC_QUE_FULL BIT(14) /* Soc Port Out Queue Full */
23 #define MAC_INT_TX_LAN1_QUE_FULL BIT(9) /* Port 1 Out Queue Full */
24 #define MAC_INT_TX_LAN0_QUE_FULL BIT(8) /* Port 0 Out Queue Full */
25 #define MAC_INT_RX_L_DESCF BIT(7) /* Low Priority Descriptor Full */
26 #define MAC_INT_RX_H_DESCF BIT(6) /* High Priority Descriptor Full */
27 #define MAC_INT_RX_DONE_L BIT(5) /* RX Low Priority Done */
28 #define MAC_INT_RX_DONE_H BIT(4) /* RX High Priority Done */
29 #define MAC_INT_TX_DONE_L BIT(3) /* TX Low Priority Done */
30 #define MAC_INT_TX_DONE_H BIT(2) /* TX High Priority Done */
31 #define MAC_INT_TX_DES_ERR BIT(1) /* TX Descriptor Error */
32 #define MAC_INT_RX_DES_ERR BIT(0) /* Rx Descriptor Error */
48 #define MAC_ADDR_LOOKUP_IDLE BIT(2)
49 #define MAC_SEARCH_NEXT_ADDR BIT(1)
50 #define MAC_BEGIN_SEARCH_ADDR BIT(0)
54 #define MAC_R_PORT_MAP GENMASK(13, 12)
58 #define MAC_R_PROXY BIT(3)
59 #define MAC_R_MC_INGRESS BIT(2)
60 #define MAC_AT_TABLE_END BIT(1)
61 #define MAC_AT_DATA_READY BIT(0)
64 #define MAC_W_PORT_MAP GENMASK(13, 12)
65 #define MAC_W_LAN_PORT_1 BIT(13)
66 #define MAC_W_LAN_PORT_0 BIT(12)
68 #define MAC_W_CPU_PORT_1 BIT(11)
69 #define MAC_W_CPU_PORT_0 BIT(10)
72 #define MAC_W_PROXY BIT(3)
73 #define MAC_W_MC_INGRESS BIT(2)
74 #define MAC_W_MAC_DONE BIT(1)
75 #define MAC_W_MAC_CMD BIT(0)
101 #define MAC_EN_SOC1_AGING BIT(15)
102 #define MAC_EN_SOC0_AGING BIT(14)
103 #define MAC_DIS_LRN_SOC1 BIT(13)
104 #define MAC_DIS_LRN_SOC0 BIT(12)
105 #define MAC_EN_CRC_SOC1 BIT(9)
106 #define MAC_EN_CRC_SOC0 BIT(8)
107 #define MAC_DIS_SOC1_CPU BIT(7)
108 #define MAC_DIS_SOC0_CPU BIT(6)
109 #define MAC_DIS_BC2CPU_P1 BIT(5)
110 #define MAC_DIS_BC2CPU_P0 BIT(4)
112 #define MAC_DIS_MC2CPU_P1 BIT(3)
113 #define MAC_DIS_MC2CPU_P0 BIT(2)
118 #define MAC_DIS_PORT1 BIT(25)
119 #define MAC_DIS_PORT0 BIT(24)
120 #define MAC_DIS_RMC2CPU_P1 BIT(17)
121 #define MAC_DIS_RMC2CPU_P0 BIT(16)
122 #define MAC_EN_FLOW_CTL_P1 BIT(9)
123 #define MAC_EN_FLOW_CTL_P0 BIT(8)
124 #define MAC_EN_BACK_PRESS_P1 BIT(1)
125 #define MAC_EN_BACK_PRESS_P0 BIT(0)
128 #define MAC_DIS_SA_LRN_P1 BIT(9)
129 #define MAC_DIS_SA_LRN_P0 BIT(8)
132 #define MAC_EN_AGING_P1 BIT(9)
133 #define MAC_EN_AGING_P0 BIT(8)
141 #define MAC_LED_ACT_HI BIT(28)
146 #define MAC_CPU_PHY_REG_ADDR GENMASK(12, 8)
151 #define MAC_PHY_RD_RDY BIT(1)
152 #define MAC_PHY_WT_DONE BIT(0)
158 #define MAC_FORCE_RMII_EN_1 BIT(7)
159 #define MAC_FORCE_RMII_EN_0 BIT(6)
165 #define MAC_TRIG_L_SOC0 BIT(1)
166 #define MAC_TRIG_H_SOC0 BIT(0)
180 #define TXD_OWN BIT(31)
182 #define TXD_SOP BIT(25) /* start of a packet */
183 #define TXD_EOP BIT(24) /* end of a packet */
184 #define TXD_VLAN GENMASK(17, 12)
187 #define TXD_EOR BIT(31) /* end of ring */
188 #define TXD_BUF_LEN2 GENMASK(22, 12)
193 #define RXD_OWN BIT(31)
195 #define RXD_TCP_UDP_CHKSUM BIT(23)
196 #define RXD_PROXY BIT(22)
198 #define RXD_VLAN_TAG BIT(19)
199 #define RXD_IP_CHKSUM BIT(18)
201 #define RXD_PKT_SP GENMASK(14, 12) /* packet source port */
204 #define RXD_EOR BIT(31) /* end of ring */
205 #define RXD_BUF_LEN2 GENMASK(22, 12)