Lines Matching +full:no +full:- +full:read +full:- +full:rollover
1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
85 #define INTR_RX_BUF_UNAVAIL 0x00000020 /* no more receive buffers.
89 #define INTR_RX_COMP_FULL 0x00000080 /* no more room in completion
104 len of non-reassembly pkt
143 /* top level interrupt bits that are cleared during read of REG_INTR_STATUS_ALIAS.
159 set if no ACK64# during ABS64 cycle
162 no read retry after 2^15 clocks */
166 #define PCI_ERR_BIM_DMA_READ 0x10 /* BIM received 0 count DMA read req.
183 #define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */
185 #define BIM_CFG_32BIT 0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */
205 * reset. poll until TX and RX read back as 0's for completion.
216 reset when hot-swap is being
232 #define SW_RESET_RDPCI_SM_MASK 0x00300000 /* read pci state bits:
236 #define SW_RESET_RDARB_SM_MASK 0x00C00000 /* read arbitration state bits:
253 /* Cassini only. 64-bit register used to check PCI datapath. when read,
254 * value written has both lower and upper 32-bit halves rotated to the right
255 * one bit position. e.g., FFFFFFFF FFFFFFFF -> 7FFFFFFF 7FFFFFFF
279 /* access 24 entry BIM read and write buffers. put address in REG_BIM_BUFFER_ADDR
280 * and read/write from/to it REG_BIM_BUFFER_DATA_LOW and _DATA_HI.
286 #define BIM_BUFFER_ADDR_MASK 0x3F /* index (0 - 23) of buffer */
288 read buffer access = 0 */
293 /* set BIM_RAM_BIST_START to start built-in self test for BIM read buffer.
294 * bit auto-clears when done with status read from _SUMMARY and _PASS bits.
296 #define REG_BIM_RAM_BIST 0x102C /* BIM RAM (read buffer) BIST
298 #define BIM_RAM_BIST_RD_START 0x01 /* start BIST for BIM read buffer */
302 #define BIM_RAM_BIST_RD_PASS 0x04 /* summary BIST pass status for read
307 #define BIM_RAM_BIST_RD_LOW_PASS 0x10 /* read low bank passes BIST */
308 #define BIM_RAM_BIST_RD_HI_PASS 0x20 /* read high bank passes BIST */
361 #define REG_PLUS_INTRN_MASK(x) (REG_PLUS_INTR_MASK_1 + ((x) - 1)*16)
363 * all of the alternate (2-4) INTR registers while _1 corresponds to only
380 #define REG_PLUS_INTRN_STATUS(x) (REG_PLUS_INTR_STATUS_1 + ((x) - 1)*16)
386 #define REG_PLUS_ALIASN_CLEAR(x) (REG_PLUS_ALIAS_CLEAR_1 + ((x) - 1)*16)
390 #define REG_PLUS_INTRN_STATUS_ALIAS(x) (REG_PLUS_INTR_STATUS_ALIAS_1 + ((x) - 1)*16)
420 #define MAX_TX_RINGS_MASK (MAX_TX_RINGS - 1)
457 #define TX_CFG_INTR_COMPWB_DIS 0x20000000 /* disable pre-interrupt completion
474 /* 11-bit counters that point to next location in FIFO to be loaded/retrieved.
481 #define REG_TX_FIFO_READ_PTR 0x201C /* TX FIFO read pointer */
482 #define REG_TX_FIFO_SHADOW_READ_PTR 0x2020 /* TX FIFO shadow read
485 /* (ro) 11-bit up/down counter w/ # of frames currently in TX FIFO */
504 /* 64-bit pointer to the transmit data buffer. only the 50 LSB are incremented
513 * tx descr is available within the cache line being read, cassini will
521 /* values of TX_COMPLETE_1-4 are written. each completion register
524 * TX_ALL interrupts. at all other times, the most up-to-date index values
549 * be 2KB-aligned. */
555 /* 16-bit registers hold weights for the weighted round-robin of the
560 * these registers causes a queue1 pre-emption with all historical bw
562 * pre-emption/re-allocation of network bandwidth
583 /* 9-bit register controls BIST of TX FIFO. bit set indicates that the BIST
602 * free ring size = (1 << n)*32 -> [32 - 8k]
603 * completion ring size = (1 << n)*128 -> [128 - 32k], n < 9
643 * [--------------------------------------------------------------] page
645 * |--------------| = PAGE_SIZE_BUFFER_STRIDE
684 /* 11-bit counter points to next location in RX FIFO to be loaded/read.
686 * DEFAULT: 0x0. generated on 64-bit boundaries.
689 #define REG_RX_FIFO_READ_PTR 0x400C /* RX FIFO read pointer */
692 #define REG_RX_IPP_FIFO_SHADOW_READ_PTR 0x4014 /* RX IPP FIFO shadow read
694 #define REG_RX_IPP_FIFO_READ_PTR 0x400C /* RX IPP FIFO read
695 pointer. (8-bit counter) */
756 #define RX_DEBUG_INTR_READ_PTR_MASK 0x30000000 /* interrupt read ptr of the
762 * XOFF PAUSE uses pause time value pre-programmed in the Send PAUSE MAC reg
785 /* 13-bit register used to control RX desc fetching and intr generation. if 4+
786 * valid RX descriptors are available, Cassini will read 4 at a time.
788 * be a multiple of 4 (N % 4 = 0). first desc should be cache-line aligned.
793 /* 8KB aligned 64-bit pointer to the base of the RX free/completion rings.
794 * lower 13 bits of the low register are hard-wired to 0.
804 /* 13-bit register indicate desc used by cassini for receive frames. used
813 * entries to hw, set TAIL = HEAD. if HEAD and TAIL indicate that no
815 * generated to indicate no more entries are available. sw can use
823 /* values used for receive interrupt blanking. loaded each time the ISR is read
827 for ISR read */
832 the ISR was read. 0 = no
838 ISR was read.
840 clocks (125MHz). 0 = no
920 /* next location in RX CTRL FIFO that will be loaded w/ data from RX IPP/read
926 #define REG_RX_CTRL_FIFO_READ_PTR 0x4068 /* (ro) RX control FIFO read
930 * read.
934 alias read */
938 read. 0 = no
944 ISR read. each count
946 (125MHz). 0 = no
963 /* diagnostic assess to RX CTRL FIFO. 8-bit FIFO_ADDR holds address of
964 * 81 bit control entry and 6 bit flow id. LOW and MID are both 32-bit
965 * accesses. HI is 7-bits with 6-bit flow id and 1 bit control
992 /* 64-bit pointer to receive data buffer in host memory used for headers and
1007 /* PIO diagnostic access to RX reassembly DMA Table RAM. 6-bit register holds
1008 * one of 64 79-bit locations in the RX Reassembly DMA table and the addr of
1028 /* 8KB aligned 64-bit pointer to base of RX rings. lower 13 bits hardwired to
1039 #define REG_PLUS_RX_CBN_LOW(x) (REG_PLUS_RX_CB1_LOW + 8*((x) - 1))
1040 #define REG_PLUS_RX_CBN_HI(x) (REG_PLUS_RX_CB1_HI + 8*((x) - 1))
1048 #define REG_PLUS_RX_COMPN_HEAD(x) (REG_PLUS_RX_COMP1_HEAD + 8*((x) - 1))
1049 #define REG_PLUS_RX_COMPN_TAIL(x) (REG_PLUS_RX_COMP1_TAIL + 8*((x) - 1))
1074 /* access to RX Instruction RAM. 5-bit register/counter holds addr
1075 * of 39 bit entry to be read/written. 32 LSB in _DATA_LOW. 7 MSB in _DATA_HI.
1082 #define HP_INSTR_RAM_ADDR_MASK 0x01F /* 5-bit mask */
1117 * 11-bit register. Data fills the LSB portion of bus if less than 32 bits.
1119 * RAM bytes = 4*(x - 1) + [3:0]. e.g., 0 -> [3:0], 31 -> [123:120]
1120 * FLOWDB: write DATA_RAM_FDB register and then read/write FDB1-12 to access
1131 read/write */
1132 #define HP_DATA_RAM_FDB_FDB_MASK 0x3F00 /* 1 of 64 353-bit locations
1136 /* HP flow database registers: 1 - 12, 0x415C - 0x4188, 4 8-bit bytes
1176 #define HP_STATUS2_FORCE_TCP_NOCHECK 0x00000200 /* force tcp no payload
1184 #define HP_STATUS2_NO_ASSIST 0x00000020 /* no assist */
1189 #define HP_STATUS2_TCP_NOCHECK 0x00000001 /* tcp no payload chk */
1226 /* reset bits are set using a PIO write and self-cleared after the command
1243 /* bit set indicates that event occurred. auto-cleared when status register
1244 * is read and have corresponding mask bits in mask register. events will
1259 #define MAC_TX_COLL_NORMAL 0x0008 /* rollover of the normal
1261 #define MAC_TX_COLL_EXCESS 0x0010 /* rollover of the excessive
1263 #define MAC_TX_COLL_LATE 0x0020 /* rollover of the late
1265 #define MAC_TX_COLL_FIRST 0x0040 /* rollover of the first
1267 #define MAC_TX_DEFER_TIMER 0x0080 /* rollover of the defer
1269 #define MAC_TX_PEAK_ATTEMPTS 0x0100 /* rollover of the peak
1277 #define MAC_RX_FRAME_COUNT 0x0004 /* rollover of receive frame
1279 #define MAC_RX_ALIGN_ERR 0x0008 /* rollover of alignment
1281 #define MAC_RX_CRC_ERR 0x0010 /* rollover of crc error
1283 #define MAC_RX_LEN_ERR 0x0020 /* rollover of length
1285 #define MAC_RX_VIOL_ERR 0x0040 /* rollover of code
1319 * the delay for a 1518-byte frame on a 100Mbps network is 125us.
1321 * NOTE: on half-duplex 1Gbps, TX_CFG_CARRIER_EXTEND and
1342 Rx-to-TX IPG. after
1352 back-to-pack (Tx-to-Tx
1408 for half-duplex at 1Gbps,
1413 * CRC is layer 2. however, non-reassembly packets will still contain the CRC
1453 to half-duplex 1Gbps */
1489 or in half-duplex SERDES
1491 in half-duplex when
1502 #define REG_MAC_IPG0 0x6040 /* inter-packet gap0 reg.
1504 #define REG_MAC_IPG1 0x6044 /* inter-packet gap1 reg
1506 #define REG_MAC_IPG2 0x6048 /* inter-packet gap2 reg
1549 /* mac address registers: 0 - 44, 0x6080 - 0x6130, 4 8-bit bytes.
1554 * 3*x 16MSB of alt MAC addr 1-15 [47:32] of DA field
1580 mask reg. 8-bit reg
1586 /* hash table registers: 0 - 15, 0x6160 - 0x619C, 4 8-bit bytes
1587 * 16-bit registers contain bits of the hash table.
1588 * reg x -> [16*(15 - x) + 15 : 16*(15 - x)].
1589 * e.g., 15 -> [15:0], 0 -> [255:240]
1595 * overflow. recommended initialization: 0x0000. most are 16-bits except
1619 10-bit register used as a
1623 programmed after power-on
1636 /* 27-bit register has the current state for key state machines in the MAC */
1655 /** MIF registers. the MIF can be programmed in either bit-bang or
1658 #define REG_MIF_BIT_BANG_CLOCK 0x6200 /* MIF bit-bang clock.
1659 1 -> 0 will generate a
1660 rising edge. 0 -> 1 will
1662 #define REG_MIF_BIT_BANG_DATA 0x6204 /* MIF bit-bang data. 1-bit
1664 #define REG_MIF_BIT_BANG_OUTPUT_EN 0x6208 /* MIF bit-bang output
1669 /* 32-bit register serves as an instruction register when the MIF is
1672 * execution completion. during a read operation, this register will also
1673 * contain the 16-bit data returned by the tranceiver. unless specified
1684 read */
1685 #define MIF_FRAME_OP_READ 0x20000000 /* read OPcode */
1696 to be read/written */
1709 load with 16-bit data
1713 in a read. when
1717 and 16-bit data
1720 read (if valid bit
1723 #define MIF_CFG_PHY_SELECT 0x0001 /* 1 -> select MDIO_1
1724 0 -> select MDIO_0 */
1728 #define MIF_CFG_BB_MODE 0x0004 /* 1 -> bit-bang mode
1729 0 -> frame mode */
1737 1 -> tranceiver is
1740 w/ MDIO_0 in bit-bang
1743 during a read op */
1746 1 -> transceiver is
1749 w/ MDIO_1 in bit-bang
1752 during a read op */
1757 /* 16-bit register used to determine which bits in the POLL_STATUS portion of
1764 /* 32-bit register used when in poll mode. auto-cleared after being read */
1769 reg being read */
1776 last read */
1779 /* 7-bit register has current state for all state machines in the MIF */
1791 /* the auto-negotiation enable bit should be programmed the same at
1792 * the link partner as in the local device to enable auto-negotiation to
1793 * complete. when that bit is reprogrammed, auto-neg/manual config is
1808 restart auto-
1810 #define PCS_MII_ISOLATE 0x0400 /* read as 0. ignored
1812 #define PCS_MII_POWER_DOWN 0x0800 /* read as 0. ignored
1821 #define PCS_MII_10_100_SEL 0x2000 /* read as 0. ignored on
1823 #define PCS_MII_RESET 0x8000 /* reset PCS. self-clears
1830 #define PCS_MII_STATUS_LINK_STATUS 0x0004 /* 1 -> link up.
1831 0 -> link down. 0 is
1833 kept until read. read
1837 auto-neg) */
1838 #define PCS_MII_STATUS_REMOTE_FAULT 0x0010 /* 1 -> remote fault detected
1841 auto-neg completed */
1842 #define PCS_MII_STATUS_AUTONEG_COMP 0x0020 /* 1 -> auto-negotiation
1844 0 -> auto-negotiation not
1848 a 1000 Base-X PHY. writes
1851 /* used during auto-negotiation.
1857 1000 Base-X */
1858 #define PCS_MII_ADVERT_HD 0x0040 /* advertise half-duplex
1859 1000 Base-X */
1867 going off-line. bit12 will
1895 non-resettable */
1910 #define PCS_CFG_10MS_TIMER_OVERRIDE 0x20 /* shortens 10-20ms auto-
1915 /* used for diagnostic purposes. bits 20-22 autoclear on read */
1927 #define PCS_SM_SEQ_DETECT_STATE_MASK 0x00001800 /* cycling through 0-3
1930 through 0-1 indicates
1952 no longer than 20ms */
1973 since last read */
1975 /* control which network interface is used. no more than one bit should
1986 10-bit interface */
1996 #define PCS_SERDES_CTRL_LOCKREF 0x04 /* frequency-lock RBC[0:1]
2005 * 0b001 rxdma req, rxdma ack, rxdma ready, rxdma read
2027 * counters rollover w/out generating an interrupt.
2037 /** LocalBus Devices. the following provides run-time access to the
2091 #define CAS_BMSR_1000_EXTEND 0x0100 /* supports 1000Base-T extended status */
2266 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2471 { "No HTTP", 0x0000, 0x0000, OP_EQ, 0, S1_PCKT, 0, S1_PCKT,
2544 /* number of flows that can go through re-assembly */
2570 bytes. 0 - 9256 */
2598 /* descriptor ring for free buffers contains page-sized buffers. the index
2689 link_down = 0, /* No link, will retry */
2707 * TX COMPWB must be 8-byte aligned.
2766 * are there for flow re-assembly. */
2805 int crc_size; /* 4 if half-duplex */
2833 /* Link-down problem workaround */
2850 int casreg_len; /* reg-space size for dumping */
2867 #define TX_DESC_NEXT(r, x) (((x) + 1) & (TX_DESC_RINGN_SIZE(r) - 1))
2868 #define RX_DESC_ENTRY(r, x) ((x) & (RX_DESC_RINGN_SIZE(r) - 1))
2869 #define RX_COMP_ENTRY(r, x) ((x) & (RX_COMP_RINGN_SIZE(r) - 1))
2871 #define TX_BUFF_COUNT(r, x, y) ((x) <= (y) ? ((y) - (x)) : \
2872 (TX_DESC_RINGN_SIZE(r) - (x) + (y)))
2874 #define TX_BUFFS_AVAIL(cp, i) ((cp)->tx_old[(i)] <= (cp)->tx_new[(i)] ? \
2875 (cp)->tx_old[(i)] + (TX_DESC_RINGN_SIZE(i) - 1) - (cp)->tx_new[(i)] : \
2876 (cp)->tx_old[(i)] - (cp)->tx_new[(i)] - 1)
2879 (((unsigned long) (addr) + ((align) - 1UL)) & ~((align) - 1))