Lines Matching full:transmit
16 #define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
19 #define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
74 #define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
75 #define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
85 #define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
91 #define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
92 #define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
110 #define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
118 #define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
123 #define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
125 #define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
126 #define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
127 #define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
128 #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
129 #define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */