Lines Matching +full:eth +full:- +full:ck
1 // SPDX-License-Identifier: GPL-2.0-only
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
38 *------------------------------------------
40 *------------------------------------------
42 *------------------------------------------
44 *------------------------------------------
46 *------------------------------------------
48 *------------------------------------------
64 * ---------------------------------------------------------------------------
65 *| MII | - | eth-ck | n/a | n/a |
66 *| | | st,ext-phyclk | | |
67 * ---------------------------------------------------------------------------
68 *| GMII | - | eth-ck | n/a | n/a |
69 *| | | st,ext-phyclk | | |
70 * ---------------------------------------------------------------------------
71 *| RGMII | - | eth-ck | n/a | eth-ck |
72 *| | | st,ext-phyclk | | st,eth-clk-sel or|
73 *| | | | | st,ext-phyclk |
74 * ---------------------------------------------------------------------------
75 *| RMII | - | eth-ck | eth-ck | n/a |
76 *| | | st,ext-phyclk | st,eth-ref-clk-sel | |
77 *| | | | or st,ext-phyclk | |
78 * ---------------------------------------------------------------------------
93 u32 mode_reg; /* MAC glue-logic mode register */
112 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; in stm32_dwmac_init()
115 if (dwmac->ops->set_mode) { in stm32_dwmac_init()
116 ret = dwmac->ops->set_mode(plat_dat); in stm32_dwmac_init()
121 ret = clk_prepare_enable(dwmac->clk_tx); in stm32_dwmac_init()
125 if (!dwmac->dev->power.is_suspended) { in stm32_dwmac_init()
126 ret = clk_prepare_enable(dwmac->clk_rx); in stm32_dwmac_init()
128 clk_disable_unprepare(dwmac->clk_tx); in stm32_dwmac_init()
133 if (dwmac->ops->clk_prepare) { in stm32_dwmac_init()
134 ret = dwmac->ops->clk_prepare(dwmac, true); in stm32_dwmac_init()
136 clk_disable_unprepare(dwmac->clk_rx); in stm32_dwmac_init()
137 clk_disable_unprepare(dwmac->clk_tx); in stm32_dwmac_init()
149 ret = clk_prepare_enable(dwmac->syscfg_clk); in stm32mp1_clk_prepare()
152 if (dwmac->enable_eth_ck) { in stm32mp1_clk_prepare()
153 ret = clk_prepare_enable(dwmac->clk_eth_ck); in stm32mp1_clk_prepare()
155 clk_disable_unprepare(dwmac->syscfg_clk); in stm32mp1_clk_prepare()
160 clk_disable_unprepare(dwmac->syscfg_clk); in stm32mp1_clk_prepare()
161 if (dwmac->enable_eth_ck) in stm32mp1_clk_prepare()
162 clk_disable_unprepare(dwmac->clk_eth_ck); in stm32mp1_clk_prepare()
169 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; in stm32mp1_set_mode()
170 u32 reg = dwmac->mode_reg, clk_rate; in stm32mp1_set_mode()
173 clk_rate = clk_get_rate(dwmac->clk_eth_ck); in stm32mp1_set_mode()
174 dwmac->enable_eth_ck = false; in stm32mp1_set_mode()
175 switch (plat_dat->interface) { in stm32mp1_set_mode()
177 if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk) in stm32mp1_set_mode()
178 dwmac->enable_eth_ck = true; in stm32mp1_set_mode()
185 (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { in stm32mp1_set_mode()
186 dwmac->enable_eth_ck = true; in stm32mp1_set_mode()
194 (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) { in stm32mp1_set_mode()
195 dwmac->enable_eth_ck = true; in stm32mp1_set_mode()
206 (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { in stm32mp1_set_mode()
207 dwmac->enable_eth_ck = true; in stm32mp1_set_mode()
214 plat_dat->interface); in stm32mp1_set_mode()
216 return -EINVAL; in stm32mp1_set_mode()
220 regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, in stm32mp1_set_mode()
221 dwmac->ops->syscfg_eth_mask); in stm32mp1_set_mode()
224 return regmap_update_bits(dwmac->regmap, reg, in stm32mp1_set_mode()
225 dwmac->ops->syscfg_eth_mask, val); in stm32mp1_set_mode()
230 struct stm32_dwmac *dwmac = plat_dat->bsp_priv; in stm32mcu_set_mode()
231 u32 reg = dwmac->mode_reg; in stm32mcu_set_mode()
234 switch (plat_dat->interface) { in stm32mcu_set_mode()
245 plat_dat->interface); in stm32mcu_set_mode()
247 return -EINVAL; in stm32mcu_set_mode()
250 return regmap_update_bits(dwmac->regmap, reg, in stm32mcu_set_mode()
251 dwmac->ops->syscfg_eth_mask, val << 23); in stm32mcu_set_mode()
256 clk_disable_unprepare(dwmac->clk_tx); in stm32_dwmac_clk_disable()
257 clk_disable_unprepare(dwmac->clk_rx); in stm32_dwmac_clk_disable()
259 if (dwmac->ops->clk_prepare) in stm32_dwmac_clk_disable()
260 dwmac->ops->clk_prepare(dwmac, false); in stm32_dwmac_clk_disable()
266 struct device_node *np = dev->of_node; in stm32_dwmac_parse_data()
270 dwmac->clk_tx = devm_clk_get(dev, "mac-clk-tx"); in stm32_dwmac_parse_data()
271 if (IS_ERR(dwmac->clk_tx)) { in stm32_dwmac_parse_data()
272 dev_err(dev, "No ETH Tx clock provided...\n"); in stm32_dwmac_parse_data()
273 return PTR_ERR(dwmac->clk_tx); in stm32_dwmac_parse_data()
276 dwmac->clk_rx = devm_clk_get(dev, "mac-clk-rx"); in stm32_dwmac_parse_data()
277 if (IS_ERR(dwmac->clk_rx)) { in stm32_dwmac_parse_data()
278 dev_err(dev, "No ETH Rx clock provided...\n"); in stm32_dwmac_parse_data()
279 return PTR_ERR(dwmac->clk_rx); in stm32_dwmac_parse_data()
282 if (dwmac->ops->parse_data) { in stm32_dwmac_parse_data()
283 err = dwmac->ops->parse_data(dwmac, dev); in stm32_dwmac_parse_data()
289 dwmac->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscon"); in stm32_dwmac_parse_data()
290 if (IS_ERR(dwmac->regmap)) in stm32_dwmac_parse_data()
291 return PTR_ERR(dwmac->regmap); in stm32_dwmac_parse_data()
293 err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg); in stm32_dwmac_parse_data()
304 struct device_node *np = dev->of_node; in stm32mp1_parse_data()
308 dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); in stm32mp1_parse_data()
311 dwmac->eth_clk_sel_reg = of_property_read_bool(np, "st,eth-clk-sel"); in stm32mp1_parse_data()
314 dwmac->eth_ref_clk_sel_reg = in stm32mp1_parse_data()
315 of_property_read_bool(np, "st,eth-ref-clk-sel"); in stm32mp1_parse_data()
318 dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck"); in stm32mp1_parse_data()
319 if (IS_ERR(dwmac->clk_eth_ck)) { in stm32mp1_parse_data()
321 dwmac->clk_eth_ck = NULL; in stm32mp1_parse_data()
325 dwmac->clk_ethstp = devm_clk_get(dev, "ethstp"); in stm32mp1_parse_data()
326 if (IS_ERR(dwmac->clk_ethstp)) { in stm32mp1_parse_data()
328 "No ETH peripheral clock provided for CStop mode ...\n"); in stm32mp1_parse_data()
329 return PTR_ERR(dwmac->clk_ethstp); in stm32mp1_parse_data()
333 dwmac->syscfg_clk = devm_clk_get(dev, "syscfg-clk"); in stm32mp1_parse_data()
334 if (IS_ERR(dwmac->syscfg_clk)) in stm32mp1_parse_data()
335 dwmac->syscfg_clk = NULL; in stm32mp1_parse_data()
340 dwmac->irq_pwr_wakeup = platform_get_irq_byname_optional(pdev, in stm32mp1_parse_data()
342 if (dwmac->irq_pwr_wakeup == -EPROBE_DEFER) in stm32mp1_parse_data()
343 return -EPROBE_DEFER; in stm32mp1_parse_data()
345 if (!dwmac->clk_eth_ck && dwmac->irq_pwr_wakeup >= 0) { in stm32mp1_parse_data()
346 err = device_init_wakeup(&pdev->dev, true); in stm32mp1_parse_data()
348 dev_err(&pdev->dev, "Failed to init wake up irq\n"); in stm32mp1_parse_data()
351 err = dev_pm_set_dedicated_wake_irq(&pdev->dev, in stm32mp1_parse_data()
352 dwmac->irq_pwr_wakeup); in stm32mp1_parse_data()
354 dev_err(&pdev->dev, "Failed to set wake up irq\n"); in stm32mp1_parse_data()
355 device_init_wakeup(&pdev->dev, false); in stm32mp1_parse_data()
357 device_set_wakeup_enable(&pdev->dev, false); in stm32mp1_parse_data()
378 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); in stm32_dwmac_probe()
380 ret = -ENOMEM; in stm32_dwmac_probe()
384 data = of_device_get_match_data(&pdev->dev); in stm32_dwmac_probe()
386 dev_err(&pdev->dev, "no of match data provided\n"); in stm32_dwmac_probe()
387 ret = -EINVAL; in stm32_dwmac_probe()
391 dwmac->ops = data; in stm32_dwmac_probe()
392 dwmac->dev = &pdev->dev; in stm32_dwmac_probe()
394 ret = stm32_dwmac_parse_data(dwmac, &pdev->dev); in stm32_dwmac_probe()
396 dev_err(&pdev->dev, "Unable to parse OF data\n"); in stm32_dwmac_probe()
400 plat_dat->bsp_priv = dwmac; in stm32_dwmac_probe()
406 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); in stm32_dwmac_probe()
424 int ret = stmmac_dvr_remove(&pdev->dev); in stm32_dwmac_remove()
425 struct stm32_dwmac *dwmac = priv->plat->bsp_priv; in stm32_dwmac_remove()
427 stm32_dwmac_clk_disable(priv->plat->bsp_priv); in stm32_dwmac_remove()
429 if (dwmac->irq_pwr_wakeup >= 0) { in stm32_dwmac_remove()
430 dev_pm_clear_wake_irq(&pdev->dev); in stm32_dwmac_remove()
431 device_init_wakeup(&pdev->dev, false); in stm32_dwmac_remove()
441 ret = clk_prepare_enable(dwmac->clk_ethstp); in stm32mp1_suspend()
445 clk_disable_unprepare(dwmac->clk_tx); in stm32mp1_suspend()
446 clk_disable_unprepare(dwmac->syscfg_clk); in stm32mp1_suspend()
447 if (dwmac->enable_eth_ck) in stm32mp1_suspend()
448 clk_disable_unprepare(dwmac->clk_eth_ck); in stm32mp1_suspend()
455 clk_disable_unprepare(dwmac->clk_ethstp); in stm32mp1_resume()
460 clk_disable_unprepare(dwmac->clk_tx); in stm32mcu_suspend()
461 clk_disable_unprepare(dwmac->clk_rx); in stm32mcu_suspend()
471 struct stm32_dwmac *dwmac = priv->plat->bsp_priv; in stm32_dwmac_suspend()
477 if (dwmac->ops->suspend) in stm32_dwmac_suspend()
478 ret = dwmac->ops->suspend(dwmac); in stm32_dwmac_suspend()
487 struct stm32_dwmac *dwmac = priv->plat->bsp_priv; in stm32_dwmac_resume()
490 if (dwmac->ops->resume) in stm32_dwmac_resume()
491 dwmac->ops->resume(dwmac); in stm32_dwmac_resume()
493 ret = stm32_dwmac_init(priv->plat); in stm32_dwmac_resume()
522 { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
523 { .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},
532 .name = "stm32-dwmac",