47 	u32	reg_shift;  member
103 	u32 reg_offset, reg_shift;  in socfpga_dwmac_parse_data()  local
124 	ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);  in socfpga_dwmac_parse_data()
218 	dwmac->reg_shift = reg_shift;  in socfpga_dwmac_parse_data()
266 	u32 reg_shift = dwmac->reg_shift;  in socfpga_gen5_set_phy_mode()  local
286 	ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);  in socfpga_gen5_set_phy_mode()
287 	ctrl |= val << reg_shift;  in socfpga_gen5_set_phy_mode()
295 		module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));  in socfpga_gen5_set_phy_mode()
301 		ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);  in socfpga_gen5_set_phy_mode()
304 			  (reg_shift / 2));  in socfpga_gen5_set_phy_mode()
328 	u32 reg_shift = dwmac->reg_shift;  in socfpga_gen10_set_phy_mode()  local
356 		module |= (SYSMGR_FPGAINTF_EMAC_BIT << reg_shift);  in socfpga_gen10_set_phy_mode()