1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
52  * timing tuning.
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
73 /* Defined for adding a delay to the input RX_CLK for better timing.
112 	data = readl(dwmac->regs + reg);  in meson8b_dwmac_mask_bits()
116 	writel(data, dwmac->regs + reg);  in meson8b_dwmac_mask_bits()
129 	snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev),  in meson8b_dwmac_register_clk()
138 	hw->init = &init;  in meson8b_dwmac_register_clk()
140 	return devm_clk_register(dwmac->dev, hw);  in meson8b_dwmac_register_clk()
146 	struct device *dev = dwmac->dev;  in meson8b_init_rgmii_tx_clk()
149 		{ .index = -1, },  in meson8b_init_rgmii_tx_clk()
165 		return -ENOMEM;  in meson8b_init_rgmii_tx_clk()
167 	clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;  in meson8b_init_rgmii_tx_clk()
168 	clk_configs->m250_mux.shift = __ffs(PRG_ETH0_CLK_M250_SEL_MASK);  in meson8b_init_rgmii_tx_clk()
169 	clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK >>  in meson8b_init_rgmii_tx_clk()
170 				     clk_configs->m250_mux.shift;  in meson8b_init_rgmii_tx_clk()
173 					 &clk_configs->m250_mux.hw);  in meson8b_init_rgmii_tx_clk()
177 	parent_data.hw = &clk_configs->m250_mux.hw;  in meson8b_init_rgmii_tx_clk()
178 	clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0;  in meson8b_init_rgmii_tx_clk()
179 	clk_configs->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT;  in meson8b_init_rgmii_tx_clk()
180 	clk_configs->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH;  in meson8b_init_rgmii_tx_clk()
181 	clk_configs->m250_div.table = div_table;  in meson8b_init_rgmii_tx_clk()
182 	clk_configs->m250_div.flags = CLK_DIVIDER_ALLOW_ZERO |  in meson8b_init_rgmii_tx_clk()
186 					 &clk_configs->m250_div.hw);  in meson8b_init_rgmii_tx_clk()
190 	parent_data.hw = &clk_configs->m250_div.hw;  in meson8b_init_rgmii_tx_clk()
191 	clk_configs->fixed_div2.mult = 1;  in meson8b_init_rgmii_tx_clk()
192 	clk_configs->fixed_div2.div = 2;  in meson8b_init_rgmii_tx_clk()
195 					 &clk_configs->fixed_div2.hw);  in meson8b_init_rgmii_tx_clk()
199 	parent_data.hw = &clk_configs->fixed_div2.hw;  in meson8b_init_rgmii_tx_clk()
200 	clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0;  in meson8b_init_rgmii_tx_clk()
201 	clk_configs->rgmii_tx_en.bit_idx = PRG_ETH0_RGMII_TX_CLK_EN;  in meson8b_init_rgmii_tx_clk()
204 					 &clk_configs->rgmii_tx_en.hw);  in meson8b_init_rgmii_tx_clk()
208 	dwmac->rgmii_tx_clk = clk;  in meson8b_init_rgmii_tx_clk()
215 	switch (dwmac->phy_mode) {  in meson8b_set_phy_mode()
226 		/* disable RGMII mode -> enables RMII mode */  in meson8b_set_phy_mode()
231 		dev_err(dwmac->dev, "fail to set phy-mode %s\n",  in meson8b_set_phy_mode()
232 			phy_modes(dwmac->phy_mode));  in meson8b_set_phy_mode()
233 		return -EINVAL;  in meson8b_set_phy_mode()
241 	switch (dwmac->phy_mode) {  in meson_axg_set_phy_mode()
252 		/* disable RGMII mode -> enables RMII mode */  in meson_axg_set_phy_mode()
258 		dev_err(dwmac->dev, "fail to set phy-mode %s\n",  in meson_axg_set_phy_mode()
259 			phy_modes(dwmac->phy_mode));  in meson_axg_set_phy_mode()
260 		return -EINVAL;  in meson_axg_set_phy_mode()
275 	return devm_add_action_or_reset(dwmac->dev,  in meson8b_devm_clk_prepare_enable()
288 				   dwmac->tx_delay_ns >> 1);  in meson8b_init_rgmii_delays()
290 	if (dwmac->data->has_prg_eth1_rgmii_rx_delay)  in meson8b_init_rgmii_delays()
292 					   dwmac->rx_delay_ps / 200);  in meson8b_init_rgmii_delays()
293 	else if (dwmac->rx_delay_ps == 2000)  in meson8b_init_rgmii_delays()
296 	switch (dwmac->phy_mode) {  in meson8b_init_rgmii_delays()
313 		dev_err(dwmac->dev, "unsupported phy-mode %s\n",  in meson8b_init_rgmii_delays()
314 			phy_modes(dwmac->phy_mode));  in meson8b_init_rgmii_delays()
315 		return -EINVAL;  in meson8b_init_rgmii_delays()
319 		if (!dwmac->timing_adj_clk) {  in meson8b_init_rgmii_delays()
320 			dev_err(dwmac->dev,  in meson8b_init_rgmii_delays()
321 				"The timing-adjustment clock is mandatory for the RX delay re-timing\n");  in meson8b_init_rgmii_delays()
322 			return -EINVAL;  in meson8b_init_rgmii_delays()
325 		/* The timing adjustment logic is driven by a separate clock */  in meson8b_init_rgmii_delays()
327 						      dwmac->timing_adj_clk);  in meson8b_init_rgmii_delays()
329 			dev_err(dwmac->dev,  in meson8b_init_rgmii_delays()
330 				"Failed to enable the timing-adjustment clock\n");  in meson8b_init_rgmii_delays()
350 	if (phy_interface_mode_is_rgmii(dwmac->phy_mode)) {  in meson8b_init_prg_eth()
351 		/* only relevant for RMII mode -> disable in RGMII mode */  in meson8b_init_prg_eth()
357 		 * a register) based on the line-speed (125MHz for Gbit speeds,  in meson8b_init_prg_eth()
360 		ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000);  in meson8b_init_prg_eth()
362 			dev_err(dwmac->dev,  in meson8b_init_prg_eth()
368 						      dwmac->rgmii_tx_clk);  in meson8b_init_prg_eth()
370 			dev_err(dwmac->dev,  in meson8b_init_prg_eth()
381 	/* enable TX_CLK and PHY_REF_CLK generator */  in meson8b_init_prg_eth()
403 	dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);  in meson8b_dwmac_probe()
405 		ret = -ENOMEM;  in meson8b_dwmac_probe()
409 	dwmac->data = (const struct meson8b_dwmac_data *)  in meson8b_dwmac_probe()
410 		of_device_get_match_data(&pdev->dev);  in meson8b_dwmac_probe()
411 	if (!dwmac->data) {  in meson8b_dwmac_probe()
412 		ret = -EINVAL;  in meson8b_dwmac_probe()
415 	dwmac->regs = devm_platform_ioremap_resource(pdev, 1);  in meson8b_dwmac_probe()
416 	if (IS_ERR(dwmac->regs)) {  in meson8b_dwmac_probe()
417 		ret = PTR_ERR(dwmac->regs);  in meson8b_dwmac_probe()
421 	dwmac->dev = &pdev->dev;  in meson8b_dwmac_probe()
422 	ret = of_get_phy_mode(pdev->dev.of_node, &dwmac->phy_mode);  in meson8b_dwmac_probe()
424 		dev_err(&pdev->dev, "missing phy-mode property\n");  in meson8b_dwmac_probe()
429 	if (of_property_read_u32(pdev->dev.of_node, "amlogic,tx-delay-ns",  in meson8b_dwmac_probe()
430 				 &dwmac->tx_delay_ns))  in meson8b_dwmac_probe()
431 		dwmac->tx_delay_ns = 2;  in meson8b_dwmac_probe()
434 	if (of_property_read_u32(pdev->dev.of_node, "rx-internal-delay-ps",  in meson8b_dwmac_probe()
435 				 &dwmac->rx_delay_ps)) {  in meson8b_dwmac_probe()
436 		if (!of_property_read_u32(pdev->dev.of_node,  in meson8b_dwmac_probe()
437 					  "amlogic,rx-delay-ns",  in meson8b_dwmac_probe()
438 					  &dwmac->rx_delay_ps))  in meson8b_dwmac_probe()
440 			dwmac->rx_delay_ps *= 1000;  in meson8b_dwmac_probe()
443 	if (dwmac->data->has_prg_eth1_rgmii_rx_delay) {  in meson8b_dwmac_probe()
444 		if (dwmac->rx_delay_ps > 3000 || dwmac->rx_delay_ps % 200) {  in meson8b_dwmac_probe()
445 			dev_err(dwmac->dev,  in meson8b_dwmac_probe()
447 			ret = -EINVAL;  in meson8b_dwmac_probe()
451 		if (dwmac->rx_delay_ps != 0 && dwmac->rx_delay_ps != 2000) {  in meson8b_dwmac_probe()
452 			dev_err(dwmac->dev,  in meson8b_dwmac_probe()
454 			ret = -EINVAL;  in meson8b_dwmac_probe()
459 	dwmac->timing_adj_clk = devm_clk_get_optional(dwmac->dev,  in meson8b_dwmac_probe()
460 						      "timing-adjustment");  in meson8b_dwmac_probe()
461 	if (IS_ERR(dwmac->timing_adj_clk)) {  in meson8b_dwmac_probe()
462 		ret = PTR_ERR(dwmac->timing_adj_clk);  in meson8b_dwmac_probe()
474 	ret = dwmac->data->set_phy_mode(dwmac);  in meson8b_dwmac_probe()
482 	plat_dat->bsp_priv = dwmac;  in meson8b_dwmac_probe()
484 	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);  in meson8b_dwmac_probe()
513 		.compatible = "amlogic,meson8b-dwmac",
517 		.compatible = "amlogic,meson8m2-dwmac",
521 		.compatible = "amlogic,meson-gxbb-dwmac",
525 		.compatible = "amlogic,meson-axg-dwmac",
529 		.compatible = "amlogic,meson-g12a-dwmac",
540 		.name           = "meson8b-dwmac",