Lines Matching +full:clock +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0
95 /* clock ids to be requested */
115 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
116 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
120 switch (plat->phy_mode) { in mt2712_set_interface()
134 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
135 return -EINVAL; in mt2712_set_interface()
138 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
145 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
147 switch (plat->phy_mode) { in mt2712_delay_ps2stage()
151 mac_delay->tx_delay /= 550; in mt2712_delay_ps2stage()
152 mac_delay->rx_delay /= 550; in mt2712_delay_ps2stage()
159 mac_delay->tx_delay /= 170; in mt2712_delay_ps2stage()
160 mac_delay->rx_delay /= 170; in mt2712_delay_ps2stage()
163 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_delay_ps2stage()
170 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_stage2ps()
172 switch (plat->phy_mode) { in mt2712_delay_stage2ps()
176 mac_delay->tx_delay *= 550; in mt2712_delay_stage2ps()
177 mac_delay->rx_delay *= 550; in mt2712_delay_stage2ps()
184 mac_delay->tx_delay *= 170; in mt2712_delay_stage2ps()
185 mac_delay->rx_delay *= 170; in mt2712_delay_stage2ps()
188 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_delay_stage2ps()
195 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_set_delay()
200 switch (plat->phy_mode) { in mt2712_set_delay()
202 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay); in mt2712_set_delay()
203 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay); in mt2712_set_delay()
204 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv); in mt2712_set_delay()
206 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
207 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
208 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
211 if (plat->rmii_clk_from_mac) { in mt2712_set_delay()
212 /* case 1: mac provides the rmii reference clock, in mt2712_set_delay()
213 * and the clock output to TXC pin. in mt2712_set_delay()
214 * The egress timing can be adjusted by GTXC delay macro circuit. in mt2712_set_delay()
215 * The ingress timing can be adjusted by TXC delay macro circuit. in mt2712_set_delay()
217 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
218 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
219 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
221 delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); in mt2712_set_delay()
222 delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay); in mt2712_set_delay()
223 delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv); in mt2712_set_delay()
225 /* case 2: the rmii reference clock is from external phy, in mt2712_set_delay()
227 * the reference clk is connected to. The reference clock is a in mt2712_set_delay()
229 * the reference clock timing adjustment in mt2712_set_delay()
231 if (plat->rmii_rxc) { in mt2712_set_delay()
232 /* the rmii reference clock from outside is connected in mt2712_set_delay()
233 * to RXC pin, the reference clock will be adjusted in mt2712_set_delay()
234 * by RXC delay macro circuit. in mt2712_set_delay()
236 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
237 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
238 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
240 /* the rmii reference clock from outside is connected in mt2712_set_delay()
241 * to TXC pin, the reference clock will be adjusted in mt2712_set_delay()
242 * by TXC delay macro circuit. in mt2712_set_delay()
244 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
245 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
246 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
248 /* tx_inv will inverse the tx clock inside mac relateive to in mt2712_set_delay()
249 * reference clock from external phy, in mt2712_set_delay()
250 * and this bit is located in the same register with fine-tune in mt2712_set_delay()
252 if (mac_delay->tx_inv) in mt2712_set_delay()
262 delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); in mt2712_set_delay()
263 delay_val |= FIELD_PREP(ETH_DLY_GTXC_STAGES, mac_delay->tx_delay); in mt2712_set_delay()
264 delay_val |= FIELD_PREP(ETH_DLY_GTXC_INV, mac_delay->tx_inv); in mt2712_set_delay()
266 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
267 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
268 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
271 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_delay()
272 return -EINVAL; in mt2712_set_delay()
274 regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val); in mt2712_set_delay()
275 regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val); in mt2712_set_delay()
294 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? MT8195_RMII_CLK_SRC_INTERNAL : 0; in mt8195_set_interface()
295 int rmii_rxc = plat->rmii_rxc ? MT8195_RMII_CLK_SRC_RXC : 0; in mt8195_set_interface()
299 switch (plat->phy_mode) { in mt8195_set_interface()
314 dev_err(plat->dev, "phy interface not supported\n"); in mt8195_set_interface()
315 return -EINVAL; in mt8195_set_interface()
321 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val); in mt8195_set_interface()
328 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt8195_delay_ps2stage()
331 mac_delay->tx_delay /= 290; in mt8195_delay_ps2stage()
332 mac_delay->rx_delay /= 290; in mt8195_delay_ps2stage()
337 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt8195_delay_stage2ps()
340 mac_delay->tx_delay *= 290; in mt8195_delay_stage2ps()
341 mac_delay->rx_delay *= 290; in mt8195_delay_stage2ps()
346 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt8195_set_delay()
351 switch (plat->phy_mode) { in mt8195_set_delay()
353 delay_val |= FIELD_PREP(MT8195_DLY_TXC_ENABLE, !!mac_delay->tx_delay); in mt8195_set_delay()
354 delay_val |= FIELD_PREP(MT8195_DLY_TXC_STAGES, mac_delay->tx_delay); in mt8195_set_delay()
355 delay_val |= FIELD_PREP(MT8195_DLY_TXC_INV, mac_delay->tx_inv); in mt8195_set_delay()
357 delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay); in mt8195_set_delay()
358 delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay); in mt8195_set_delay()
359 delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv); in mt8195_set_delay()
362 if (plat->rmii_clk_from_mac) { in mt8195_set_delay()
363 /* case 1: mac provides the rmii reference clock, in mt8195_set_delay()
364 * and the clock output to TXC pin. in mt8195_set_delay()
365 * The egress timing can be adjusted by RMII_TXC delay macro circuit. in mt8195_set_delay()
366 * The ingress timing can be adjusted by RMII_RXC delay macro circuit. in mt8195_set_delay()
369 !!mac_delay->tx_delay); in mt8195_set_delay()
371 mac_delay->tx_delay); in mt8195_set_delay()
373 mac_delay->tx_inv); in mt8195_set_delay()
376 !!mac_delay->rx_delay); in mt8195_set_delay()
378 mac_delay->rx_delay); in mt8195_set_delay()
380 mac_delay->rx_inv); in mt8195_set_delay()
382 /* case 2: the rmii reference clock is from external phy, in mt8195_set_delay()
384 * the reference clk is connected to. The reference clock is a in mt8195_set_delay()
386 * the reference clock timing adjustment in mt8195_set_delay()
388 if (plat->rmii_rxc) { in mt8195_set_delay()
389 /* the rmii reference clock from outside is connected in mt8195_set_delay()
390 * to RXC pin, the reference clock will be adjusted in mt8195_set_delay()
391 * by RXC delay macro circuit. in mt8195_set_delay()
394 !!mac_delay->rx_delay); in mt8195_set_delay()
396 mac_delay->rx_delay); in mt8195_set_delay()
398 mac_delay->rx_inv); in mt8195_set_delay()
400 /* the rmii reference clock from outside is connected in mt8195_set_delay()
401 * to TXC pin, the reference clock will be adjusted in mt8195_set_delay()
402 * by TXC delay macro circuit. in mt8195_set_delay()
405 !!mac_delay->rx_delay); in mt8195_set_delay()
407 mac_delay->rx_delay); in mt8195_set_delay()
409 mac_delay->rx_inv); in mt8195_set_delay()
417 gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_ENABLE, !!mac_delay->tx_delay); in mt8195_set_delay()
418 gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_STAGES, mac_delay->tx_delay); in mt8195_set_delay()
419 gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_INV, mac_delay->tx_inv); in mt8195_set_delay()
421 delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay); in mt8195_set_delay()
422 delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay); in mt8195_set_delay()
423 delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv); in mt8195_set_delay()
427 dev_err(plat->dev, "phy interface not supported\n"); in mt8195_set_delay()
428 return -EINVAL; in mt8195_set_delay()
431 regmap_update_bits(plat->peri_regmap, in mt8195_set_delay()
438 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val); in mt8195_set_delay()
439 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val); in mt8195_set_delay()
450 if ((phy_interface_mode_is_rgmii(priv_plat->phy_mode))) { in mt8195_fix_mac_speed()
451 /* prefer 2ns fixed delay which is controlled by TXC_PHASE_CTRL, in mt8195_fix_mac_speed()
453 * Fall back to delay macro circuit for 10/100Mbps link speed. in mt8195_fix_mac_speed()
456 regmap_update_bits(priv_plat->peri_regmap, in mt8195_fix_mac_speed()
481 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mediatek_dwmac_config_dt()
485 plat->peri_regmap = syscon_regmap_lookup_by_phandle(plat->np, "mediatek,pericfg"); in mediatek_dwmac_config_dt()
486 if (IS_ERR(plat->peri_regmap)) { in mediatek_dwmac_config_dt()
487 dev_err(plat->dev, "Failed to get pericfg syscon\n"); in mediatek_dwmac_config_dt()
488 return PTR_ERR(plat->peri_regmap); in mediatek_dwmac_config_dt()
491 err = of_get_phy_mode(plat->np, &plat->phy_mode); in mediatek_dwmac_config_dt()
493 dev_err(plat->dev, "not find phy-mode\n"); in mediatek_dwmac_config_dt()
497 if (!of_property_read_u32(plat->np, "mediatek,tx-delay-ps", &tx_delay_ps)) { in mediatek_dwmac_config_dt()
498 if (tx_delay_ps < plat->variant->tx_delay_max) { in mediatek_dwmac_config_dt()
499 mac_delay->tx_delay = tx_delay_ps; in mediatek_dwmac_config_dt()
501 dev_err(plat->dev, "Invalid TX clock delay: %dps\n", tx_delay_ps); in mediatek_dwmac_config_dt()
502 return -EINVAL; in mediatek_dwmac_config_dt()
506 if (!of_property_read_u32(plat->np, "mediatek,rx-delay-ps", &rx_delay_ps)) { in mediatek_dwmac_config_dt()
507 if (rx_delay_ps < plat->variant->rx_delay_max) { in mediatek_dwmac_config_dt()
508 mac_delay->rx_delay = rx_delay_ps; in mediatek_dwmac_config_dt()
510 dev_err(plat->dev, "Invalid RX clock delay: %dps\n", rx_delay_ps); in mediatek_dwmac_config_dt()
511 return -EINVAL; in mediatek_dwmac_config_dt()
515 mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse"); in mediatek_dwmac_config_dt()
516 mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse"); in mediatek_dwmac_config_dt()
517 plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc"); in mediatek_dwmac_config_dt()
518 plat->rmii_clk_from_mac = of_property_read_bool(plat->np, "mediatek,rmii-clk-from-mac"); in mediatek_dwmac_config_dt()
519 plat->mac_wol = of_property_read_bool(plat->np, "mediatek,mac-wol"); in mediatek_dwmac_config_dt()
526 const struct mediatek_dwmac_variant *variant = plat->variant; in mediatek_dwmac_clk_init()
529 plat->clks = devm_kcalloc(plat->dev, variant->num_clks, sizeof(*plat->clks), GFP_KERNEL); in mediatek_dwmac_clk_init()
530 if (!plat->clks) in mediatek_dwmac_clk_init()
531 return -ENOMEM; in mediatek_dwmac_clk_init()
533 for (i = 0; i < variant->num_clks; i++) in mediatek_dwmac_clk_init()
534 plat->clks[i].id = variant->clk_list[i]; in mediatek_dwmac_clk_init()
536 ret = devm_clk_bulk_get(plat->dev, variant->num_clks, plat->clks); in mediatek_dwmac_clk_init()
540 /* The clock labeled as "rmii_internal" is needed only in RMII(when in mediatek_dwmac_clk_init()
541 * MAC provides the reference clock), and useless for RGMII/MII or in mediatek_dwmac_clk_init()
542 * RMII(when PHY provides the reference clock). in mediatek_dwmac_clk_init()
543 * So, "rmii_internal" clock is got and configured only when in mediatek_dwmac_clk_init()
544 * reference clock of RMII is from MAC. in mediatek_dwmac_clk_init()
546 if (plat->rmii_clk_from_mac) { in mediatek_dwmac_clk_init()
547 plat->rmii_internal_clk = devm_clk_get(plat->dev, "rmii_internal"); in mediatek_dwmac_clk_init()
548 if (IS_ERR(plat->rmii_internal_clk)) in mediatek_dwmac_clk_init()
549 ret = PTR_ERR(plat->rmii_internal_clk); in mediatek_dwmac_clk_init()
551 plat->rmii_internal_clk = NULL; in mediatek_dwmac_clk_init()
560 const struct mediatek_dwmac_variant *variant = plat->variant; in mediatek_dwmac_init()
563 if (variant->dwmac_set_phy_interface) { in mediatek_dwmac_init()
564 ret = variant->dwmac_set_phy_interface(plat); in mediatek_dwmac_init()
566 dev_err(plat->dev, "failed to set phy interface, err = %d\n", ret); in mediatek_dwmac_init()
571 if (variant->dwmac_set_delay) { in mediatek_dwmac_init()
572 ret = variant->dwmac_set_delay(plat); in mediatek_dwmac_init()
574 dev_err(plat->dev, "failed to set delay value, err = %d\n", ret); in mediatek_dwmac_init()
585 const struct mediatek_dwmac_variant *variant = plat->variant; in mediatek_dwmac_clks_config()
589 ret = clk_bulk_prepare_enable(variant->num_clks, plat->clks); in mediatek_dwmac_clks_config()
591 dev_err(plat->dev, "failed to enable clks, err = %d\n", ret); in mediatek_dwmac_clks_config()
595 ret = clk_prepare_enable(plat->rmii_internal_clk); in mediatek_dwmac_clks_config()
597 dev_err(plat->dev, "failed to enable rmii internal clk, err = %d\n", ret); in mediatek_dwmac_clks_config()
601 clk_disable_unprepare(plat->rmii_internal_clk); in mediatek_dwmac_clks_config()
602 clk_bulk_disable_unprepare(variant->num_clks, plat->clks); in mediatek_dwmac_clks_config()
614 plat->interface = priv_plat->phy_mode; in mediatek_dwmac_common_data()
615 plat->use_phy_wol = priv_plat->mac_wol ? 0 : 1; in mediatek_dwmac_common_data()
616 plat->riwt_off = 1; in mediatek_dwmac_common_data()
617 plat->maxmtu = ETH_DATA_LEN; in mediatek_dwmac_common_data()
618 plat->addr64 = priv_plat->variant->dma_bit_mask; in mediatek_dwmac_common_data()
619 plat->bsp_priv = priv_plat; in mediatek_dwmac_common_data()
620 plat->init = mediatek_dwmac_init; in mediatek_dwmac_common_data()
621 plat->clks_config = mediatek_dwmac_clks_config; in mediatek_dwmac_common_data()
622 if (priv_plat->variant->dwmac_fix_mac_speed) in mediatek_dwmac_common_data()
623 plat->fix_mac_speed = priv_plat->variant->dwmac_fix_mac_speed; in mediatek_dwmac_common_data()
625 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev, in mediatek_dwmac_common_data()
626 sizeof(*plat->safety_feat_cfg), in mediatek_dwmac_common_data()
628 if (!plat->safety_feat_cfg) in mediatek_dwmac_common_data()
629 return -ENOMEM; in mediatek_dwmac_common_data()
631 plat->safety_feat_cfg->tsoee = 1; in mediatek_dwmac_common_data()
632 plat->safety_feat_cfg->mrxpee = 0; in mediatek_dwmac_common_data()
633 plat->safety_feat_cfg->mestee = 1; in mediatek_dwmac_common_data()
634 plat->safety_feat_cfg->mrxee = 1; in mediatek_dwmac_common_data()
635 plat->safety_feat_cfg->mtxee = 1; in mediatek_dwmac_common_data()
636 plat->safety_feat_cfg->epsi = 0; in mediatek_dwmac_common_data()
637 plat->safety_feat_cfg->edpp = 1; in mediatek_dwmac_common_data()
638 plat->safety_feat_cfg->prtyen = 1; in mediatek_dwmac_common_data()
639 plat->safety_feat_cfg->tmouten = 1; in mediatek_dwmac_common_data()
641 for (i = 0; i < plat->tx_queues_to_use; i++) { in mediatek_dwmac_common_data()
644 plat->tx_queues_cfg[i].tbs_en = 1; in mediatek_dwmac_common_data()
657 priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat), GFP_KERNEL); in mediatek_dwmac_probe()
659 return -ENOMEM; in mediatek_dwmac_probe()
661 priv_plat->variant = of_device_get_match_data(&pdev->dev); in mediatek_dwmac_probe()
662 if (!priv_plat->variant) { in mediatek_dwmac_probe()
663 dev_err(&pdev->dev, "Missing dwmac-mediatek variant\n"); in mediatek_dwmac_probe()
664 return -EINVAL; in mediatek_dwmac_probe()
667 priv_plat->dev = &pdev->dev; in mediatek_dwmac_probe()
668 priv_plat->np = pdev->dev.of_node; in mediatek_dwmac_probe()
693 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); in mediatek_dwmac_probe()
709 struct mediatek_dwmac_plat_data *priv_plat = get_stmmac_bsp_priv(&pdev->dev); in mediatek_dwmac_remove()
719 { .compatible = "mediatek,mt2712-gmac",
721 { .compatible = "mediatek,mt8195-gmac",
732 .name = "dwmac-mediatek",