Lines Matching +full:0 +full:x00008000
21 /* Register set is duplicated for BE at an offset of 0x200 */
22 #define LAN9420_CPSR_ENDIAN_OFFSET (0x200)
24 #define LAN9420_CPSR_ENDIAN_OFFSET (0)
27 #define PCI_VENDOR_ID_9420 (0x1055)
28 #define PCI_DEVICE_ID_9420 (0xE420)
30 #define LAN_REGISTER_EXTENT (0x400)
33 #define SMSC9420_EEPROM_MAGIC (0x9420)
40 #define BUS_MODE (0x00)
41 #define BUS_MODE_SWR_ (BIT(0))
50 #define TX_POLL_DEMAND (0x04)
52 #define RX_POLL_DEMAND (0x08)
54 #define RX_BASE_ADDR (0x0C)
56 #define TX_BASE_ADDR (0x10)
58 #define DMAC_STATUS (0x14)
70 #define DMAC_STS_TX_ (BIT(0))
72 #define DMAC_CONTROL (0x18)
79 #define DMAC_INTR_ENA (0x1C)
88 #define DMAC_INTR_ENA_TX_ (BIT(0))
90 #define MISS_FRAME_CNTR (0x20)
92 #define TX_BUFF_ADDR (0x50)
94 #define RX_BUFF_ADDR (0x54)
97 #define TDES0_OWN_ (0x80000000)
98 #define TDES0_ERROR_SUMMARY_ (0x00008000)
99 #define TDES0_LOSS_OF_CARRIER_ (0x00000800)
100 #define TDES0_NO_CARRIER_ (0x00000400)
101 #define TDES0_LATE_COLLISION_ (0x00000200)
102 #define TDES0_EXCESSIVE_COLLISIONS_ (0x00000100)
103 #define TDES0_HEARTBEAT_FAIL_ (0x00000080)
104 #define TDES0_COLLISION_COUNT_MASK_ (0x00000078)
106 #define TDES0_EXCESSIVE_DEFERRAL_ (0x00000004)
107 #define TDES0_DEFERRED_ (0x00000001)
109 #define TDES1_IC_ 0x80000000
110 #define TDES1_LS_ 0x40000000
111 #define TDES1_FS_ 0x20000000
112 #define TDES1_TXCSEN_ 0x08000000
114 #define TDES1_TCH_ 0x01000000
116 /* Receive Descriptor 0 Bit Defs */
117 #define RDES0_OWN_ (0x80000000)
118 #define RDES0_FRAME_LENGTH_MASK_ (0x07FF0000)
120 #define RDES0_ERROR_SUMMARY_ (0x00008000)
121 #define RDES0_DESCRIPTOR_ERROR_ (0x00004000)
122 #define RDES0_LENGTH_ERROR_ (0x00001000)
123 #define RDES0_RUNT_FRAME_ (0x00000800)
124 #define RDES0_MULTICAST_FRAME_ (0x00000400)
125 #define RDES0_FIRST_DESCRIPTOR_ (0x00000200)
126 #define RDES0_LAST_DESCRIPTOR_ (0x00000100)
127 #define RDES0_FRAME_TOO_LONG_ (0x00000080)
128 #define RDES0_COLLISION_SEEN_ (0x00000040)
129 #define RDES0_FRAME_TYPE_ (0x00000020)
130 #define RDES0_WATCHDOG_TIMEOUT_ (0x00000010)
131 #define RDES0_MII_ERROR_ (0x00000008)
132 #define RDES0_DRIBBLING_BIT_ (0x00000004)
133 #define RDES0_CRC_ERROR_ (0x00000002)
136 #define RDES1_RER_ (0x02000000)
141 #define MAC_CR (0x80)
142 #define MAC_CR_RXALL_ (0x80000000)
143 #define MAC_CR_DIS_RXOWN_ (0x00800000)
144 #define MAC_CR_LOOPBK_ (0x00200000)
145 #define MAC_CR_FDPX_ (0x00100000)
146 #define MAC_CR_MCPAS_ (0x00080000)
147 #define MAC_CR_PRMS_ (0x00040000)
148 #define MAC_CR_INVFILT_ (0x00020000)
149 #define MAC_CR_PASSBAD_ (0x00010000)
150 #define MAC_CR_HFILT_ (0x00008000)
151 #define MAC_CR_HPFILT_ (0x00002000)
152 #define MAC_CR_LCOLL_ (0x00001000)
153 #define MAC_CR_DIS_BCAST_ (0x00000800)
154 #define MAC_CR_DIS_RTRY_ (0x00000400)
155 #define MAC_CR_PADSTR_ (0x00000100)
156 #define MAC_CR_BOLMT_MSK (0x000000C0)
157 #define MAC_CR_MFCHK_ (0x00000020)
158 #define MAC_CR_TXEN_ (0x00000008)
159 #define MAC_CR_RXEN_ (0x00000004)
161 #define ADDRH (0x84)
163 #define ADDRL (0x88)
165 #define HASHH (0x8C)
167 #define HASHL (0x90)
169 #define MII_ACCESS (0x94)
170 #define MII_ACCESS_MII_BUSY_ (0x00000001)
171 #define MII_ACCESS_MII_WRITE_ (0x00000002)
172 #define MII_ACCESS_MII_READ_ (0x00000000)
173 #define MII_ACCESS_INDX_MSK_ (0x000007C0)
174 #define MII_ACCESS_PHYADDR_MSK_ (0x0000F8C0)
178 #define MII_DATA (0x98)
180 #define FLOW (0x9C)
182 #define VLAN1 (0xA0)
184 #define VLAN2 (0xA4)
186 #define WUFF (0xA8)
188 #define WUCSR (0xAC)
190 #define COE_CR (0xB0)
191 #define TX_COE_EN (0x00010000)
192 #define RX_COE_MODE (0x00000002)
193 #define RX_COE_EN (0x00000001)
198 #define ID_REV (0xC0)
200 #define INT_CTL (0xC4)
201 #define INT_CTL_SW_INT_EN_ (0x00008000)
204 #define INT_CTL_GPT_INT_EN_ (0x00000008)
205 #define INT_CTL_PHY_INT_EN_ (0x00000004)
206 #define INT_CTL_WAKE_INT_EN_ (0x00000002)
208 #define INT_STAT (0xC8)
213 #define INT_STAT_PHY_INT_ (0x00000004)
214 #define INT_STAT_WAKE_INT_ (0x00000002)
215 #define INT_STAT_DMAC_INT_ (0x00000001)
217 #define INT_CFG (0xCC)
218 #define INT_CFG_IRQ_INT_ (0x00080000)
219 #define INT_CFG_IRQ_EN_ (0x00040000)
220 #define INT_CFG_INT_DEAS_CLR_ (0x00000200)
221 #define INT_CFG_INT_DEAS_MASK (0x000000FF)
223 #define GPIO_CFG (0xD0)
224 #define GPIO_CFG_LED_3_ (0x40000000)
225 #define GPIO_CFG_LED_2_ (0x20000000)
226 #define GPIO_CFG_LED_1_ (0x10000000)
227 #define GPIO_CFG_EEPR_EN_ (0x00700000)
229 #define GPT_CFG (0xD4)
230 #define GPT_CFG_TIMER_EN_ (0x20000000)
232 #define GPT_CNT (0xD8)
234 #define BUS_CFG (0xDC)
235 #define BUS_CFG_RXTXWEIGHT_1_1 (0 << 25)
240 #define PMT_CTRL (0xE0)
242 #define FREE_RUN (0xF4)
244 #define E2P_CMD (0xF8)
245 #define E2P_CMD_EPC_BUSY_ (0x80000000)
246 #define E2P_CMD_EPC_CMD_ (0x70000000)
247 #define E2P_CMD_EPC_CMD_READ_ (0x00000000)
248 #define E2P_CMD_EPC_CMD_EWDS_ (0x10000000)
249 #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
250 #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
251 #define E2P_CMD_EPC_CMD_WRAL_ (0x40000000)
252 #define E2P_CMD_EPC_CMD_ERASE_ (0x50000000)
253 #define E2P_CMD_EPC_CMD_ERAL_ (0x60000000)
254 #define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000)
255 #define E2P_CMD_EPC_TIMEOUT_ (0x00000200)
256 #define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100)
257 #define E2P_CMD_EPC_ADDR_ (0x000000FF)
259 #define E2P_DATA (0xFC)
260 #define E2P_DATA_EEPROM_DATA_ (0x000000FF)