1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*------------------------------------------------------------------------
3  . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
21  ---------------------------------------------------------------------------*/
29  * Any 16-bit access is performed with two 8-bit accesses if the hardware
30  * can't do it directly. Most registers are 16-bit so those are mandatory.
55 #include <asm/mach-types.h>
65 #define SMC_IO_SHIFT		(lp->io_shift)
96 #define SMC_IRQ_FLAGS		(-1)	/* from resource */
114 			 (lp)->cfg.pxa_u16_align4)
123 #define SMC_inb(a, r)		inb((a) + (r) - 0xa0000000)
124 #define SMC_inw(a, r)		inw((a) + (r) - 0xa0000000)
125 #define SMC_inl(a, r)		inl((a) + (r) - 0xa0000000)
126 #define SMC_outb(v, a, r)	outb(v, (a) + (r) - 0xa0000000)
127 #define SMC_outw(lp, v, a, r)	outw(v, (a) + (r) - 0xa0000000)
128 #define SMC_outl(v, a, r)	outl(v, (a) + (r) - 0xa0000000)
129 #define SMC_insl(a, r, p, l)	insl((a) + (r) - 0xa0000000, p, l)
130 #define SMC_outsl(a, r, p, l)	outsl((a) + (r) - 0xa0000000, p, l)
131 #define SMC_insw(a, r, p, l)	insw((a) + (r) - 0xa0000000, p, l)
132 #define SMC_outsw(a, r, p, l)	outsw((a) + (r) - 0xa0000000, p, l)
167 	while (l-- > 0)  in mcf_insw()
174 	while (l-- > 0)  in mcf_outsw()
196 #define SMC_IO_SHIFT		(lp->io_shift)
264 	/* on some platforms a u16 write must be 4-bytes aligned */
270 #define SMC_8BIT(p)	((p)->cfg.flags & SMC91X_USE_8BIT)
271 #define SMC_16BIT(p)	((p)->cfg.flags & SMC91X_USE_16BIT)
272 #define SMC_32BIT(p)	((p)->cfg.flags & SMC91X_USE_32BIT)
277  * always happening in irq context so no need to worry about races.  TX is
281 #include <linux/dma-mapping.h>
286 	smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
291 	struct dma_async_tx_descriptor *tx;  in smc_pxa_dma_inpump()  local
296 	dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);  in smc_pxa_dma_inpump()
297 	tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len,  in smc_pxa_dma_inpump()
299 	if (tx) {  in smc_pxa_dma_inpump()
300 		cookie = dmaengine_submit(tx);  in smc_pxa_dma_inpump()
301 		dma_async_issue_pending(lp->dma_chan);  in smc_pxa_dma_inpump()
303 			status = dmaengine_tx_status(lp->dma_chan, cookie,  in smc_pxa_dma_inpump()
308 		dmaengine_terminate_all(lp->dma_chan);  in smc_pxa_dma_inpump()
310 	dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);  in smc_pxa_dma_inpump()
317 	struct dma_slave_config	config;  in smc_pxa_dma_insl()  local
321 	if (!lp->dma_chan) {  in smc_pxa_dma_insl()
330 		len--;  in smc_pxa_dma_insl()
333 	memset(&config, 0, sizeof(config));  in smc_pxa_dma_insl()
334 	config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;  in smc_pxa_dma_insl()
335 	config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;  in smc_pxa_dma_insl()
336 	config.src_addr = lp->physaddr + reg;  in smc_pxa_dma_insl()
337 	config.dst_addr = lp->physaddr + reg;  in smc_pxa_dma_insl()
338 	config.src_maxburst = 32;  in smc_pxa_dma_insl()
339 	config.dst_maxburst = 32;  in smc_pxa_dma_insl()
340 	ret = dmaengine_slave_config(lp->dma_chan, &config);  in smc_pxa_dma_insl()
342 		dev_err(lp->device, "dma channel configuration failed: %d\n",  in smc_pxa_dma_insl()
355 	smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
360 	struct dma_slave_config	config;  in smc_pxa_dma_insw()  local
364 	if (!lp->dma_chan) {  in smc_pxa_dma_insw()
373 		len--;  in smc_pxa_dma_insw()
376 	memset(&config, 0, sizeof(config));  in smc_pxa_dma_insw()
377 	config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;  in smc_pxa_dma_insw()
378 	config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;  in smc_pxa_dma_insw()
379 	config.src_addr = lp->physaddr + reg;  in smc_pxa_dma_insw()
380 	config.dst_addr = lp->physaddr + reg;  in smc_pxa_dma_insw()
381 	config.src_maxburst = 32;  in smc_pxa_dma_insw()
382 	config.dst_maxburst = 32;  in smc_pxa_dma_insw()
383 	ret = dmaengine_slave_config(lp->dma_chan, &config);  in smc_pxa_dma_insw()
385 		dev_err(lp->device, "dma channel configuration failed: %d\n",  in smc_pxa_dma_insw()
480 #define TCR_LOOP	0x0002	// Controls output pin LBK
482 #define TCR_PAD_EN	0x0080	// When 1 will pad tx frames < 64 bytes w/0
483 #define TCR_NOCRC	0x0100	// When 1 will not append CRC to tx frames
484 #define TCR_MON_CSN	0x0400	// When 1 tx monitors carrier
486 #define TCR_STP_SQET	0x1000	// When 1 stops tx if Signal Quality Error
498 #define ES_TX_SUC	0x0001	// Last TX was successful
499 #define ES_SNGL_COL	0x0002	// Single collision detected for last tx
500 #define ES_MUL_COL	0x0004	// Multiple collisions detected for last tx
501 #define ES_LTX_MULT	0x0008	// Last tx was a multicast
504 #define ES_LTXBRD	0x0040	// Last tx was a broadcast
506 #define ES_LATCOL	0x0200	// Late collision detected on last tx
511 #define ES_TXUNRN	0x8000	// Tx Underrun
545 #define RPC_DPLX	0x1000	// When 1 PHY is in Full-Duplex Mode
546 #define RPC_ANEG	0x0800	// When 1 PHY is in Auto-Negotiate Mode
575 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
600 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
620 #define MC_RSTTXFIFO	(7<<5)	// Reset the TX FIFOs
634 // TX FIFO Ports Register
637 #define TXFIFO_TEMPTY	0x80	// TX FIFO Empty
672 #define IM_TX_EMPTY_INT	0x04 // Set if the TX FIFO goes empty
688 #define MII_MSK_CRS100	0x4000 // Disables CRS100 detection during tx half dup
689 #define MII_MDOE	0x0008 // MII Output Enable
692 #define MII_MDO		0x0001 // MII Output, pin MDO
760  * These phy registers are specific to our on-board phy.
773 #define PHY_CFG1_TLVL_SHIFT	2	// Transmit Output Level Adjust
785 // PHY Status Output (and Interrupt status) Register
786 #define PHY_INT_REG		0x12	// Status Output (Interrupt Status)
795 #define PHY_INT_SPDDET		0x0080	// 1=100Base-TX mode, 0=10Base-T mode
804  * SMC91C96 ethernet config and status registers.
824  * Note: the following macros do *not* select the bank -- this must
854  * effects and use a 32-bit access.
856  * Enforce it on any 32-bit capable setup for now.
1055 				__len -= 2;				\
1059 			if (SMC_CAN_USE_DATACS && lp->datacs)		\
1060 				__ioaddr = lp->datacs;			\
1084 				 * Back both source (on-chip) and	\
1092 				__ptr -= 2;				\
1097 			if (SMC_CAN_USE_DATACS && lp->datacs)		\
1098 				__ioaddr = lp->datacs;			\