35 static int debug = 1;			/* 1 normal messages, 0 quiet .. 7 verbose. */
68 #define RX_FIFO_THRESH 1		/* 0-3, 0==32, 64,96, or 3==128 bytes  */
102 module_param(debug, int, 0);
103 module_param(rx_copybreak, int, 0);
104 module_param_array(options, int, NULL, 0);
105 module_param_array(full_duplex, int, NULL, 0);
106 MODULE_PARM_DESC(debug, "EPIC/100 debug level (0-5)");
107 MODULE_PARM_DESC(options, "EPIC/100: Bits 0-3: media type, bit 4: full duplex");
146 #define EPIC_TOTAL_SIZE 0x100
150 #define EPIC_BAR	0
177 	{ 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 },
178 	{ 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 },
179 	{ 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID,
180 	  PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 },
181 	{ 0,}
193   COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
194   PCIBurstCnt=0x18,
195   TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28,	/* Rx error counters. */
196   MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
199   RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
200   PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
205 	TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
206 	PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
207 	RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
208 	TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
209 	RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
213 	StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80,
216 #define EpicRemoved	0xffffffff	/* Chip failed or removed (CardBus) */
220 #define EpicNormalEvent	(0x0000ffff & ~EpicNapiEvent)
223 	0, 0x0C00, 0x0C00, 0x2000,  0x0100, 0x2100, 0, 0,
224 	0, 0, 0, 0,  0, 0, 0, 0 };
248 	DescOwn=0x8000,
327 	int i, ret, option = 0, duplex = 0;  in epic_init_one()
343 	if (pci_resource_len(pdev, 0) < EPIC_TOTAL_SIZE) {  in epic_init_one()
352 	if (ret < 0)  in epic_init_one()
363 	ioaddr = pci_iomap(pdev, EPIC_BAR, 0);  in epic_init_one()
375 	ep->mii.phy_id_mask = 0x1f;  in epic_init_one()
376 	ep->mii.reg_num_mask = 0x1f;  in epic_init_one()
394 		duplex = (dev->mem_start & 16) ? 1 : 0;  in epic_init_one()
395 	} else if (card_idx >= 0  &&  card_idx < MAX_UNITS) {  in epic_init_one()
396 		if (options[card_idx] >= 0)  in epic_init_one()
398 		if (full_duplex[card_idx] >= 0)  in epic_init_one()
406 	ew32(GENCTL, 0x4200);  in epic_init_one()
409 	for (i = 16; i > 0; i--)  in epic_init_one()
410 		ew32(TEST1, 0x0008);  in epic_init_one()
413 	ew32(MIICfg, 0x12);  in epic_init_one()
415 		ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800);  in epic_init_one()
416 	ew32(GENCTL, 0x0200);  in epic_init_one()
419 	for (i = 0; i < 3; i++)  in epic_init_one()
425 		for (i = 0; i < 64; i++)  in epic_init_one()
441 		int phy, phy_idx = 0;  in epic_init_one()
444 			if (mii_status != 0xffff  &&  mii_status != 0x0000) {  in epic_init_one()
449 					phy, mdio_read(dev, phy, 0), mii_status);  in epic_init_one()
453 		if (phy_idx != 0) {  in epic_init_one()
454 			phy = ep->phys[0];  in epic_init_one()
464 			ep->phys[0] = 3;  in epic_init_one()
466 		ep->mii.phy_id = ep->phys[0];  in epic_init_one()
471 		ew32(NVCTL, er32(NVCTL) & ~0x483c);  in epic_init_one()
472 	ew32(GENCTL, 0x0008);  in epic_init_one()
488 	if (ret < 0)  in epic_init_one()
519 #define EE_SHIFT_CLK	0x04	/* EEPROM shift clock. */
520 #define EE_CS			0x02	/* EEPROM chip select. */
521 #define EE_DATA_WRITE	0x08	/* EEPROM chip data in. */
522 #define EE_WRITE_0		0x01
523 #define EE_WRITE_1		0x09
524 #define EE_DATA_READ	0x10	/* EEPROM chip data out. */
525 #define EE_ENB			(0x0001 | EE_CS)
543 	ew32(INTMASK, 0x00000000);  in epic_disable_int()
575 	int retval = 0;  in read_eeprom()
577 		(er32(EECTL) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);  in read_eeprom()
583 	for (i = 12; i >= 0; i--) {  in read_eeprom()
592 	for (i = 16; i > 0; i--) {  in read_eeprom()
595 		retval = (retval << 1) | ((er32(EECTL) & EE_DATA_READ) ? 1 : 0);  in read_eeprom()
616 	for (i = 400; i > 0; i--) {  in mdio_read()
618 		if ((er32(MIICtrl) & MII_READOP) == 0) {  in mdio_read()
621 			    er16(MIIData) == 0xffff) {  in mdio_read()
628 	return 0xffff;  in mdio_read()
639 	for (i = 10000; i > 0; i--) {  in mdio_write()
641 		if ((er32(MIICtrl) & MII_WRITEOP) == 0)  in mdio_write()
655 	ew32(GENCTL, 0x4001);  in epic_open()
666 	ew32(GENCTL, 0x4000);  in epic_open()
668 	for (i = 16; i > 0; i--)  in epic_open()
669 		ew32(TEST1, 0x0008);  in epic_open()
676 #if 0  in epic_open()
677 	ew32(MIICfg, dev->if_port == 1 ? 0x13 : 0x12);  in epic_open()
680 		ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800);  in epic_open()
684 	ew32(GENCTL, 0x4432 | (RX_FIFO_THRESH << 8));  in epic_open()
686 	ew32(GENCTL, 0x0432 | (RX_FIFO_THRESH << 8));  in epic_open()
688 	ew32(GENCTL, 0x4412 | (RX_FIFO_THRESH << 8));  in epic_open()
690 	ew32(GENCTL, 0x0412 | (RX_FIFO_THRESH << 8));  in epic_open()
695 	for (i = 0; i < 3; i++)  in epic_open()
703 			mdio_write(dev, ep->phys[0], MII_BMCR, media2miictl[dev->if_port&15]);  in epic_open()
707 					    mdio_read(dev, ep->phys[0], MII_BMSR));  in epic_open()
710 		int mii_lpa = mdio_read(dev, ep->phys[0], MII_LPA);  in epic_open()
711 		if (mii_lpa != 0xffff) {  in epic_open()
712 			if ((mii_lpa & LPA_100FULL) || (mii_lpa & 0x01C0) == LPA_10FULL)  in epic_open()
715 				mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);  in epic_open()
720 					    ep->phys[0], mii_lpa);  in epic_open()
724 	ew32(TxCtrl, ep->mii.full_duplex ? 0x7f : 0x79);  in epic_open()
747 	timer_setup(&ep->timer, epic_timer, 0);  in epic_open()
765 	ew32(INTMASK, 0x00000000);  in epic_pause()
770 	if (er16(COMMAND) != 0xffff) {  in epic_pause()
787 	ew32(GENCTL, 0x4001);  in epic_restart()
794 	for (i = 16; i > 0; i--)  in epic_restart()
795 		ew32(TEST1, 0x0008);  in epic_restart()
798 	ew32(GENCTL, 0x0432 | (RX_FIFO_THRESH << 8));  in epic_restart()
800 	ew32(GENCTL, 0x0412 | (RX_FIFO_THRESH << 8));  in epic_restart()
802 	ew32(MIICfg, dev->if_port == 1 ? 0x13 : 0x12);  in epic_restart()
804 		ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800);  in epic_restart()
806 	for (i = 0; i < 3; i++)  in epic_restart()
811 	ew32(TxCtrl, ep->mii.full_duplex ? 0x7f : 0x79);  in epic_restart()
834 	int mii_lpa = ep->mii_phy_cnt ? mdio_read(dev, ep->phys[0], MII_LPA) : 0;  in check_media()
836 	int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;  in check_media()
840 	if (mii_lpa == 0xffff)		/* Bogus read */  in check_media()
846 			    ep->phys[0], mii_lpa);  in check_media()
847 		ew32(TxCtrl, ep->mii.full_duplex ? 0x7F : 0x79);  in check_media()
876 	if (debug > 0) {  in epic_tx_timeout()
884 	if (er16(TxSTAT) & 0x10) {		/* Tx FIFO underflow. */  in epic_tx_timeout()
904 	ep->tx_full = 0;  in epic_init_ring()
905 	ep->dirty_tx = ep->cur_tx = 0;  in epic_init_ring()
906 	ep->cur_rx = ep->dirty_rx = 0;  in epic_init_ring()
910 	for (i = 0; i < RX_RING_SIZE; i++) {  in epic_init_ring()
911 		ep->rx_ring[i].rxstatus = 0;  in epic_init_ring()
921 	for (i = 0; i < RX_RING_SIZE; i++) {  in epic_init_ring()
937 	for (i = 0; i < TX_RING_SIZE; i++) {  in epic_init_ring()
939 		ep->tx_ring[i].txstatus = 0x0000;  in epic_init_ring()
970 		ctrl_word = 0x100000; /* No interrupt */  in epic_start_xmit()
972 		ctrl_word = 0x140000; /* Tx-done intr. */  in epic_start_xmit()
974 		ctrl_word = 0x100000; /* No Tx-done intr. */  in epic_start_xmit()
977 		ctrl_word = 0x140000; /* Tx-done intr. */  in epic_start_xmit()
1012 	if (status & 0x1050)  in epic_tx_error()
1014 	if (status & 0x0008)  in epic_tx_error()
1016 	if (status & 0x0040)  in epic_tx_error()
1018 	if (status & 0x0010)  in epic_tx_error()
1031 	for (dirty_tx = ep->dirty_tx; cur_tx - dirty_tx > 0; dirty_tx++) {  in epic_tx()
1039 		if (likely(txstatus & 0x0001)) {  in epic_tx()
1065 		ep->tx_full = 0;  in epic_tx()
1077 	unsigned int handled = 0;  in epic_interrupt()
1089 	if ((status & IntrSummary) == 0)  in epic_interrupt()
1129 		ew32(INTSTAT, status & 0x7f18);  in epic_interrupt()
1146 	int work_done = 0;  in epic_rx()
1156 	while ((ep->rx_ring[entry].rxstatus & DescOwn) == 0) {  in epic_rx()
1162 		if (--rx_work_limit < 0)  in epic_rx()
1164 		if (status & 0x2006) {  in epic_rx()
1168 			if (status & 0x2000) {  in epic_rx()
1172 			} else if (status & 0x0006)  in epic_rx()
1219 	for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {  in epic_rx()
1304 	for (i = 0; i < RX_RING_SIZE; i++) {  in epic_close()
1307 		ep->rx_ring[i].rxstatus = 0;		/* Not owned by Epic chip. */  in epic_close()
1308 		ep->rx_ring[i].buflength = 0;  in epic_close()
1314 		ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */  in epic_close()
1316 	for (i = 0; i < TX_RING_SIZE; i++) {  in epic_close()
1327 	ew32(GENCTL, 0x0008);  in epic_close()
1329 	return 0;  in epic_close()
1361 		ew32(RxCtrl, 0x002c);  in set_rx_mode()
1363 		memset(mc_filter, 0xff, sizeof(mc_filter));  in set_rx_mode()
1368 		memset(mc_filter, 0xff, sizeof(mc_filter));  in set_rx_mode()
1369 		ew32(RxCtrl, 0x000c);  in set_rx_mode()
1371 		ew32(RxCtrl, 0x0004);  in set_rx_mode()
1376 		memset(mc_filter, 0, sizeof(mc_filter));  in set_rx_mode()
1379 				ether_crc_le(ETH_ALEN, ha->addr) & 0x3f;  in set_rx_mode()
1385 		for (i = 0; i < 4; i++)  in set_rx_mode()
1409 	return 0;  in netdev_get_link_ksettings()
1456 		ew32(GENCTL, 0x0200);  in ethtool_begin()
1457 		ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800);  in ethtool_begin()
1459 	return 0;  in ethtool_begin()
1469 		ew32(GENCTL, 0x0008);  in ethtool_complete()
1470 		ew32(NVCTL, (er32(NVCTL) & ~0x483c) | 0x0000);  in ethtool_complete()
1495 		ew32(GENCTL, 0x0200);  in netdev_ioctl()
1496 		ew32(NVCTL, (er32(NVCTL) & ~0x003c) | 0x4800);  in netdev_ioctl()
1506 		ew32(GENCTL, 0x0008);  in netdev_ioctl()
1507 		ew32(NVCTL, (er32(NVCTL) & ~0x483c) | 0x0000);  in netdev_ioctl()
1537 		return 0;  in epic_suspend()
1540 	ew32(GENCTL, 0x0008);  in epic_suspend()
1542 	return 0;  in epic_suspend()
1551 		return 0;  in epic_resume()
1554 	return 0;  in epic_resume()