266 	void __iomem		*port_base;  member
309 static inline void _sc92031_dummy_read(void __iomem *port_base)  in _sc92031_dummy_read()  argument
311 	ioread32(port_base + MAC0);  in _sc92031_dummy_read()
314 static u32 _sc92031_mii_wait(void __iomem *port_base)  in _sc92031_mii_wait()  argument
320 		mii_status = ioread32(port_base + Miistatus);  in _sc92031_mii_wait()
326 static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)  in _sc92031_mii_cmd()  argument
328 	iowrite32(Mii_Divider, port_base + Miicmd0);  in _sc92031_mii_cmd()
330 	_sc92031_mii_wait(port_base);  in _sc92031_mii_cmd()
332 	iowrite32(cmd1, port_base + Miicmd1);  in _sc92031_mii_cmd()
333 	iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);  in _sc92031_mii_cmd()
335 	return _sc92031_mii_wait(port_base);  in _sc92031_mii_cmd()
338 static void _sc92031_mii_scan(void __iomem *port_base)  in _sc92031_mii_scan()  argument
340 	_sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);  in _sc92031_mii_scan()
343 static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)  in _sc92031_mii_read()  argument
345 	return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;  in _sc92031_mii_read()
348 static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)  in _sc92031_mii_write()  argument
350 	_sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));  in _sc92031_mii_write()
356 	void __iomem *port_base = priv->port_base;  in sc92031_disable_interrupts()  local
363 	iowrite32(0, port_base + IntrMask);  in sc92031_disable_interrupts()
364 	_sc92031_dummy_read(port_base);  in sc92031_disable_interrupts()
374 	void __iomem *port_base = priv->port_base;  in sc92031_enable_interrupts()  local
381 	iowrite32(IntrBits, port_base + IntrMask);  in sc92031_enable_interrupts()
387 	void __iomem *port_base = priv->port_base;  in _sc92031_disable_tx_rx()  local
391 	iowrite32(priv->rx_config, port_base + RxConfig);  in _sc92031_disable_tx_rx()
392 	iowrite32(priv->tx_config, port_base + TxConfig);  in _sc92031_disable_tx_rx()
398 	void __iomem *port_base = priv->port_base;  in _sc92031_enable_tx_rx()  local
402 	iowrite32(priv->rx_config, port_base + RxConfig);  in _sc92031_enable_tx_rx()
403 	iowrite32(priv->tx_config, port_base + TxConfig);  in _sc92031_enable_tx_rx()
420 	void __iomem *port_base = priv->port_base;  in _sc92031_set_mar()  local
451 	iowrite32(mar0, port_base + MAR0);  in _sc92031_set_mar()
452 	iowrite32(mar1, port_base + MAR0 + 4);  in _sc92031_set_mar()
458 	void __iomem *port_base = priv->port_base;  in _sc92031_set_rx_config()  local
482 		iowrite32(priv->rx_config, port_base + RxConfig);  in _sc92031_set_rx_config()
488 	void __iomem *port_base = priv->port_base;  in _sc92031_check_media()  local
491 	bmsr = _sc92031_mii_read(port_base, MII_BMSR);  in _sc92031_check_media()
496 		u16 output_status = _sc92031_mii_read(port_base,  in _sc92031_check_media()
498 		_sc92031_mii_scan(port_base);  in _sc92031_check_media()
527 		iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);  in _sc92031_check_media()
538 		_sc92031_mii_scan(port_base);  in _sc92031_check_media()
553 	void __iomem *port_base = priv->port_base;  in _sc92031_phy_reset()  local
556 	phy_ctrl = ioread32(port_base + PhyCtrl);  in _sc92031_phy_reset()
579 	iowrite32(phy_ctrl, port_base + PhyCtrl);  in _sc92031_phy_reset()
583 	iowrite32(phy_ctrl, port_base + PhyCtrl);  in _sc92031_phy_reset()
586 	_sc92031_mii_write(port_base, MII_JAB,  in _sc92031_phy_reset()
588 	_sc92031_mii_scan(port_base);  in _sc92031_phy_reset()
597 	void __iomem *port_base = priv->port_base;  in _sc92031_reset()  local
600 	iowrite32(0, port_base + PMConfig);  in _sc92031_reset()
603 	iowrite32(Cfg0_Reset, port_base + Config0);  in _sc92031_reset()
606 	iowrite32(0, port_base + Config0);  in _sc92031_reset()
610 	iowrite32(0, port_base + IntrMask);  in _sc92031_reset()
613 	iowrite32(0, port_base + MAR0);  in _sc92031_reset()
614 	iowrite32(0, port_base + MAR0 + 4);  in _sc92031_reset()
617 	iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);  in _sc92031_reset()
632 	iowrite32(Cfg1_Rcv64K, port_base + Config1);  in _sc92031_reset()
641 	iowrite32(priv->pm_config, port_base + PMConfig);  in _sc92031_reset()
644 	ioread32(port_base + IntrStatus);  in _sc92031_reset()
650 	void __iomem *port_base = priv->port_base;  in _sc92031_tx_tasklet()  local
659 		tx_status = ioread32(port_base + TxStatus0 + entry * 4);  in _sc92031_tx_tasklet()
723 	void __iomem *port_base = priv->port_base;  in _sc92031_rx_tasklet()  local
730 	rx_ring_head = ioread32(port_base + RxBufWPtr);  in _sc92031_rx_tasklet()
820 	iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);  in _sc92031_rx_tasklet()
837 	void __iomem *port_base = priv->port_base;  in sc92031_tasklet()  local
868 	iowrite32(intr_mask, port_base + IntrMask);  in sc92031_tasklet()
877 	void __iomem *port_base = priv->port_base;  in sc92031_interrupt()  local
881 	iowrite32(0, port_base + IntrMask);  in sc92031_interrupt()
882 	_sc92031_dummy_read(port_base);  in sc92031_interrupt()
884 	intr_status = ioread32(port_base + IntrStatus);  in sc92031_interrupt()
901 	iowrite32(intr_mask, port_base + IntrMask);  in sc92031_interrupt()
909 	void __iomem *port_base = priv->port_base;  in sc92031_get_stats()  local
918 		temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;  in sc92031_get_stats()
936 	void __iomem *port_base = priv->port_base;  in sc92031_start_xmit()  local
976 			port_base + TxAddr0 + entry * 4);  in sc92031_start_xmit()
977 	iowrite32(tx_status, port_base + TxStatus0 + entry * 4);  in sc92031_start_xmit()
1122 	void __iomem *port_base = priv->port_base;  in sc92031_ethtool_get_link_ksettings()  local
1130 	phy_address = ioread32(port_base + Miicmd1) >> 27;  in sc92031_ethtool_get_link_ksettings()
1131 	phy_ctrl = ioread32(port_base + PhyCtrl);  in sc92031_ethtool_get_link_ksettings()
1133 	output_status = _sc92031_mii_read(port_base, MII_OutputStatus);  in sc92031_ethtool_get_link_ksettings()
1134 	_sc92031_mii_scan(port_base);  in sc92031_ethtool_get_link_ksettings()
1185 	void __iomem *port_base = priv->port_base;  in sc92031_ethtool_set_link_ksettings()  local
1243 	old_phy_ctrl = ioread32(port_base + PhyCtrl);  in sc92031_ethtool_set_link_ksettings()
1247 		iowrite32(phy_ctrl, port_base + PhyCtrl);  in sc92031_ethtool_set_link_ksettings()
1258 	void __iomem *port_base = priv->port_base;  in sc92031_ethtool_get_wol()  local
1262 	pm_config = ioread32(port_base + PMConfig);  in sc92031_ethtool_get_wol()
1285 	void __iomem *port_base = priv->port_base;  in sc92031_ethtool_set_wol()  local
1290 	pm_config = ioread32(port_base + PMConfig)  in sc92031_ethtool_set_wol()
1304 	iowrite32(pm_config, port_base + PMConfig);  in sc92031_ethtool_set_wol()
1315 	void __iomem *port_base = priv->port_base;  in sc92031_ethtool_nway_reset()  local
1320 	bmcr = _sc92031_mii_read(port_base, MII_BMCR);  in sc92031_ethtool_nway_reset()
1326 	_sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);  in sc92031_ethtool_nway_reset()
1329 	_sc92031_mii_scan(port_base);  in sc92031_ethtool_nway_reset()
1400 	void __iomem* port_base;  in sc92031_probe()  local
1424 	port_base = pci_iomap(pdev, SC92031_USE_PIO, 0);  in sc92031_probe()
1425 	if (unlikely(!port_base)) {  in sc92031_probe()
1450 	priv->port_base = port_base;  in sc92031_probe()
1458 	iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);  in sc92031_probe()
1460 	mac0 = ioread32(port_base + MAC0);  in sc92031_probe()
1461 	mac1 = ioread32(port_base + MAC0 + 4);  in sc92031_probe()
1483 	pci_iounmap(pdev, port_base);  in sc92031_probe()
1497 	void __iomem* port_base = priv->port_base;  in sc92031_remove()  local
1501 	pci_iounmap(pdev, port_base);  in sc92031_remove()