Lines Matching +full:wire +full:- +full:or

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  * Copyright 2020-2022 Xilinx Inc.
7  * This program is free software; you can redistribute it and/or modify it
19  * insertion is not supported; errors in internal operation or in the
25 	if (efx->log_tc_errs)						\
26 		netif_info(efx, drv, efx->net_dev, "%s\n", message);	\
32 if (efx->log_tc_errs)					\
33 	netif_info(efx, drv, efx->net_dev, fmt, ##args);\
74  * struct efx_tc_state - control plane data for TC offload
79  * @match_action_ht: Hashtable of TC match-action rules
84  * @dflt: Match-action rules for default switching; at priority
86  * @dflt.pf: rule for traffic ingressing from PF (egresses to wire)
87  * @dflt.wire: rule for traffic ingressing from wire (egresses to PF)
99 		struct efx_tc_flow_rule wire;  member