53 				     FRF_CZ_TC_TIMER_VAL, 0);  in siena_push_irq_moderation()
61 	if (efx->fc_disable++ == 0)  in efx_siena_prepare_flush()
67 	if (--efx->fc_disable == 0)  in siena_finish_flush()
73 	  EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
75 	  EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
77 	  EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
79 	  EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
81 	  EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
83 	  EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
85 	  EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
87 	  EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
89 	  EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
91 	  EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
93 	  EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
95 	  EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
97 	  EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
121 	rc2 = efx_siena_reset_up(efx, reset_method, rc == 0);  in siena_test_chip()
165 		if (rc != 0)  in siena_ptp_set_ts_config()
223 	u32 caps = 0;  in siena_probe_nvconfig()
245 	return 0;  in siena_dimension_resources()
248 /* On all Falcon-architecture NICs, PFs use BAR 0 for I/O space and BAR 2(&3)
275 	if (efx_farch_fpga_ver(efx) != 0) {  in siena_probe_nic()
308 	BUG_ON(efx->irq_status.dma_addr & 0x0f);  in siena_probe_nic()
336 	return 0;  in siena_probe_nic()
365 	return 0;  in siena_rx_pull_rss_config()
382 		     FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);  in siena_rx_push_rss_config()
397 	return 0;  in siena_rx_push_rss_config()
423 	EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);  in siena_init_nic()
428 	EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);  in siena_init_nic()
441 	efx->rss_context.context_id = 0; /* indicates RSS is active */  in siena_init_nic()
444 	rc = efx_siena_mcdi_log_ctrl(efx, true, false, 0);  in siena_init_nic()
449 	EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);  in siena_init_nic()
456 	return 0;  in siena_init_nic()
479 	[SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
481 	[GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
545 	[0 ... BITS_TO_LONGS(SIENA_STAT_COUNT) - 1] = ~0UL,
565 		return 0;  in siena_try_update_nic_stats()
589 	return 0;  in siena_try_update_nic_stats()
601 	for (retry = 0; retry < 100; ++retry) {  in siena_update_nic_stats()
602 		if (siena_try_update_nic_stats(efx) == 0)  in siena_update_nic_stats()
654 	if (rc != 0)  in siena_mac_reconfigure()
660 				  inbuf, sizeof(inbuf), NULL, 0, NULL);  in siena_mac_reconfigure()
678 		wol->wolopts = 0;  in siena_get_wol()
679 	memset(&wol->sopass, 0, sizeof(wol->sopass));  in siena_get_wol()
710 	return 0;  in siena_set_wol()
725 	if (rc != 0) {  in siena_init_wol()
762 	for (i = 0; i < inlen_dw; i++)  in siena_mcdi_request()
769 	_efx_writed(efx, (__force __le32) 0x45789abc, doorbell);  in siena_mcdi_request()
783 	return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&  in siena_mcdi_poll_response()
794 	for (i = 0; i < outlen_dw; i++)  in siena_mcdi_read_response()
808 	if (value == 0)  in siena_mcdi_poll_reboot()
809 		return 0;  in siena_mcdi_poll_reboot()
817 	nic_data->stats[SIENA_STAT_tx_good_bytes] = 0;  in siena_mcdi_poll_reboot()
818 	nic_data->stats[SIENA_STAT_rx_good_bytes] = 0;  in siena_mcdi_poll_reboot()
841 	[MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO]	= { 0, "sfc_dummy_phy" },
842 	[MC_CMD_NVRAM_TYPE_MC_FW]		= { 0, "sfc_mcfw" },
843 	[MC_CMD_NVRAM_TYPE_MC_FW_BACKUP]	= { 0, "sfc_mcfw_backup" },
844 	[MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0]	= { 0, "sfc_static_cfg" },
846 	[MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0]	= { 0, "sfc_dynamic_cfg" },
848 	[MC_CMD_NVRAM_TYPE_EXP_ROM]		= { 0, "sfc_exp_rom" },
849 	[MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0]	= { 0, "sfc_exp_rom_cfg" },
851 	[MC_CMD_NVRAM_TYPE_PHY_PORT0]		= { 0, "sfc_phy_fw" },
853 	[MC_CMD_NVRAM_TYPE_FPGA]		= { 0, "sfc_fpga" },
890 	return 0;  in siena_mtd_probe_partition()
906 	for (i = 0; i < n_parts; i++)  in siena_mtd_get_fw_subtypes()
909 	return 0;  in siena_mtd_get_fw_subtypes()
930 	type = 0;  in siena_mtd_probe()
931 	n_parts = 0;  in siena_mtd_probe()
933 	while (nvram_types != 0) {  in siena_mtd_probe()
937 			if (rc == 0)  in siena_mtd_probe()
950 	rc = efx_siena_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));  in siena_mtd_probe()
963 	return 0;  in siena_check_caps()
1097 	.rx_buffer_padding = 0,