Lines Matching +full:tx +full:- +full:ping +full:- +full:pong
1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2005-2013 Solarflare Communications Inc.
61 /* Checksum generation is a per-queue option in hardware, so each
62 * queue visible to the networking core is backed by two hardware TX
68 #define EFX_TXQ_TYPE_HIGHPRI 4 /* High-priority (for TC) */
70 /* HIGHPRI is Siena-only, and INNER_CSUM is EF10, so no need for both */
86 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
89 * of every buffer. Otherwise, we just need to ensure 4-byte
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
111 * struct efx_buffer - A general-purpose DMA buffer
126 * struct efx_special_buffer - DMA buffer entered into buffer table
133 * table entries (and so can be physically non-contiguous, although we
146 * struct efx_tx_buffer - buffer state for a TX descriptor
151 * @option: When @flags & %EFX_TX_BUF_OPTION, an EF10-specific option
184 * struct efx_tx_queue - An Efx TX queue
186 * This is a ring buffer of TX fragments.
187 * Since the TX completion path always executes on the same
198 * @label: Label for TX completion events.
199 * Is our index within @channel->tx_queue array.
200 * @type: configuration type of this TX queue. A bitmask of %EFX_TXQ_TYPE_* flags.
204 * @core_txq: The networking core TX queue structure
207 * %EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
210 * @piobuf: PIO buffer region for this TX queue (shared with its partner).
215 * @xdp_tx: Is this an XDP tx queue?
220 * only get the up-to-date value of @write_count if this
222 * avoid cache-line ping-pong between the xmit path and the
224 * @merge_events: Number of TX merged completion events
225 * @completed_timestamp_major: Top part of the most recent tx timestamp.
226 * @completed_timestamp_minor: Low part of the most recent tx timestamp.
237 * Filled in iff @efx->type->option_descriptors; only used for PIO.
241 * only get the up-to-date value of read_count if this
243 * avoid cache-line ping-pong between the xmit path and the
250 * @pushes: Number of times the TX push feature has been used
251 * @pio_packets: Number of times the TX PIO feature has been used
253 * @cb_packets: Number of times the TX copybreak feature has been used
257 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
312 #define EFX_TX_CB_SIZE (1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
315 * struct efx_rx_buffer - An Efx RX data buffer
341 * struct efx_rx_page_state - Page-based rx buffer state
356 * struct efx_rx_queue - An Efx RX queue
383 * @min_fill: RX descriptor minimum non-zero fill level.
433 * struct efx_channel - An Efx channel
435 * A channel comprises an event queue, at least one TX queue, at least
444 * @irq: IRQ number (MSI and MSI-X only)
489 * @tx_queue: TX queues for this channel
562 * struct efx_msi_context - Context for each MSI
577 * struct efx_channel_type - distinguishes traffic and extra channels
586 * @want_txqs: Determine whether this channel should have TX queues
587 * created. If %NULL, TX queues are not created.
591 * channel's TX queues.
617 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
626 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
681 /* Pseudo bit-mask flow control field */
687 * struct efx_link_state - Current state of the link
689 * @fd: Link is full-duplex
703 return left->up == right->up && left->fd == right->fd &&
704 left->fc == right->fc && left->speed == right->speed;
708 * enum efx_phy_mode - PHY operating mode flags
710 * @PHY_MODE_TX_DISABLED: on with TX disabled
729 * struct efx_hw_stat_desc - Description of a hardware statistic
732 * @dma_width: Width in bits (0 for non-DMA statistics)
733 * @offset: Offset within stats (ignored for non-DMA statistics)
744 /* Number of (single-bit) entries in a multicast filter hash */
758 * struct efx_rss_context - A user-defined RSS context for filtering
764 * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
781 #define EFX_ARFS_FILTER_ID_PENDING -1
782 #define EFX_ARFS_FILTER_ID_ERROR -2
783 #define EFX_ARFS_FILTER_ID_REMOVING -3
785 * struct efx_arfs_rule - record of an ARFS filter and its IDs
787 * @spec: details of the filter (used as key for hash table). Use efx->type to
808 * struct efx_async_filter_insertion - Request to asynchronously insert a filter
813 * @flow_id: Identifies the kernel-side flow for which this request was made
834 * struct efx_nic - an Efx NIC
852 * @vi_stride: step between per-VI registers / memory regions
864 * @tx_queue: TX DMA queues
868 * @extra_channel_types: Types of extra (non-traffic) channels that
871 * @xdp_tx_queues: Array of pointers to tx queues used for XDP transmit.
872 * @xdp_txq_queues_mode: XDP TX queues sharing strategy.
875 * @txq_stop_thresh: TX queue fill level at or above which we stop it.
876 * @txq_wake_thresh: TX queue fill level at or below which we wake it.
877 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
883 * @n_tx_channels: Number of channels used for TX
884 * @n_extra_tx_channels: Number of extra channels with TX queues
885 * @tx_queues_per_channel: number of TX queues probed on each channel
886 * @n_xdp_channels: Number of channels used for XDP TX
887 * @xdp_channel_offset: Offset of zeroth channel used for XPD TX.
888 * @xdp_tx_per_channel: Max number of TX queues on an XDP TX channel.
901 * (valid only if channel->sync_timestamps_enabled; always negative)
910 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
915 * @selftest_work: Work item for asynchronous self-test
918 * @mcdi: Management-Controller-to-Driver Interface state
933 * @phy_data: PHY private data (including PHY-specific stats)
942 * @unicast_filter: Flag for Falcon-arch simple unicast filter.
944 * @multicast_hash: Multicast hash table for Falcon-arch.
947 * @fc_disable: When non-zero flow control is disabled. Typically used to
953 * @loopback_selftest: Offline self-test private state
956 * @filter_state: Architecture-dependent filter table state
958 * @rps_slot_map: bitmap of in-flight entries in @rps_slot
964 * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
1182 * struct efx_probe_data - State after hardware probe
1196 return &probe_data->efx;
1201 return efx->net_dev->reg_state == NETREG_REGISTERED;
1206 return efx->port_num;
1224 * struct efx_nic_type - Efx device type definition
1241 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1259 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1271 * The SDU length may be any value from 0 up to the protocol-
1284 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
1290 * @tx_probe: Allocate resources for TX queue (and select TXQ type)
1291 * @tx_init: Initialise TX queue on the NIC
1292 * @tx_remove: Free resources for TX queue
1293 * @tx_write: Write TX descriptors and doorbell
1294 * @tx_enqueue: Add an SKB to TX queue
1336 * @mtd_sync: Wait for write-back to complete on MTD partition. This
1347 * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1351 * @print_additional_fwver: Dump NIC-specific additional FW version info
1355 * @txd_ptr_tbl_base: TX descriptor ring base address
1359 * @evq_rptr_tbl_base: Event queue read-pointer table base address
1367 * @option_descriptors: NIC supports TX option descriptors
1566 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels);
1567 return efx->channel[index];
1572 for (_channel = (_efx)->channel[0]; \
1574 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
1575 (_efx)->channel[_channel->channel + 1] : NULL)
1579 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
1581 _channel = _channel->channel ? \
1582 (_efx)->channel[_channel->channel - 1] : NULL)
1587 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels);
1588 return efx->channel[efx->tx_channel_offset + index];
1594 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_xdp_channels);
1595 return efx->channel[efx->xdp_channel_offset + index];
1600 return channel->channel - channel->efx->xdp_channel_offset <
1601 channel->efx->n_xdp_channels;
1606 return channel && channel->channel >= channel->efx->tx_channel_offset;
1612 return channel->efx->xdp_tx_per_channel;
1613 return channel->efx->tx_queues_per_channel;
1620 return channel->tx_queue_by_type[type];
1631 /* Iterate over all TX queues belonging to a channel */
1636 for (_tx_queue = (_channel)->tx_queue; \
1637 _tx_queue < (_channel)->tx_queue + \
1643 return channel->rx_queue.core_index >= 0;
1650 return &channel->rx_queue;
1658 for (_rx_queue = &(_channel)->rx_queue; \
1670 return efx_rx_queue_channel(rx_queue)->channel;
1679 return &rx_queue->buffer[index];
1685 if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))
1692 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1700 * The 10G MAC requires 8-byte alignment on the frame
1703 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1714 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1718 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1721 /* Get the max fill level of the TX queues on this channel */
1730 tx_queue->insert_count - tx_queue->read_count);
1744 tx_queue->insert_count - tx_queue->old_read_count);
1756 const struct net_device *net_dev = efx->net_dev;
1758 return net_dev->features | net_dev->hw_features;
1761 /* Get the current TX queue insert index. */
1765 return tx_queue->insert_count & tx_queue->ptr_mask;
1768 /* Get a TX buffer. */
1772 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
1775 /* Get a TX buffer, checking it's not currently in use. */
1782 EFX_WARN_ON_ONCE_PARANOID(buffer->len);
1783 EFX_WARN_ON_ONCE_PARANOID(buffer->flags);
1784 EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len);