Lines Matching +full:rx +full:- +full:tx +full:- +full:swap
1 // SPDX-License-Identifier: GPL-2.0-only
24 * 0 => MSI-X
30 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
34 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
62 netif_warn(efx, probe, efx->net_dev, in count_online_cores()
70 cpumask_of_pcibus(efx->pci_dev->bus)); in count_online_cores()
98 netif_cond_dbg(efx, probe, efx->net_dev, !rss_cpus, warn, in efx_wanted_parallelism()
99 "Reducing number of rx queues from %u to %u.\n", in efx_wanted_parallelism()
108 if (efx->type->sriov_wanted) { in efx_wanted_parallelism()
109 if (efx->type->sriov_wanted(efx) && efx_vf_size(efx) > 1 && in efx_wanted_parallelism()
111 netif_warn(efx, probe, efx->net_dev, in efx_wanted_parallelism()
113 "VF support. Increase vf-msix-limit to use more " in efx_wanted_parallelism()
140 * we allocate a TX queue per CPU. We share event queues across in efx_allocate_msix_channels()
141 * multiple tx queues, assuming tx and ev queues are both in efx_allocate_msix_channels()
149 vec_count = pci_msix_vec_count(efx->pci_dev); in efx_allocate_msix_channels()
156 * We need a channel per event queue, plus a VI per tx queue. in efx_allocate_msix_channels()
160 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED; in efx_allocate_msix_channels()
161 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
164 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
166 } else if (n_channels + n_xdp_tx > efx->max_vis) { in efx_allocate_msix_channels()
167 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_BORROWED; in efx_allocate_msix_channels()
168 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
169 "Insufficient resources for %d XDP TX queues (%d other channels, max VIs %d)\n", in efx_allocate_msix_channels()
170 n_xdp_tx, n_channels, efx->max_vis); in efx_allocate_msix_channels()
171 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
174 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_SHARED; in efx_allocate_msix_channels()
175 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
179 n_xdp_ev = max_channels - n_channels; in efx_allocate_msix_channels()
180 netif_warn(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
184 efx->xdp_txq_queues_mode = EFX_XDP_TX_QUEUES_DEDICATED; in efx_allocate_msix_channels()
187 if (efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_BORROWED) { in efx_allocate_msix_channels()
188 efx->n_xdp_channels = n_xdp_ev; in efx_allocate_msix_channels()
189 efx->xdp_tx_per_channel = tx_per_ev; in efx_allocate_msix_channels()
190 efx->xdp_tx_queue_count = n_xdp_tx; in efx_allocate_msix_channels()
192 netif_dbg(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
193 "Allocating %d TX and %d event queues for XDP\n", in efx_allocate_msix_channels()
196 efx->n_xdp_channels = 0; in efx_allocate_msix_channels()
197 efx->xdp_tx_per_channel = 0; in efx_allocate_msix_channels()
198 efx->xdp_tx_queue_count = n_xdp_tx; in efx_allocate_msix_channels()
202 netif_err(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
203 "WARNING: Insufficient MSI-X vectors available (%d < %u).\n", in efx_allocate_msix_channels()
205 netif_err(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
212 efx->n_channels = n_channels; in efx_allocate_msix_channels()
214 /* Ignore XDP tx channels when creating rx channels. */ in efx_allocate_msix_channels()
215 n_channels -= efx->n_xdp_channels; in efx_allocate_msix_channels()
218 efx->n_tx_channels = in efx_allocate_msix_channels()
220 efx->max_tx_channels); in efx_allocate_msix_channels()
221 efx->tx_channel_offset = in efx_allocate_msix_channels()
222 n_channels - efx->n_tx_channels; in efx_allocate_msix_channels()
223 efx->n_rx_channels = in efx_allocate_msix_channels()
224 max(n_channels - in efx_allocate_msix_channels()
225 efx->n_tx_channels, 1U); in efx_allocate_msix_channels()
227 efx->n_tx_channels = min(n_channels, efx->max_tx_channels); in efx_allocate_msix_channels()
228 efx->tx_channel_offset = 0; in efx_allocate_msix_channels()
229 efx->n_rx_channels = n_channels; in efx_allocate_msix_channels()
232 efx->n_rx_channels = min(efx->n_rx_channels, parallelism); in efx_allocate_msix_channels()
233 efx->n_tx_channels = min(efx->n_tx_channels, parallelism); in efx_allocate_msix_channels()
235 efx->xdp_channel_offset = n_channels; in efx_allocate_msix_channels()
237 netif_dbg(efx, drv, efx->net_dev, in efx_allocate_msix_channels()
238 "Allocating %u RX channels\n", in efx_allocate_msix_channels()
239 efx->n_rx_channels); in efx_allocate_msix_channels()
241 return efx->n_channels; in efx_allocate_msix_channels()
245 * the resulting numbers of channels and RX queues.
255 if (efx->extra_channel_type[i]) in efx_probe_interrupts()
258 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { in efx_probe_interrupts()
263 rc = efx_allocate_msix_channels(efx, efx->max_channels, in efx_probe_interrupts()
269 rc = pci_enable_msix_range(efx->pci_dev, xentries, 1, in efx_probe_interrupts()
274 netif_err(efx, drv, efx->net_dev, in efx_probe_interrupts()
275 "could not enable MSI-X\n"); in efx_probe_interrupts()
276 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_MSI) in efx_probe_interrupts()
277 efx->interrupt_mode = EFX_INT_MODE_MSI; in efx_probe_interrupts()
281 netif_err(efx, drv, efx->net_dev, in efx_probe_interrupts()
282 "WARNING: Insufficient MSI-X vectors" in efx_probe_interrupts()
284 netif_err(efx, drv, efx->net_dev, in efx_probe_interrupts()
290 for (i = 0; i < efx->n_channels; i++) in efx_probe_interrupts()
291 efx_get_channel(efx, i)->irq = in efx_probe_interrupts()
297 if (efx->interrupt_mode == EFX_INT_MODE_MSI) { in efx_probe_interrupts()
298 efx->n_channels = 1; in efx_probe_interrupts()
299 efx->n_rx_channels = 1; in efx_probe_interrupts()
300 efx->n_tx_channels = 1; in efx_probe_interrupts()
301 efx->tx_channel_offset = 0; in efx_probe_interrupts()
302 efx->n_xdp_channels = 0; in efx_probe_interrupts()
303 efx->xdp_channel_offset = efx->n_channels; in efx_probe_interrupts()
304 rc = pci_enable_msi(efx->pci_dev); in efx_probe_interrupts()
306 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; in efx_probe_interrupts()
308 netif_err(efx, drv, efx->net_dev, in efx_probe_interrupts()
310 if (efx->type->min_interrupt_mode >= EFX_INT_MODE_LEGACY) in efx_probe_interrupts()
311 efx->interrupt_mode = EFX_INT_MODE_LEGACY; in efx_probe_interrupts()
318 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { in efx_probe_interrupts()
319 efx->n_channels = 1 + (efx_separate_tx_channels ? 1 : 0); in efx_probe_interrupts()
320 efx->n_rx_channels = 1; in efx_probe_interrupts()
321 efx->n_tx_channels = 1; in efx_probe_interrupts()
322 efx->tx_channel_offset = efx_separate_tx_channels ? 1 : 0; in efx_probe_interrupts()
323 efx->n_xdp_channels = 0; in efx_probe_interrupts()
324 efx->xdp_channel_offset = efx->n_channels; in efx_probe_interrupts()
325 efx->legacy_irq = efx->pci_dev->irq; in efx_probe_interrupts()
329 efx->n_extra_tx_channels = 0; in efx_probe_interrupts()
330 j = efx->xdp_channel_offset; in efx_probe_interrupts()
332 if (!efx->extra_channel_type[i]) in efx_probe_interrupts()
334 if (j <= efx->tx_channel_offset + efx->n_tx_channels) { in efx_probe_interrupts()
335 efx->extra_channel_type[i]->handle_no_channel(efx); in efx_probe_interrupts()
337 --j; in efx_probe_interrupts()
338 efx_get_channel(efx, j)->type = in efx_probe_interrupts()
339 efx->extra_channel_type[i]; in efx_probe_interrupts()
341 efx->n_extra_tx_channels++; in efx_probe_interrupts()
345 rss_spread = efx->n_rx_channels; in efx_probe_interrupts()
348 if (efx->type->sriov_wanted) { in efx_probe_interrupts()
349 efx->rss_spread = ((rss_spread > 1 || in efx_probe_interrupts()
350 !efx->type->sriov_wanted(efx)) ? in efx_probe_interrupts()
355 efx->rss_spread = rss_spread; in efx_probe_interrupts()
363 const struct cpumask *numa_mask = cpumask_of_pcibus(efx->pci_dev->bus); in efx_set_interrupt_affinity()
371 cpu = -1; in efx_set_interrupt_affinity()
376 irq_set_affinity_hint(channel->irq, cpumask_of(cpu)); in efx_set_interrupt_affinity()
385 irq_set_affinity_hint(channel->irq, NULL); in efx_clear_interrupt_affinity()
403 /* Remove MSI/MSI-X interrupts */ in efx_remove_interrupts()
405 channel->irq = 0; in efx_remove_interrupts()
406 pci_disable_msi(efx->pci_dev); in efx_remove_interrupts()
407 pci_disable_msix(efx->pci_dev); in efx_remove_interrupts()
410 efx->legacy_irq = 0; in efx_remove_interrupts()
424 struct efx_nic *efx = channel->efx; in efx_probe_eventq()
427 netif_dbg(efx, probe, efx->net_dev, in efx_probe_eventq()
428 "chan %d create event queue\n", channel->channel); in efx_probe_eventq()
430 /* Build an event queue with room for one event per tx and rx buffer, in efx_probe_eventq()
433 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); in efx_probe_eventq()
435 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; in efx_probe_eventq()
443 struct efx_nic *efx = channel->efx; in efx_init_eventq()
446 EFX_WARN_ON_PARANOID(channel->eventq_init); in efx_init_eventq()
448 netif_dbg(efx, drv, efx->net_dev, in efx_init_eventq()
449 "chan %d init event queue\n", channel->channel); in efx_init_eventq()
453 efx->type->push_irq_moderation(channel); in efx_init_eventq()
454 channel->eventq_read_ptr = 0; in efx_init_eventq()
455 channel->eventq_init = true; in efx_init_eventq()
463 netif_dbg(channel->efx, ifup, channel->efx->net_dev, in efx_start_eventq()
464 "chan %d start event queue\n", channel->channel); in efx_start_eventq()
467 channel->enabled = true; in efx_start_eventq()
470 napi_enable(&channel->napi_str); in efx_start_eventq()
477 if (!channel->enabled) in efx_stop_eventq()
480 napi_disable(&channel->napi_str); in efx_stop_eventq()
481 channel->enabled = false; in efx_stop_eventq()
486 if (!channel->eventq_init) in efx_fini_eventq()
489 netif_dbg(channel->efx, drv, channel->efx->net_dev, in efx_fini_eventq()
490 "chan %d fini event queue\n", channel->channel); in efx_fini_eventq()
493 channel->eventq_init = false; in efx_fini_eventq()
498 netif_dbg(channel->efx, drv, channel->efx->net_dev, in efx_remove_eventq()
499 "chan %d remove event queue\n", channel->channel); in efx_remove_eventq()
518 time = jiffies - channel->rfs_last_expiry; in efx_filter_rfs_expire()
519 quota = channel->rfs_filter_count * time / (30 * HZ); in efx_filter_rfs_expire()
520 if (quota >= 20 && __efx_filter_rfs_expire(channel, min(channel->rfs_filter_count, quota))) in efx_filter_rfs_expire()
521 channel->rfs_last_expiry += time; in efx_filter_rfs_expire()
539 channel->efx = efx; in efx_alloc_channel()
540 channel->channel = i; in efx_alloc_channel()
541 channel->type = &efx_default_channel_type; in efx_alloc_channel()
544 tx_queue = &channel->tx_queue[j]; in efx_alloc_channel()
545 tx_queue->efx = efx; in efx_alloc_channel()
546 tx_queue->queue = -1; in efx_alloc_channel()
547 tx_queue->label = j; in efx_alloc_channel()
548 tx_queue->channel = channel; in efx_alloc_channel()
552 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); in efx_alloc_channel()
555 rx_queue = &channel->rx_queue; in efx_alloc_channel()
556 rx_queue->efx = efx; in efx_alloc_channel()
557 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0); in efx_alloc_channel()
567 efx->channel[i] = efx_alloc_channel(efx, i); in efx_init_channels()
568 if (!efx->channel[i]) in efx_init_channels()
569 return -ENOMEM; in efx_init_channels()
570 efx->msi_context[i].efx = efx; in efx_init_channels()
571 efx->msi_context[i].index = i; in efx_init_channels()
575 efx->interrupt_mode = min(efx->type->min_interrupt_mode, in efx_init_channels()
578 efx->max_channels = EFX_MAX_CHANNELS; in efx_init_channels()
579 efx->max_tx_channels = EFX_MAX_CHANNELS; in efx_init_channels()
589 if (efx->channel[i]) { in efx_fini_channels()
590 kfree(efx->channel[i]); in efx_fini_channels()
591 efx->channel[i] = NULL; in efx_fini_channels()
611 channel->napi_dev = NULL; in efx_copy_channel()
612 INIT_HLIST_NODE(&channel->napi_str.napi_hash_node); in efx_copy_channel()
613 channel->napi_str.napi_id = 0; in efx_copy_channel()
614 channel->napi_str.state = 0; in efx_copy_channel()
615 memset(&channel->eventq, 0, sizeof(channel->eventq)); in efx_copy_channel()
618 tx_queue = &channel->tx_queue[j]; in efx_copy_channel()
619 if (tx_queue->channel) in efx_copy_channel()
620 tx_queue->channel = channel; in efx_copy_channel()
621 tx_queue->buffer = NULL; in efx_copy_channel()
622 tx_queue->cb_page = NULL; in efx_copy_channel()
623 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); in efx_copy_channel()
626 rx_queue = &channel->rx_queue; in efx_copy_channel()
627 rx_queue->buffer = NULL; in efx_copy_channel()
628 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); in efx_copy_channel()
629 timer_setup(&rx_queue->slow_fill, efx_rx_slow_fill, 0); in efx_copy_channel()
631 INIT_DELAYED_WORK(&channel->filter_work, efx_filter_rfs_expire); in efx_copy_channel()
643 netif_dbg(channel->efx, probe, channel->efx->net_dev, in efx_probe_channel()
644 "creating channel %d\n", channel->channel); in efx_probe_channel()
646 rc = channel->type->pre_probe(channel); in efx_probe_channel()
666 channel->rx_list = NULL; in efx_probe_channel()
678 struct efx_nic *efx = channel->efx; in efx_get_channel_name()
682 number = channel->channel; in efx_get_channel_name()
684 if (number >= efx->xdp_channel_offset && in efx_get_channel_name()
685 !WARN_ON_ONCE(!efx->n_xdp_channels)) { in efx_get_channel_name()
686 type = "-xdp"; in efx_get_channel_name()
687 number -= efx->xdp_channel_offset; in efx_get_channel_name()
688 } else if (efx->tx_channel_offset == 0) { in efx_get_channel_name()
690 } else if (number < efx->tx_channel_offset) { in efx_get_channel_name()
691 type = "-rx"; in efx_get_channel_name()
693 type = "-tx"; in efx_get_channel_name()
694 number -= efx->tx_channel_offset; in efx_get_channel_name()
696 snprintf(buf, len, "%s%s-%d", efx->name, type, number); in efx_get_channel_name()
704 channel->type->get_name(channel, in efx_set_channel_names()
705 efx->msi_context[channel->channel].name, in efx_set_channel_names()
706 sizeof(efx->msi_context[0].name)); in efx_set_channel_names()
715 efx->next_buffer_table = 0; in efx_probe_channels()
725 netif_err(efx, probe, efx->net_dev, in efx_probe_channels()
727 channel->channel); in efx_probe_channels()
745 netif_dbg(channel->efx, drv, channel->efx->net_dev, in efx_remove_channel()
746 "destroy chan %d\n", channel->channel); in efx_remove_channel()
753 channel->type->post_remove(channel); in efx_remove_channel()
763 kfree(efx->xdp_tx_queues); in efx_remove_channels()
769 if (xdp_queue_number >= efx->xdp_tx_queue_count) in efx_set_xdp_tx_queue()
770 return -EINVAL; in efx_set_xdp_tx_queue()
772 netif_dbg(efx, drv, efx->net_dev, in efx_set_xdp_tx_queue()
774 tx_queue->channel->channel, tx_queue->label, in efx_set_xdp_tx_queue()
775 xdp_queue_number, tx_queue->queue); in efx_set_xdp_tx_queue()
776 efx->xdp_tx_queues[xdp_queue_number] = tx_queue; in efx_set_xdp_tx_queue()
788 /* We need to mark which channels really have RX and TX in efx_set_xdp_channels()
789 * queues, and adjust the TX queue numbers if we have separate in efx_set_xdp_channels()
790 * RX-only and TX-only channels. in efx_set_xdp_channels()
793 if (channel->channel < efx->tx_channel_offset) in efx_set_xdp_channels()
798 tx_queue->queue = next_queue++; in efx_set_xdp_channels()
806 tx_queue->queue = next_queue++; in efx_set_xdp_channels()
807 netif_dbg(efx, drv, efx->net_dev, in efx_set_xdp_channels()
809 channel->channel, tx_queue->label, in efx_set_xdp_channels()
810 tx_queue->queue); in efx_set_xdp_channels()
818 if (efx->xdp_txq_queues_mode == in efx_set_xdp_channels()
820 tx_queue = &channel->tx_queue[0]; in efx_set_xdp_channels()
828 WARN_ON(efx->xdp_txq_queues_mode == EFX_XDP_TX_QUEUES_DEDICATED && in efx_set_xdp_channels()
829 xdp_queue_number != efx->xdp_tx_queue_count); in efx_set_xdp_channels()
830 WARN_ON(efx->xdp_txq_queues_mode != EFX_XDP_TX_QUEUES_DEDICATED && in efx_set_xdp_channels()
831 xdp_queue_number > efx->xdp_tx_queue_count); in efx_set_xdp_channels()
833 /* If we have more CPUs than assigned XDP TX queues, assign the already in efx_set_xdp_channels()
837 while (xdp_queue_number < efx->xdp_tx_queue_count) { in efx_set_xdp_channels()
838 tx_queue = efx->xdp_tx_queues[next_queue++]; in efx_set_xdp_channels()
849 struct efx_ptp_data *ptp_data = efx->ptp_data; in efx_realloc_channels()
865 if (channel->type->copy) in efx_realloc_channels()
868 channel->eventq.index + in efx_realloc_channels()
869 channel->eventq.entries); in efx_realloc_channels()
872 rx_queue->rxd.index + in efx_realloc_channels()
873 rx_queue->rxd.entries); in efx_realloc_channels()
876 tx_queue->txd.index + in efx_realloc_channels()
877 tx_queue->txd.entries); in efx_realloc_channels()
886 for (i = 0; i < efx->n_channels; i++) { in efx_realloc_channels()
887 channel = efx->channel[i]; in efx_realloc_channels()
888 if (channel->type->copy) in efx_realloc_channels()
889 channel = channel->type->copy(channel); in efx_realloc_channels()
891 rc = -ENOMEM; in efx_realloc_channels()
897 /* Swap entry counts and channel pointers */ in efx_realloc_channels()
898 old_rxq_entries = efx->rxq_entries; in efx_realloc_channels()
899 old_txq_entries = efx->txq_entries; in efx_realloc_channels()
900 efx->rxq_entries = rxq_entries; in efx_realloc_channels()
901 efx->txq_entries = txq_entries; in efx_realloc_channels()
902 for (i = 0; i < efx->n_channels; i++) in efx_realloc_channels()
903 swap(efx->channel[i], other_channel[i]); in efx_realloc_channels()
906 efx->next_buffer_table = next_buffer_table; in efx_realloc_channels()
908 for (i = 0; i < efx->n_channels; i++) { in efx_realloc_channels()
909 channel = efx->channel[i]; in efx_realloc_channels()
910 if (!channel->type->copy) in efx_realloc_channels()
915 efx_init_napi_channel(efx->channel[i]); in efx_realloc_channels()
920 efx->ptp_data = NULL; in efx_realloc_channels()
922 for (i = 0; i < efx->n_channels; i++) { in efx_realloc_channels()
924 if (channel && channel->type->copy) { in efx_realloc_channels()
931 efx->ptp_data = ptp_data; in efx_realloc_channels()
935 netif_err(efx, drv, efx->net_dev, in efx_realloc_channels()
945 /* Swap back */ in efx_realloc_channels()
946 efx->rxq_entries = old_rxq_entries; in efx_realloc_channels()
947 efx->txq_entries = old_txq_entries; in efx_realloc_channels()
948 for (i = 0; i < efx->n_channels; i++) in efx_realloc_channels()
949 swap(efx->channel[i], other_channel[i]); in efx_realloc_channels()
959 if (efx->xdp_tx_queue_count) { in efx_set_channels()
960 EFX_WARN_ON_PARANOID(efx->xdp_tx_queues); in efx_set_channels()
962 /* Allocate array for XDP TX queue lookup. */ in efx_set_channels()
963 efx->xdp_tx_queues = kcalloc(efx->xdp_tx_queue_count, in efx_set_channels()
964 sizeof(*efx->xdp_tx_queues), in efx_set_channels()
966 if (!efx->xdp_tx_queues) in efx_set_channels()
967 return -ENOMEM; in efx_set_channels()
971 if (channel->channel < efx->n_rx_channels) in efx_set_channels()
972 channel->rx_queue.core_index = channel->channel; in efx_set_channels()
974 channel->rx_queue.core_index = -1; in efx_set_channels()
979 rc = netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); in efx_set_channels()
982 return netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); in efx_set_channels()
987 return channel->channel - channel->efx->tx_channel_offset < in efx_default_channel_want_txqs()
988 channel->efx->n_tx_channels; in efx_default_channel_want_txqs()
1000 BUG_ON(efx->state == STATE_DISABLED); in efx_soft_enable_interrupts()
1002 efx->irq_soft_enabled = true; in efx_soft_enable_interrupts()
1006 if (!channel->type->keep_eventq) { in efx_soft_enable_interrupts()
1023 if (!channel->type->keep_eventq) in efx_soft_enable_interrupts()
1034 if (efx->state == STATE_DISABLED) in efx_soft_disable_interrupts()
1039 efx->irq_soft_enabled = false; in efx_soft_disable_interrupts()
1042 if (efx->legacy_irq) in efx_soft_disable_interrupts()
1043 synchronize_irq(efx->legacy_irq); in efx_soft_disable_interrupts()
1046 if (channel->irq) in efx_soft_disable_interrupts()
1047 synchronize_irq(channel->irq); in efx_soft_disable_interrupts()
1050 if (!channel->type->keep_eventq) in efx_soft_disable_interrupts()
1064 BUG_ON(efx->state == STATE_DISABLED); in efx_enable_interrupts()
1066 if (efx->eeh_disabled_legacy_irq) { in efx_enable_interrupts()
1067 enable_irq(efx->legacy_irq); in efx_enable_interrupts()
1068 efx->eeh_disabled_legacy_irq = false; in efx_enable_interrupts()
1071 efx->type->irq_enable_master(efx); in efx_enable_interrupts()
1074 if (channel->type->keep_eventq) { in efx_enable_interrupts()
1092 if (channel->type->keep_eventq) in efx_enable_interrupts()
1096 efx->type->irq_disable_non_ev(efx); in efx_enable_interrupts()
1108 if (channel->type->keep_eventq) in efx_disable_interrupts()
1112 efx->type->irq_disable_non_ev(efx); in efx_disable_interrupts()
1124 atomic_inc(&efx->active_queues); in efx_start_channels()
1129 atomic_inc(&efx->active_queues); in efx_start_channels()
1135 WARN_ON(channel->rx_pkt_n_frags); in efx_start_channels()
1146 /* Stop RX refill */ in efx_stop_channels()
1149 rx_queue->refill_enabled = false; in efx_stop_channels()
1153 /* RX packet processing is pipelined, so wait for the in efx_stop_channels()
1155 * might be kept active by non-data events, so don't in efx_stop_channels()
1165 if (efx->type->fini_dmaq) in efx_stop_channels()
1166 rc = efx->type->fini_dmaq(efx); in efx_stop_channels()
1169 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); in efx_stop_channels()
1171 netif_dbg(efx, drv, efx->net_dev, in efx_stop_channels()
1202 if (unlikely(!channel->enabled)) in efx_process_channel()
1206 EFX_WARN_ON_PARANOID(channel->rx_list != NULL); in efx_process_channel()
1208 channel->rx_list = &rx_list; in efx_process_channel()
1211 tx_queue->pkts_compl = 0; in efx_process_channel()
1212 tx_queue->bytes_compl = 0; in efx_process_channel()
1226 if (tx_queue->bytes_compl) { in efx_process_channel()
1227 netdev_tx_completed_queue(tx_queue->core_txq, in efx_process_channel()
1228 tx_queue->pkts_compl, in efx_process_channel()
1229 tx_queue->bytes_compl); in efx_process_channel()
1234 netif_receive_skb_list(channel->rx_list); in efx_process_channel()
1235 channel->rx_list = NULL; in efx_process_channel()
1242 int step = efx->irq_mod_step_us; in efx_update_irq_mod()
1244 if (channel->irq_mod_score < irq_adapt_low_thresh) { in efx_update_irq_mod()
1245 if (channel->irq_moderation_us > step) { in efx_update_irq_mod()
1246 channel->irq_moderation_us -= step; in efx_update_irq_mod()
1247 efx->type->push_irq_moderation(channel); in efx_update_irq_mod()
1249 } else if (channel->irq_mod_score > irq_adapt_high_thresh) { in efx_update_irq_mod()
1250 if (channel->irq_moderation_us < in efx_update_irq_mod()
1251 efx->irq_rx_moderation_us) { in efx_update_irq_mod()
1252 channel->irq_moderation_us += step; in efx_update_irq_mod()
1253 efx->type->push_irq_moderation(channel); in efx_update_irq_mod()
1257 channel->irq_count = 0; in efx_update_irq_mod()
1258 channel->irq_mod_score = 0; in efx_update_irq_mod()
1270 struct efx_nic *efx = channel->efx; in efx_poll()
1276 netif_vdbg(efx, intr, efx->net_dev, in efx_poll()
1278 channel->channel, raw_smp_processor_id()); in efx_poll()
1286 efx->irq_rx_adaptive && in efx_poll()
1287 unlikely(++channel->irq_count == 1000)) { in efx_poll()
1293 time = jiffies - channel->rfs_last_expiry; in efx_poll()
1295 if (channel->rfs_filter_count * time >= 600 * HZ) in efx_poll()
1296 mod_delayed_work(system_wq, &channel->filter_work, 0); in efx_poll()
1313 struct efx_nic *efx = channel->efx; in efx_init_napi_channel()
1315 channel->napi_dev = efx->net_dev; in efx_init_napi_channel()
1316 netif_napi_add(channel->napi_dev, &channel->napi_str, efx_poll); in efx_init_napi_channel()
1329 if (channel->napi_dev) in efx_fini_napi_channel()
1330 netif_napi_del(&channel->napi_str); in efx_fini_napi_channel()
1332 channel->napi_dev = NULL; in efx_fini_napi_channel()