Lines Matching full:xilinx

5  * Copyright 2019-2022 Xilinx Inc.
33 /* Expected size of a Xilinx continuation address table entry. */
87 			  "Bad BAR value of %d in Xilinx capabilities EF100 entry.\n",  in ef100_pci_parse_ef100_entry()
105 /* Parse a Xilinx capabilities table entry describing a continuation to a new
129 			  "Bad BAR value of %d in Xilinx capabilities sub-table.\n",  in ef100_pci_parse_continue_entry()
139 				  "Xilinx table will overrun BAR[%d] offset=0x%llx\n",  in ef100_pci_parse_continue_entry()
150 				  "Mapping new BAR for Xilinx table failed, rc=%d\n", rc);  in ef100_pci_parse_continue_entry()
176 /* Iterate over the Xilinx capabilities table in the currently mapped BAR and
198 			  "Seen Xilinx table entry 0x%x size 0x%x at 0x%llx in BAR[%d]\n",  in ef100_pci_walk_xilinx_table()
203 				  "Xilinx table entry too short len=0x%x\n", entry_size);  in ef100_pci_walk_xilinx_table()
212 					  "Bad length or rev for EF100 entry in Xilinx capabilities table. entry_size=%d rev=%d.\n",  in ef100_pci_walk_xilinx_table()
225 					  "Bad length or rev for continue entry in Xilinx capabilities table. entry_size=%d rev=%d.\n",  in ef100_pci_walk_xilinx_table()
246 				  "Xilinx table overrun at position=0x%llx.\n",  in ef100_pci_walk_xilinx_table()
278 /* Call ef100_pci_walk_xilinx_table() for the Xilinx capabilities table pointed
302 			  "Bad BAR value of %d in Xilinx capabilities sub-table.\n",  in ef100_pci_parse_xilinx_cap()
331 			  "Xilinx table will overrun BAR[%d] offset=0x%llx\n",  in ef100_pci_parse_xilinx_cap()
353 /* Call ef100_pci_parse_ef100_entry() for each Xilinx PCI_EXT_CAP_ID_VNDR
412 			  "Seen %d Xilinx tables, but no EF100 entry.\n",  in ef100_pci_find_func_ctrl_window()