38 	unsigned int bar;  member
72 	u32 bar = ef100_pci_get_bar_bits(efx, entry_location, EF100_BAR);  in ef100_pci_parse_ef100_entry()  local
75 		  "Found EF100 function control window bar=%d offset=0x%llx\n",  in ef100_pci_parse_ef100_entry()
76 		  bar, offset);  in ef100_pci_parse_ef100_entry()
84 	if (bar == ESE_GZ_CFGBAR_EF100_BAR_NUM_EXPANSION_ROM ||  in ef100_pci_parse_ef100_entry()
85 	    bar == ESE_GZ_CFGBAR_EF100_BAR_NUM_INVALID) {  in ef100_pci_parse_ef100_entry()
87 			  "Bad BAR value of %d in Xilinx capabilities EF100 entry.\n",  in ef100_pci_parse_ef100_entry()
88 			  bar);  in ef100_pci_parse_ef100_entry()
92 	result->bar = bar;  in ef100_pci_parse_ef100_entry()
98 static bool ef100_pci_does_bar_overflow(struct efx_nic *efx, int bar,  in ef100_pci_does_bar_overflow()  argument
102 					pci_resource_len(efx->pci_dev, bar);  in ef100_pci_does_bar_overflow()
115 	u32 bar;  in ef100_pci_parse_continue_entry()  local
119 	bar = EFX_OWORD_FIELD32(entry, ESF_GZ_CFGBAR_CONT_CAP_BAR);  in ef100_pci_parse_continue_entry()
126 	if (bar == ESE_GZ_VSEC_BAR_NUM_EXPANSION_ROM ||  in ef100_pci_parse_continue_entry()
127 	    bar == ESE_GZ_VSEC_BAR_NUM_INVALID) {  in ef100_pci_parse_continue_entry()
129 			  "Bad BAR value of %d in Xilinx capabilities sub-table.\n",  in ef100_pci_parse_continue_entry()
130 			  bar);  in ef100_pci_parse_continue_entry()
134 	if (bar != previous_bar) {  in ef100_pci_parse_continue_entry()
137 		if (ef100_pci_does_bar_overflow(efx, bar, offset)) {  in ef100_pci_parse_continue_entry()
139 				  "Xilinx table will overrun BAR[%d] offset=0x%llx\n",  in ef100_pci_parse_continue_entry()
140 				  bar, offset);  in ef100_pci_parse_continue_entry()
144 		/* Temporarily map new BAR. */  in ef100_pci_parse_continue_entry()
145 		rc = efx_init_io(efx, bar,  in ef100_pci_parse_continue_entry()
147 				 pci_resource_len(efx->pci_dev, bar));  in ef100_pci_parse_continue_entry()
150 				  "Mapping new BAR for Xilinx table failed, rc=%d\n", rc);  in ef100_pci_parse_continue_entry()
159 	if (bar != previous_bar) {  in ef100_pci_parse_continue_entry()
162 		/* Put old BAR back. */  in ef100_pci_parse_continue_entry()
168 				  "Putting old BAR back failed, rc=%d\n", rc);  in ef100_pci_parse_continue_entry()
176 /* Iterate over the Xilinx capabilities table in the currently mapped BAR and
198 			  "Seen Xilinx table entry 0x%x size 0x%x at 0x%llx in BAR[%d]\n",  in ef100_pci_walk_xilinx_table()
288 	u32 bar = 0;  in ef100_pci_parse_xilinx_cap()  local
291 	rc = ef100_pci_get_config_bits(efx, vndr_cap, TBL_BAR, &bar);  in ef100_pci_parse_xilinx_cap()
299 	if (bar == ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_EXPANSION_ROM ||  in ef100_pci_parse_xilinx_cap()
300 	    bar == ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_INVALID) {  in ef100_pci_parse_xilinx_cap()
302 			  "Bad BAR value of %d in Xilinx capabilities sub-table.\n",  in ef100_pci_parse_xilinx_cap()
303 			  bar);  in ef100_pci_parse_xilinx_cap()
329 	if (offset > pci_resource_len(efx->pci_dev, bar) - sizeof(u32) * 2) {  in ef100_pci_parse_xilinx_cap()
331 			  "Xilinx table will overrun BAR[%d] offset=0x%llx\n",  in ef100_pci_parse_xilinx_cap()
332 			  bar, offset);  in ef100_pci_parse_xilinx_cap()
336 	/* Temporarily map BAR. */  in ef100_pci_parse_xilinx_cap()
337 	rc = efx_init_io(efx, bar,  in ef100_pci_parse_xilinx_cap()
339 			 pci_resource_len(efx->pci_dev, bar));  in ef100_pci_parse_xilinx_cap()
348 	/* Unmap temporarily mapped BAR. */  in ef100_pci_parse_xilinx_cap()
486 		fcw.bar = EFX_EF100_PCI_DEFAULT_BAR;  in ef100_pci_probe()
491 	if (fcw.offset > pci_resource_len(efx->pci_dev, fcw.bar) - ESE_GZ_FCW_LEN) {  in ef100_pci_probe()
492 		pci_err(pci_dev, "Func control window overruns BAR\n");  in ef100_pci_probe()
497 	/* Set up basic I/O (BAR mappings etc) */  in ef100_pci_probe()
498 	rc = efx_init_io(efx, fcw.bar,  in ef100_pci_probe()
500 			 pci_resource_len(efx->pci_dev, fcw.bar));  in ef100_pci_probe()