79 #define RTL_W32(tp, reg, val32)	writel((val32), tp->mmio_addr + (reg))  macro
772 	RTL_W32(tp, ERIDR, val);  in _rtl_eri_write()
774 	RTL_W32(tp, ERIAR, cmd);  in _rtl_eri_write()
790 	RTL_W32(tp, ERIAR, cmd);  in _rtl_eri_read()
833 	RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);  in r8168_phy_ocp_write()
843 	RTL_W32(tp, GPHY_OCP, reg << 15);  in r8168_phy_ocp_read()
854 	RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);  in r8168_mac_ocp_write()
862 	RTL_W32(tp, OCPDR, reg << 15);  in r8168_mac_ocp_read()
941 	RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));  in r8169_mdio_write()
955 	RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);  in r8169_mdio_read()
978 	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);  in r8168dp_2_mdio_start()
983 	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);  in r8168dp_2_mdio_stop()
1048 	RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |  in rtl_ephy_write()
1058 	RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);  in rtl_ephy_read()
1066 	RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));  in r8168dp_ocp_read()
1079 	RTL_W32(tp, OCPDR, data);  in r8168dp_ocp_write()
1080 	RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));  in r8168dp_ocp_write()
1232 	RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);  in rtl8168d_efuse_read()
1249 		RTL_W32(tp, IntrStatus_8125, bits);  in rtl_ack_events()
1257 		RTL_W32(tp, IntrMask_8125, 0);  in rtl_irq_disable()
1265 		RTL_W32(tp, IntrMask_8125, tp->irq_mask);  in rtl_irq_enable()
1456 	RTL_W32(tp, RxConfig, rx_config);  in rtl_set_rx_config_features()
1545 	RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));  in rtl8169_do_counters()
1547 	RTL_W32(tp, CounterAddrLow, cmd);  in rtl8169_do_counters()
1548 	RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);  in rtl8169_do_counters()
2187 	RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));  in rtl_rar_set()
2190 	RTL_W32(tp, MAC0, get_unaligned_le32(addr));  in rtl_rar_set()
2216 		RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |  in rtl_wol_enable_rx()
2240 		RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);  in rtl_init_rxcfg()
2245 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);  in rtl_init_rxcfg()
2248 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);  in rtl_init_rxcfg()
2251 		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);  in rtl_init_rxcfg()
2254 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);  in rtl_init_rxcfg()
2402 	RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);  in rtl_rx_close()
2448 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);  in rtl_disable_rxdvgate()
2453 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);  in rtl_enable_rxdvgate()
2466 	RTL_W32(tp, TxConfig, val);  in rtl_set_tx_config_registers()
2482 	RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);  in rtl_set_rx_tx_desc_registers()
2483 	RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));  in rtl_set_rx_tx_desc_registers()
2484 	RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);  in rtl_set_rx_tx_desc_registers()
2485 	RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));  in rtl_set_rx_tx_desc_registers()
2502 	RTL_W32(tp, 0x7c, val);  in rtl8169_set_magic_reg()
2537 	RTL_W32(tp, MAR0 + 4, mc_filter[1]);  in rtl_set_rx_mode()
2538 	RTL_W32(tp, MAR0 + 0, mc_filter[0]);  in rtl_set_rx_mode()
2541 	RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);  in rtl_set_rx_mode()
2553 	RTL_W32(tp, CSIDR, value);  in rtl_csi_write()
2554 	RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |  in rtl_csi_write()
2564 	RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |  in rtl_csi_read()
2862 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);  in rtl_hw_start_8168e_1()
2863 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);  in rtl_hw_start_8168e_1()
2897 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);  in rtl_hw_start_8168e_2()
2920 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);  in rtl_hw_start_8168f()
3432 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8105e_1()
3435 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);  in rtl_hw_start_8105e_1()
3461 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8402()
3484 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8106()
3486 	RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);  in rtl_hw_start_8106()
3670 		RTL_W32(tp, i, 0);  in rtl_hw_start_8125()