Lines Matching refs:RTL_R8
80 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) macro
674 RTL_R8(tp, ChipCmd); in rtl_pci_commit()
701 mac[i] = RTL_R8(tp, reg + i); in rtl_read_mac_from_reg()
1123 return RTL_R8(tp, IBISR0) & 0x20; in DECLARE_RTL_COND()
1128 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); in rtl8168ep_stop_cmac()
1130 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); in rtl8168ep_stop_cmac()
1131 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); in rtl8168ep_stop_cmac()
1210 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); in rtl_set_d3_pll_down()
1212 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); in rtl_set_d3_pll_down()
1357 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; in __rtl8169_set_wol()
1365 options = RTL_R8(tp, Config1) & ~PMEnable; in __rtl8169_set_wol()
1373 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; in __rtl8169_set_wol()
1555 u8 val = RTL_R8(tp, ChipCmd); in rtl8169_update_counters()
2106 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); in rtl8168_config_eee_mac()
2266 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); in r8168c_hw_jumbo_enable()
2267 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); in r8168c_hw_jumbo_enable()
2272 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); in r8168c_hw_jumbo_disable()
2273 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); in r8168c_hw_jumbo_disable()
2278 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); in r8168dp_hw_jumbo_enable()
2283 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); in r8168dp_hw_jumbo_disable()
2289 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); in r8168e_hw_jumbo_enable()
2290 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); in r8168e_hw_jumbo_enable()
2296 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); in r8168e_hw_jumbo_disable()
2297 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); in r8168e_hw_jumbo_disable()
2302 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); in r8168b_1_hw_jumbo_enable()
2307 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); in r8168b_1_hw_jumbo_disable()
2365 return RTL_R8(tp, ChipCmd) & CmdReset; in DECLARE_RTL_COND()
2407 return RTL_R8(tp, TxPoll) & NPQ; in DECLARE_RTL_COND()
2417 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; in DECLARE_RTL_COND()
2437 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); in rtl_wait_txrx_fifo_empty()
2499 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) in rtl8169_set_magic_reg()
2633 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); in rtl_pcie_state_l2l3_disable()
2679 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); in rtl_hw_aspm_clkreq_enable()
2680 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); in rtl_hw_aspm_clkreq_enable()
2703 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); in rtl_hw_aspm_clkreq_enable()
2704 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); in rtl_hw_aspm_clkreq_enable()
2730 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8168b()
2735 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); in __rtl_hw_start_8168cp()
2737 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in __rtl_hw_start_8168cp()
2763 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8168cp_2()
2770 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8168cp_3()
2865 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); in rtl_hw_start_8168e_1()
2892 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_start_8168e_2()
2896 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); in rtl_hw_start_8168e_2()
2898 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); in rtl_hw_start_8168e_2()
2918 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_start_8168f()
2919 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); in rtl_hw_start_8168f()
2921 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); in rtl_hw_start_8168f()
3213 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); in rtl_hw_start_8168h_1()
3214 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); in rtl_hw_start_8168h_1()
3216 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); in rtl_hw_start_8168h_1()
3266 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); in rtl_hw_start_8168ep()
3286 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); in rtl_hw_start_8168ep_3()
3287 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); in rtl_hw_start_8168ep_3()
3328 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); in rtl_hw_start_8117()
3329 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); in rtl_hw_start_8117()
3331 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); in rtl_hw_start_8117()
3381 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8102e_1()
3383 cfg1 = RTL_R8(tp, Config1); in rtl_hw_start_8102e_1()
3395 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8102e_2()
3415 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8401()
3437 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); in rtl_hw_start_8105e_1()
3438 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); in rtl_hw_start_8105e_1()
3463 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_start_8402()
3487 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); in rtl_hw_start_8106()
3488 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); in rtl_hw_start_8106()
3518 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); in rtl_hw_start_8125_common()
3896 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); in rtl8169_cleanup()
3904 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); in rtl8169_cleanup()
4922 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); in rtl_alloc_irq()
4954 return RTL_R8(tp, MCU) & LINK_LIST_RDY; in DECLARE_RTL_COND()
5035 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); in rtl_hw_init_8168g()
5037 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_init_8168g()
5050 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); in rtl_hw_init_8125()
5052 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_init_8125()