Lines Matching +full:0 +full:x0020
14 #define OPCODE_OB_MAC_IOCB_FN0 0x01
15 #define OPCODE_OB_MAC_IOCB_FN2 0x21
17 #define OPCODE_IB_MAC_IOCB 0xF9
18 #define OPCODE_IB_3032_MAC_IOCB 0x09
19 #define OPCODE_IB_IP_IOCB 0xFA
20 #define OPCODE_IB_3032_IP_IOCB 0x0A
22 #define OPCODE_FUNC_ID_MASK 0x30
23 #define OUTBOUND_MAC_IOCB 0x01 /* plus function bits */
25 #define FN0_MA_BITS_MASK 0x00
26 #define FN1_MA_BITS_MASK 0x80
31 #define OB_MAC_IOCB_REQ_MA 0xe0
32 #define OB_MAC_IOCB_REQ_F 0x10
33 #define OB_MAC_IOCB_REQ_X 0x08
34 #define OB_MAC_IOCB_REQ_D 0x02
35 #define OB_MAC_IOCB_REQ_I 0x01
37 #define OB_3032MAC_IOCB_REQ_IC 0x04
38 #define OB_3032MAC_IOCB_REQ_TC 0x02
39 #define OB_3032MAC_IOCB_REQ_UC 0x01
64 #define OB_MAC_IOCB_REQ_E 0x80000000 /* Last valid buffer in list. */
65 #define OB_MAC_IOCB_REQ_C 0x40000000 /* points to an OAL. (continuation) */
66 #define OB_MAC_IOCB_REQ_L 0x20000000 /* Auburn local address pointer. */
67 #define OB_MAC_IOCB_REQ_R 0x10000000 /* 32-bit address pointer. */
72 #define OB_MAC_IOCB_RSP_P 0x08
73 #define OB_MAC_IOCB_RSP_L 0x04
74 #define OB_MAC_IOCB_RSP_S 0x02
75 #define OB_MAC_IOCB_RSP_I 0x01
85 #define IB_MAC_IOCB_RSP_V 0x80
87 #define IB_MAC_IOCB_RSP_S 0x80
88 #define IB_MAC_IOCB_RSP_H1 0x40
89 #define IB_MAC_IOCB_RSP_H0 0x20
90 #define IB_MAC_IOCB_RSP_B 0x10
91 #define IB_MAC_IOCB_RSP_M 0x08
92 #define IB_MAC_IOCB_RSP_MA 0x07
104 #define OB_IP_IOCB_REQ_O 0x100
105 #define OB_IP_IOCB_REQ_H 0x008
106 #define OB_IP_IOCB_REQ_U 0x004
107 #define OB_IP_IOCB_REQ_D 0x002
108 #define OB_IP_IOCB_REQ_I 0x001
131 #define OB_IP_IOCB_REQ_E 0x80000000
132 #define OB_IP_IOCB_REQ_C 0x40000000
133 #define OB_IP_IOCB_REQ_L 0x20000000
134 #define OB_IP_IOCB_REQ_R 0x10000000
139 #define OB_MAC_IOCB_RSP_H 0x10
140 #define OB_MAC_IOCB_RSP_E 0x08
141 #define OB_MAC_IOCB_RSP_L 0x04
142 #define OB_MAC_IOCB_RSP_S 0x02
143 #define OB_MAC_IOCB_RSP_I 0x01
153 #define IB_IP_IOCB_RSP_3032_V 0x80
154 #define IB_IP_IOCB_RSP_3032_O 0x40
155 #define IB_IP_IOCB_RSP_3032_I 0x20
156 #define IB_IP_IOCB_RSP_3032_R 0x10
158 #define IB_IP_IOCB_RSP_S 0x80
159 #define IB_IP_IOCB_RSP_H1 0x40
160 #define IB_IP_IOCB_RSP_H0 0x20
161 #define IB_IP_IOCB_RSP_B 0x10
162 #define IB_IP_IOCB_RSP_M 0x08
163 #define IB_IP_IOCB_RSP_MA 0x07
167 #define IB_IP_IOCB_RSP_3032_ICE 0x01
168 #define IB_IP_IOCB_RSP_3032_CE 0x02
169 #define IB_IP_IOCB_RSP_3032_NUC 0x04
170 #define IB_IP_IOCB_RSP_3032_UDP 0x08
171 #define IB_IP_IOCB_RSP_3032_TCP 0x10
172 #define IB_IP_IOCB_RSP_3032_IPE 0x20
174 #define IB_IP_IOCB_RSP_R 0x01
190 #define PORT0_PHY_ADDRESS 0x1e00
191 #define PORT1_PHY_ADDRESS 0x1f00
195 #define MII_SCAN_REGISTER 0x00000001
200 #define PHY_OUI_1_MASK 0xfc00
201 #define PHY_MODEL_MASK 0x03f0
204 #define MII_AGERE_ADDR_1 0x00001000
205 #define MII_AGERE_ADDR_2 0x00001100
209 ISP_CONTROL_NP_MASK = 0x0003,
210 ISP_CONTROL_NP_PCSR = 0x0000,
211 ISP_CONTROL_NP_HMCR = 0x0001,
212 ISP_CONTROL_NP_LRAMCR = 0x0002,
213 ISP_CONTROL_NP_PSR = 0x0003,
214 ISP_CONTROL_RI = 0x0008,
215 ISP_CONTROL_CI = 0x0010,
216 ISP_CONTROL_PI = 0x0020,
217 ISP_CONTROL_IN = 0x0040,
218 ISP_CONTROL_BE = 0x0080,
219 ISP_CONTROL_FN_MASK = 0x0700,
220 ISP_CONTROL_FN0_NET = 0x0400,
221 ISP_CONTROL_FN0_SCSI = 0x0500,
222 ISP_CONTROL_FN1_NET = 0x0600,
223 ISP_CONTROL_FN1_SCSI = 0x0700,
224 ISP_CONTROL_LINK_DN_0 = 0x0800,
225 ISP_CONTROL_LINK_DN_1 = 0x1000,
226 ISP_CONTROL_FSR = 0x2000,
227 ISP_CONTROL_FE = 0x4000,
228 ISP_CONTROL_SR = 0x8000,
233 ISP_IMR_ENABLE_INT = 0x0004,
234 ISP_IMR_DISABLE_RESET_INT = 0x0008,
235 ISP_IMR_DISABLE_CMPL_INT = 0x0010,
236 ISP_IMR_DISABLE_PROC_INT = 0x0020,
241 ISP_SERIAL_PORT_IF_CLK = 0x0001,
242 ISP_SERIAL_PORT_IF_CS = 0x0002,
243 ISP_SERIAL_PORT_IF_D0 = 0x0004,
244 ISP_SERIAL_PORT_IF_DI = 0x0008,
245 ISP_NVRAM_MASK = (0x000F << 16),
246 ISP_SERIAL_PORT_IF_WE = 0x0010,
247 ISP_SERIAL_PORT_IF_NVR_MASK = 0x001F,
248 ISP_SERIAL_PORT_IF_SCI = 0x0400,
249 ISP_SERIAL_PORT_IF_SC0 = 0x0800,
250 ISP_SERIAL_PORT_IF_SCE = 0x1000,
251 ISP_SERIAL_PORT_IF_SDI = 0x2000,
252 ISP_SERIAL_PORT_IF_SDO = 0x4000,
253 ISP_SERIAL_PORT_IF_SDE = 0x8000,
254 ISP_SERIAL_PORT_IF_I2C_MASK = 0xFC00,
259 QL_RESOURCE_MASK_BASE_CODE = 0x7,
260 QL_RESOURCE_BITS_BASE_CODE = 0x4,
280 u32 MB0; /* Offset 0x00 */
281 u32 MB1; /* Offset 0x04 */
282 u32 MB2; /* Offset 0x08 */
283 u32 MB3; /* Offset 0x0c */
284 u32 MB4; /* Offset 0x10 */
285 u32 MB5; /* Offset 0x14 */
286 u32 MB6; /* Offset 0x18 */
287 u32 MB7; /* Offset 0x1c */
304 EXT_HW_CONFIG_SP_MASK = 0x0006,
305 EXT_HW_CONFIG_SP_NONE = 0x0000,
306 EXT_HW_CONFIG_SP_BYTE_PARITY = 0x0002,
307 EXT_HW_CONFIG_SP_ECC = 0x0004,
308 EXT_HW_CONFIG_SP_ECCx = 0x0006,
309 EXT_HW_CONFIG_SIZE_MASK = 0x0060,
310 EXT_HW_CONFIG_SIZE_128M = 0x0000,
311 EXT_HW_CONFIG_SIZE_256M = 0x0020,
312 EXT_HW_CONFIG_SIZE_512M = 0x0040,
313 EXT_HW_CONFIG_SIZE_INVALID = 0x0060,
314 EXT_HW_CONFIG_PD = 0x0080,
315 EXT_HW_CONFIG_FW = 0x0200,
316 EXT_HW_CONFIG_US = 0x0400,
317 EXT_HW_CONFIG_DCS_MASK = 0x1800,
318 EXT_HW_CONFIG_DCS_9MA = 0x0000,
319 EXT_HW_CONFIG_DCS_15MA = 0x0800,
320 EXT_HW_CONFIG_DCS_18MA = 0x1000,
321 EXT_HW_CONFIG_DCS_24MA = 0x1800,
322 EXT_HW_CONFIG_DDS_MASK = 0x6000,
323 EXT_HW_CONFIG_DDS_9MA = 0x0000,
324 EXT_HW_CONFIG_DDS_15MA = 0x2000,
325 EXT_HW_CONFIG_DDS_18MA = 0x4000,
326 EXT_HW_CONFIG_DDS_24MA = 0x6000,
331 INTERNAL_CHIP_DM = 0x0001,
332 INTERNAL_CHIP_SD = 0x0002,
333 INTERNAL_CHIP_RAP_MASK = 0x000C,
334 INTERNAL_CHIP_RAP_RR = 0x0000,
335 INTERNAL_CHIP_RAP_NRM = 0x0004,
336 INTERNAL_CHIP_RAP_ERM = 0x0008,
337 INTERNAL_CHIP_RAP_ERMx = 0x000C,
338 INTERNAL_CHIP_WE = 0x0010,
339 INTERNAL_CHIP_EF = 0x0020,
340 INTERNAL_CHIP_FR = 0x0040,
341 INTERNAL_CHIP_FW = 0x0080,
342 INTERNAL_CHIP_FI = 0x0100,
343 INTERNAL_CHIP_FT = 0x0200,
348 PORT_CONTROL_DS = 0x0001,
349 PORT_CONTROL_HH = 0x0002,
350 PORT_CONTROL_EI = 0x0004,
351 PORT_CONTROL_ET = 0x0008,
352 PORT_CONTROL_EF = 0x0010,
353 PORT_CONTROL_DRM = 0x0020,
354 PORT_CONTROL_RLB = 0x0040,
355 PORT_CONTROL_RCB = 0x0080,
356 PORT_CONTROL_MAC = 0x0100,
357 PORT_CONTROL_IPV = 0x0200,
358 PORT_CONTROL_IFP = 0x0400,
359 PORT_CONTROL_ITP = 0x0800,
360 PORT_CONTROL_FI = 0x1000,
361 PORT_CONTROL_DFP = 0x2000,
362 PORT_CONTROL_OI = 0x4000,
363 PORT_CONTROL_CC = 0x8000,
368 PORT_STATUS_SM0 = 0x0001,
369 PORT_STATUS_SM1 = 0x0002,
370 PORT_STATUS_X = 0x0008,
371 PORT_STATUS_DL = 0x0080,
372 PORT_STATUS_IC = 0x0200,
373 PORT_STATUS_MRC = 0x0400,
374 PORT_STATUS_NL = 0x0800,
375 PORT_STATUS_REV_ID_MASK = 0x7000,
376 PORT_STATUS_REV_ID_1 = 0x1000,
377 PORT_STATUS_REV_ID_2 = 0x2000,
378 PORT_STATUS_REV_ID_3 = 0x3000,
379 PORT_STATUS_64 = 0x8000,
380 PORT_STATUS_UP0 = 0x10000,
381 PORT_STATUS_AC0 = 0x20000,
382 PORT_STATUS_AE0 = 0x40000,
383 PORT_STATUS_UP1 = 0x100000,
384 PORT_STATUS_AC1 = 0x200000,
385 PORT_STATUS_AE1 = 0x400000,
386 PORT_STATUS_F0_ENABLED = 0x1000000,
387 PORT_STATUS_F1_ENABLED = 0x2000000,
388 PORT_STATUS_F2_ENABLED = 0x4000000,
389 PORT_STATUS_F3_ENABLED = 0x8000000,
394 MAC_ADDR_INDIRECT_PTR_REG_RP_MASK = 0x0003,
395 MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR = 0x0000,
396 MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR = 0x0001,
397 MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR = 0x0002,
398 MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR = 0x0003,
399 MAC_ADDR_INDIRECT_PTR_REG_PR = 0x0008,
400 MAC_ADDR_INDIRECT_PTR_REG_SS = 0x0010,
401 MAC_ADDR_INDIRECT_PTR_REG_SE = 0x0020,
402 MAC_ADDR_INDIRECT_PTR_REG_SP = 0x0040,
403 MAC_ADDR_INDIRECT_PTR_REG_PE = 0x0080,
408 MAC_MII_CONTROL_RC = 0x0001,
409 MAC_MII_CONTROL_SC = 0x0002,
410 MAC_MII_CONTROL_AS = 0x0004,
411 MAC_MII_CONTROL_NP = 0x0008,
412 MAC_MII_CONTROL_CLK_SEL_MASK = 0x0070,
413 MAC_MII_CONTROL_CLK_SEL_DIV2 = 0x0000,
414 MAC_MII_CONTROL_CLK_SEL_DIV4 = 0x0010,
415 MAC_MII_CONTROL_CLK_SEL_DIV6 = 0x0020,
416 MAC_MII_CONTROL_CLK_SEL_DIV8 = 0x0030,
417 MAC_MII_CONTROL_CLK_SEL_DIV10 = 0x0040,
418 MAC_MII_CONTROL_CLK_SEL_DIV14 = 0x0050,
419 MAC_MII_CONTROL_CLK_SEL_DIV20 = 0x0060,
420 MAC_MII_CONTROL_CLK_SEL_DIV28 = 0x0070,
421 MAC_MII_CONTROL_RM = 0x8000,
426 MAC_MII_STATUS_BSY = 0x0001,
427 MAC_MII_STATUS_SC = 0x0002,
428 MAC_MII_STATUS_NV = 0x0004,
432 MAC_CONFIG_REG_PE = 0x0001,
433 MAC_CONFIG_REG_TF = 0x0002,
434 MAC_CONFIG_REG_RF = 0x0004,
435 MAC_CONFIG_REG_FD = 0x0008,
436 MAC_CONFIG_REG_GM = 0x0010,
437 MAC_CONFIG_REG_LB = 0x0020,
438 MAC_CONFIG_REG_SR = 0x8000,
442 MAC_HALF_DUPLEX_REG_ED = 0x10000,
443 MAC_HALF_DUPLEX_REG_NB = 0x20000,
444 MAC_HALF_DUPLEX_REG_BNB = 0x40000,
445 MAC_HALF_DUPLEX_REG_ALT = 0x80000,
449 IP_ADDR_INDEX_REG_MASK = 0x000f,
450 IP_ADDR_INDEX_REG_FUNC_0_PRI = 0x0000,
451 IP_ADDR_INDEX_REG_FUNC_0_SEC = 0x0001,
452 IP_ADDR_INDEX_REG_FUNC_1_PRI = 0x0002,
453 IP_ADDR_INDEX_REG_FUNC_1_SEC = 0x0003,
454 IP_ADDR_INDEX_REG_FUNC_2_PRI = 0x0004,
455 IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,
456 IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
457 IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,
458 IP_ADDR_INDEX_REG_6 = 0x0008,
459 IP_ADDR_INDEX_REG_OFFSET_MASK = 0x0030,
460 IP_ADDR_INDEX_REG_E = 0x0040,
463 QL3032_PORT_CONTROL_DS = 0x0001,
464 QL3032_PORT_CONTROL_HH = 0x0002,
465 QL3032_PORT_CONTROL_EIv6 = 0x0004,
466 QL3032_PORT_CONTROL_EIv4 = 0x0008,
467 QL3032_PORT_CONTROL_ET = 0x0010,
468 QL3032_PORT_CONTROL_EF = 0x0020,
469 QL3032_PORT_CONTROL_DRM = 0x0040,
470 QL3032_PORT_CONTROL_RLB = 0x0080,
471 QL3032_PORT_CONTROL_RCB = 0x0100,
472 QL3032_PORT_CONTROL_KIE = 0x0200,
476 PROBE_MUX_ADDR_REG_MUX_SEL_MASK = 0x003f,
477 PROBE_MUX_ADDR_REG_SYSCLK = 0x0000,
478 PROBE_MUX_ADDR_REG_PCICLK = 0x0040,
479 PROBE_MUX_ADDR_REG_NRXCLK = 0x0080,
480 PROBE_MUX_ADDR_REG_CPUCLK = 0x00C0,
481 PROBE_MUX_ADDR_REG_MODULE_SEL_MASK = 0x3f00,
482 PROBE_MUX_ADDR_REG_UP = 0x4000,
483 PROBE_MUX_ADDR_REG_RE = 0x8000,
487 STATISTICS_INDEX_REG_MASK = 0x01ff,
488 STATISTICS_INDEX_REG_MAC0_TX_FRAME = 0x0000,
489 STATISTICS_INDEX_REG_MAC0_TX_BYTES = 0x0001,
490 STATISTICS_INDEX_REG_MAC0_TX_STAT1 = 0x0002,
491 STATISTICS_INDEX_REG_MAC0_TX_STAT2 = 0x0003,
492 STATISTICS_INDEX_REG_MAC0_TX_STAT3 = 0x0004,
493 STATISTICS_INDEX_REG_MAC0_TX_STAT4 = 0x0005,
494 STATISTICS_INDEX_REG_MAC0_TX_STAT5 = 0x0006,
495 STATISTICS_INDEX_REG_MAC0_RX_FRAME = 0x0007,
496 STATISTICS_INDEX_REG_MAC0_RX_BYTES = 0x0008,
497 STATISTICS_INDEX_REG_MAC0_RX_STAT1 = 0x0009,
498 STATISTICS_INDEX_REG_MAC0_RX_STAT2 = 0x000a,
499 STATISTICS_INDEX_REG_MAC0_RX_STAT3 = 0x000b,
500 STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC = 0x000c,
501 STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC = 0x000d,
502 STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN = 0x000e,
503 STATISTICS_INDEX_REG_MAC0_RX_STAT4 = 0x000f,
504 STATISTICS_INDEX_REG_MAC1_TX_FRAME = 0x0010,
505 STATISTICS_INDEX_REG_MAC1_TX_BYTES = 0x0011,
506 STATISTICS_INDEX_REG_MAC1_TX_STAT1 = 0x0012,
507 STATISTICS_INDEX_REG_MAC1_TX_STAT2 = 0x0013,
508 STATISTICS_INDEX_REG_MAC1_TX_STAT3 = 0x0014,
509 STATISTICS_INDEX_REG_MAC1_TX_STAT4 = 0x0015,
510 STATISTICS_INDEX_REG_MAC1_TX_STAT5 = 0x0016,
511 STATISTICS_INDEX_REG_MAC1_RX_FRAME = 0x0017,
512 STATISTICS_INDEX_REG_MAC1_RX_BYTES = 0x0018,
513 STATISTICS_INDEX_REG_MAC1_RX_STAT1 = 0x0019,
514 STATISTICS_INDEX_REG_MAC1_RX_STAT2 = 0x001a,
515 STATISTICS_INDEX_REG_MAC1_RX_STAT3 = 0x001b,
516 STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC = 0x001c,
517 STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC = 0x001d,
518 STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN = 0x001e,
519 STATISTICS_INDEX_REG_MAC1_RX_STAT4 = 0x001f,
520 STATISTICS_INDEX_REG_IP_TX_PKTS = 0x0020,
521 STATISTICS_INDEX_REG_IP_TX_BYTES = 0x0021,
522 STATISTICS_INDEX_REG_IP_TX_FRAG = 0x0022,
523 STATISTICS_INDEX_REG_IP_RX_PKTS = 0x0023,
524 STATISTICS_INDEX_REG_IP_RX_BYTES = 0x0024,
525 STATISTICS_INDEX_REG_IP_RX_FRAG = 0x0025,
526 STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY = 0x0026,
527 STATISTICS_INDEX_REG_IP_V6_RX_PKTS = 0x0027,
528 STATISTICS_INDEX_REG_IP_RX_PKTERR = 0x0028,
529 STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR = 0x0029,
530 STATISTICS_INDEX_REG_TCP_TX_SEG = 0x0030,
531 STATISTICS_INDEX_REG_TCP_TX_BYTES = 0x0031,
532 STATISTICS_INDEX_REG_TCP_RX_SEG = 0x0032,
533 STATISTICS_INDEX_REG_TCP_RX_BYTES = 0x0033,
534 STATISTICS_INDEX_REG_TCP_TIMER_EXP = 0x0034,
535 STATISTICS_INDEX_REG_TCP_RX_ACK = 0x0035,
536 STATISTICS_INDEX_REG_TCP_TX_ACK = 0x0036,
537 STATISTICS_INDEX_REG_TCP_RX_ERR = 0x0037,
538 STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE = 0x0038,
539 STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR = 0x003f,
543 PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 = 0x00000001,
544 PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 = 0x00000002,
545 PORT_FATAL_ERROR_STATUS_OFB_WE = 0x00000004,
546 PORT_FATAL_ERROR_STATUS_IFB_RE = 0x00000008,
547 PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 = 0x00000010,
548 PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 = 0x00000020,
549 PORT_FATAL_ERROR_STATUS_ODE_RE = 0x00000040,
550 PORT_FATAL_ERROR_STATUS_ODE_WE = 0x00000080,
551 PORT_FATAL_ERROR_STATUS_IDE_RE = 0x00000100,
552 PORT_FATAL_ERROR_STATUS_IDE_WE = 0x00000200,
553 PORT_FATAL_ERROR_STATUS_SDE_RE = 0x00000400,
554 PORT_FATAL_ERROR_STATUS_SDE_WE = 0x00000800,
555 PORT_FATAL_ERROR_STATUS_BLE = 0x00001000,
556 PORT_FATAL_ERROR_STATUS_SPE = 0x00002000,
557 PORT_FATAL_ERROR_STATUS_EP0 = 0x00004000,
558 PORT_FATAL_ERROR_STATUS_EP1 = 0x00008000,
559 PORT_FATAL_ERROR_STATUS_ICE = 0x00010000,
560 PORT_FATAL_ERROR_STATUS_ILE = 0x00020000,
561 PORT_FATAL_ERROR_STATUS_OPE = 0x00040000,
562 PORT_FATAL_ERROR_STATUS_TA = 0x00080000,
563 PORT_FATAL_ERROR_STATUS_MA = 0x00100000,
564 PORT_FATAL_ERROR_STATUS_SCE = 0x00200000,
565 PORT_FATAL_ERROR_STATUS_RPE = 0x00400000,
566 PORT_FATAL_ERROR_STATUS_MPE = 0x00800000,
567 PORT_FATAL_ERROR_STATUS_OCE = 0x01000000,
571 * port control and status page - page 0
689 #define LS_64BITS(x) (u32)(0xffffffff & ((u64)x))
690 #define MS_64BITS(x) (u32)(0xffffffff & (((u64)x)>>16>>16) )
697 CONTROL_REG = 0,
699 PHY_STAT_LINK_UP = 0x0004,
700 PHY_CTRL_LOOPBACK = 0x4000,
702 PETBI_CONTROL_REG = 0x00,
703 PETBI_CTRL_ALL_PARAMS = 0x7140,
704 PETBI_CTRL_SOFT_RESET = 0x8000,
705 PETBI_CTRL_AUTO_NEG = 0x1000,
706 PETBI_CTRL_RESTART_NEG = 0x0200,
707 PETBI_CTRL_FULL_DUPLEX = 0x0100,
708 PETBI_CTRL_SPEED_1000 = 0x0040,
710 PETBI_STATUS_REG = 0x01,
711 PETBI_STAT_NEG_DONE = 0x0020,
712 PETBI_STAT_LINK_UP = 0x0004,
714 PETBI_NEG_ADVER = 0x04,
715 PETBI_NEG_PAUSE = 0x0080,
716 PETBI_NEG_PAUSE_MASK = 0x0180,
717 PETBI_NEG_DUPLEX = 0x0020,
718 PETBI_NEG_DUPLEX_MASK = 0x0060,
720 PETBI_NEG_PARTNER = 0x05,
721 PETBI_NEG_ERROR_MASK = 0x3000,
723 PETBI_EXPANSION_REG = 0x06,
724 PETBI_EXP_PAGE_RX = 0x0002,
727 PHY_GIG_ENABLE_MAN = 0x1000, /* Enable Master/Slave Manual Config*/
728 PHY_GIG_SET_MASTER = 0x0800, /* Set Master (slave if clear)*/
729 PHY_GIG_ALL_PARAMS = 0x0300,
730 PHY_GIG_ADV_1000F = 0x0200,
731 PHY_GIG_ADV_1000H = 0x0100,
734 PHY_NEG_ALL_PARAMS = 0x0fe0,
735 PHY_NEG_ASY_PAUSE = 0x0800,
736 PHY_NEG_SYM_PAUSE = 0x0400,
737 PHY_NEG_ADV_SPEED = 0x01e0,
738 PHY_NEG_ADV_100F = 0x0100,
739 PHY_NEG_ADV_100H = 0x0080,
740 PHY_NEG_ADV_10F = 0x0040,
741 PHY_NEG_ADV_10H = 0x0020,
743 PETBI_TBI_CTRL = 0x11,
744 PETBI_TBI_RESET = 0x8000,
745 PETBI_TBI_AUTO_SENSE = 0x0100,
746 PETBI_TBI_SERDES_MODE = 0x0010,
747 PETBI_TBI_SERDES_WRAP = 0x0002,
749 AUX_CONTROL_STATUS = 0x1c,
750 PHY_AUX_NEG_DONE = 0x8000,
752 PHY_AUX_DUPLEX_STAT = 0x0020,
753 PHY_AUX_SPEED_STAT = 0x0018,
754 PHY_AUX_NO_HW_STRAP = 0x0004,
755 PHY_AUX_RESET_STICK = 0x0002,
756 PHY_NEG_PAUSE = 0x0400,
757 PHY_CTRL_SOFT_RESET = 0x8000,
758 PHY_CTRL_AUTO_NEG = 0x1000,
759 PHY_CTRL_RESTART_NEG = 0x0200,
763 FM93C56A_START = 0x1,
765 FM93C56A_READ = 0x2,
766 FM93C56A_WEN = 0x0,
767 FM93C56A_WRITE = 0x1,
768 FM93C56A_WRITE_ALL = 0x0,
769 FM93C56A_WDS = 0x0,
770 FM93C56A_ERASE = 0x3,
771 FM93C56A_ERASE_ALL = 0x0,
773 FM93C56A_WEN_EXT = 0x3,
774 FM93C56A_WRITE_ALL_EXT = 0x1,
775 FM93C56A_WDS_EXT = 0x0,
776 FM93C56A_ERASE_ALL_EXT = 0x2,
779 FM93C56A_READY = 0,
783 FM93C56A_SIZE_8 = 0x100,
784 FM93C56A_SIZE_16 = 0x80,
785 FM93C66A_SIZE_8 = 0x200,
786 FM93C66A_SIZE_16 = 0x100,
787 FM93C86A_SIZE_16 = 0x400,
798 AUBURN_EEPROM_DI = 0x8,
799 AUBURN_EEPROM_DI_0 = 0x0,
800 AUBURN_EEPROM_DI_1 = 0x8,
801 AUBURN_EEPROM_DO = 0x4,
802 AUBURN_EEPROM_DO_0 = 0x0,
803 AUBURN_EEPROM_DO_1 = 0x4,
804 AUBURN_EEPROM_CS = 0x2,
805 AUBURN_EEPROM_CS_0 = 0x0,
806 AUBURN_EEPROM_CS_1 = 0x2,
807 AUBURN_EEPROM_CLK_RISE = 0x1,
808 AUBURN_EEPROM_CLK_FALL = 0x0,
823 #define PORT_CONFIG_DEFAULT 0xf700
824 #define PORT_CONFIG_AUTO_NEG_ENABLED 0x8000
825 #define PORT_CONFIG_SYM_PAUSE_ENABLED 0x4000
826 #define PORT_CONFIG_FULL_DUPLEX_ENABLED 0x2000
827 #define PORT_CONFIG_HALF_DUPLEX_ENABLED 0x1000
828 #define PORT_CONFIG_1000MB_SPEED 0x0400
829 #define PORT_CONFIG_100MB_SPEED 0x0200
830 #define PORT_CONFIG_10MB_SPEED 0x0100
831 #define PORT_CONFIG_LINK_SPEED_MASK 0x0F00
901 #define IPSEC_CONFIG_PRESENT 0x0001
928 #define QL3XXX_VENDOR_ID 0x1077
929 #define QL3022_DEVICE_ID 0x3022
930 #define QL3032_DEVICE_ID 0x3032
960 #define IAL_LAST_ENTRY 0x00000001
961 #define IAL_CONT_ENTRY 0x00000002
962 #define IAL_FLAG_MASK 0x00000003
986 #define QL_NO_RESET 0
990 LS_UNKNOWN = 0,
1022 #define OAL_LAST_ENTRY 0x80000000 /* Last valid buffer in list. */
1023 #define OAL_CONT_ENTRY 0x40000000 /* points to an OAL. (continuation) */
1044 #define QL_BUF_TYPE_MACIOCB 0x01
1045 #define QL_BUF_TYPE_IPIOCB 0x02
1046 #define QL_BUF_TYPE_TCPIOCB 0x03
1174 …u32 mac_index; /* Driver's MAC number can be 0 or 1 for first and second networking functions res…
1175 u32 PHYAddr; /* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */