Lines Matching +full:0 +full:x1
89 LL2_OK = 0,
147 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
148 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0
149 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */
188 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
189 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
190 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
192 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
277 CORE_RX_PKT_SOURCE_NETWORK = 0,
322 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
323 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
324 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
326 #define CORE_TX_BD_DATA_START_BD_MASK 0x1
328 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
330 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
332 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
334 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
336 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
338 #define CORE_TX_BD_DATA_NBDS_MASK 0xF
340 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
342 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
344 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1
346 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x1
357 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
358 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
359 #define CORE_TX_BD_TX_DST_MASK 0x3
435 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
436 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
437 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
439 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
441 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
443 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
445 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
447 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
449 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
452 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
453 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
454 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
456 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
458 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
460 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
462 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
464 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
466 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
469 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
470 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
471 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
473 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
475 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
478 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
479 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
480 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
482 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
484 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
487 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
488 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
489 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
491 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
493 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
496 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
497 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
498 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
500 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
502 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
505 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
506 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
507 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
509 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
511 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
514 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
515 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
516 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
518 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
520 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
522 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
525 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
526 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
527 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
529 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
531 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
533 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
535 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
537 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
539 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
542 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
543 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
544 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
546 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
548 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
550 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
552 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
554 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
556 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
559 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
560 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
561 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
563 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
565 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
567 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
569 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
571 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
573 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
576 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
577 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
578 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
580 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
582 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
584 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
586 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
588 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
590 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
593 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
594 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
595 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
597 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
599 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
601 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
603 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
605 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
607 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
610 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
611 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
612 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
614 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
616 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
618 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
620 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
622 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
624 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
627 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
628 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
629 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
631 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
633 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
635 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
637 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
639 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
698 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
699 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
700 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
702 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
704 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
706 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
708 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
710 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
713 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
714 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
715 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
717 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
719 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
722 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
723 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
724 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
726 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
728 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
731 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
732 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
733 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
735 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
737 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
739 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
741 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
744 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
745 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
746 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
748 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
750 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
752 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
754 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
756 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
758 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
761 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
762 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
763 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
765 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
767 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
769 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
771 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
773 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
775 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
802 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
803 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
804 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
806 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
808 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
810 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
813 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
814 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
815 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
817 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
819 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
822 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
823 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
824 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
826 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
828 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
830 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
832 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
834 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
836 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
839 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
840 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
841 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
843 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
845 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
847 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
849 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
851 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
853 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
1038 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1
1039 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0
1040 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
1302 COMMON_ERR_CODE_OK = 0,
1309 ETH_VER_KEY = 0,
1409 TUNNEL_CLSS_MAC_VLAN = 0,
1492 #define DMAE_CMD_SRC_MASK 0x1
1493 #define DMAE_CMD_SRC_SHIFT 0
1494 #define DMAE_CMD_DST_MASK 0x3
1496 #define DMAE_CMD_C_DST_MASK 0x1
1498 #define DMAE_CMD_CRC_RESET_MASK 0x1
1500 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
1502 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
1504 #define DMAE_CMD_COMP_FUNC_MASK 0x1
1506 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1
1508 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1
1510 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
1512 #define DMAE_CMD_RESERVED1_MASK 0x1
1514 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
1516 #define DMAE_CMD_ERR_HANDLING_MASK 0x3
1518 #define DMAE_CMD_PORT_ID_MASK 0x3
1520 #define DMAE_CMD_SRC_PF_ID_MASK 0xF
1522 #define DMAE_CMD_DST_PF_ID_MASK 0xF
1524 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
1526 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
1528 #define DMAE_CMD_RESERVED2_MASK 0x3
1536 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF
1537 #define DMAE_CMD_SRC_VF_ID_SHIFT 0
1538 #define DMAE_CMD_DST_VF_ID_MASK 0xFF
1549 #define DMAE_CMD_ERROR_BIT_MASK 0x1
1550 #define DMAE_CMD_ERROR_BIT_SHIFT 0
1551 #define DMAE_CMD_RESERVED_MASK 0x7FFF
1606 #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1607 #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1608 #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1610 #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1612 #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1614 #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1617 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1618 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1619 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1621 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1623 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1625 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1627 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1629 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1631 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1643 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
1644 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
1645 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
1647 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
1649 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
1651 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
1654 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
1655 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
1656 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
1658 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
1660 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
1662 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
1664 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
1666 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
1668 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
1693 #define QED_DMAE_PARAMS_RW_REPL_SRC_MASK 0x1
1694 #define QED_DMAE_PARAMS_RW_REPL_SRC_SHIFT 0
1695 #define QED_DMAE_PARAMS_SRC_VF_VALID_MASK 0x1
1697 #define QED_DMAE_PARAMS_DST_VF_VALID_MASK 0x1
1699 #define QED_DMAE_PARAMS_COMPLETION_DST_MASK 0x1
1701 #define QED_DMAE_PARAMS_PORT_VALID_MASK 0x1
1703 #define QED_DMAE_PARAMS_SRC_PF_VALID_MASK 0x1
1705 #define QED_DMAE_PARAMS_DST_PF_VALID_MASK 0x1
1707 #define QED_DMAE_PARAMS_RESERVED_MASK 0x1FFFFFF
1721 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
1722 #define IGU_CLEANUP_RESERVED0_SHIFT 0
1723 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
1725 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
1727 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
1742 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
1743 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1744 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
1746 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
1753 #define IGU_MAPPING_LINE_VALID_MASK 0x1
1754 #define IGU_MAPPING_LINE_VALID_SHIFT 0
1755 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
1757 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
1759 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1
1761 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
1763 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
1772 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
1773 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
1774 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
1776 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
1778 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
1785 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1786 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1787 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1789 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1791 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1793 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1795 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1797 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1812 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1813 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1814 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1816 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1818 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1820 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1822 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1824 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1826 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1833 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1834 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1835 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1837 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1839 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1841 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1843 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1845 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1847 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1849 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1851 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1858 #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1
1859 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
1860 #define QM_RF_PQ_MAP_RL_ID_MASK 0xFF
1862 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
1864 #define QM_RF_PQ_MAP_VOQ_MASK 0x1F
1866 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3
1868 #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1
1870 #define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
1877 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1878 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1879 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1881 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1888 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
1889 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1890 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF
1892 #define SDM_OP_GEN_RESERVED_MASK 0xFFF
2015 #define ANY_PHASE_ID 0xffff
2119 #define FW_OVERLAY_BUF_HDR_STORM_ID_MASK 0xFF
2120 #define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0
2121 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK 0xFFFFFF
2128 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
2129 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
2130 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
2137 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
2138 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
2139 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
2146 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
2147 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
2148 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
2155 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
2156 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
2157 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
2159 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
2182 #define INIT_CALLBACK_OP_OP_MASK 0xF
2183 #define INIT_CALLBACK_OP_OP_SHIFT 0
2184 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
2193 #define INIT_DELAY_OP_OP_MASK 0xF
2194 #define INIT_DELAY_OP_OP_SHIFT 0
2195 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
2203 #define INIT_IF_MODE_OP_OP_MASK 0xF
2204 #define INIT_IF_MODE_OP_OP_SHIFT 0
2205 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
2207 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
2216 #define INIT_IF_PHASE_OP_OP_MASK 0xF
2217 #define INIT_IF_PHASE_OP_OP_SHIFT 0
2218 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0xFFF
2220 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
2223 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
2224 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
2225 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
2227 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
2242 #define INIT_RAW_OP_OP_MASK 0xF
2243 #define INIT_RAW_OP_OP_SHIFT 0
2244 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
2266 #define INIT_WRITE_OP_OP_MASK 0xF
2267 #define INIT_WRITE_OP_OP_SHIFT 0
2268 #define INIT_WRITE_OP_SOURCE_MASK 0x7
2270 #define INIT_WRITE_OP_RESERVED_MASK 0x1
2272 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
2274 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
2282 #define INIT_READ_OP_OP_MASK 0xF
2283 #define INIT_READ_OP_OP_SHIFT 0
2284 #define INIT_READ_OP_POLL_TYPE_MASK 0xF
2286 #define INIT_READ_OP_RESERVED_MASK 0x1
2288 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
2343 #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
2346 #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL
2349 #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL
2352 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
2355 #define GTT_BAR0_MAP_REG_MSDM_RAM_2048 0x013000UL
2358 #define GTT_BAR0_MAP_REG_USDM_RAM 0x014000UL
2361 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x015000UL
2364 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x016000UL
2367 #define GTT_BAR0_MAP_REG_XSDM_RAM 0x017000UL
2370 #define GTT_BAR0_MAP_REG_XSDM_RAM_1024 0x018000UL
2373 #define GTT_BAR0_MAP_REG_YSDM_RAM 0x019000UL
2376 #define GTT_BAR0_MAP_REG_PSDM_RAM 0x01a000UL
2424 * Return: 0 on success, -1 on error.
2459 * Return: 0 on success, -1 on error.
2473 * Return: 0 on success, -1 on error.
2486 * Return: 0 on success, -1 on error.
2501 * Return: 0 on success, -1 on error.
2517 * Return: 0 on success, -1 on error.
2533 * Return: 0 on success, -1 on error.
2698 * qed_memset_session_ctx(): Memset session context to 0 while
2710 * qed_memset_task_ctx(): Memset task context to 0 while preserving
2795 #define PCICFG_OFFSET 0x2000
2796 #define GRC_CONFIG_REG_PF_INIT_VF 0x624
2802 * Since registers from 0x000-0x7ff are spilt across functions, each PF will
2805 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xff
2808 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
3250 #define DMAE_READY_CB 0
3271 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
3272 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
3273 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
3275 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
3277 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
3279 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
3281 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
3283 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
3285 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
3288 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
3289 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
3290 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
3292 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
3294 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
3296 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
3298 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
3300 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
3302 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
3305 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
3306 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
3307 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
3309 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3311 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3314 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
3315 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
3316 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
3318 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
3320 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
3323 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
3324 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
3325 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
3327 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
3329 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
3332 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
3333 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
3334 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
3336 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
3338 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
3341 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
3342 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
3343 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
3345 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
3347 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
3350 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
3351 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
3352 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
3354 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
3356 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
3358 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
3361 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3362 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
3363 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
3365 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
3367 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
3369 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
3371 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
3373 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
3375 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
3378 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
3379 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
3380 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
3382 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
3384 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
3386 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
3388 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
3390 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
3392 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
3395 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
3396 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
3397 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
3399 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
3401 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
3403 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
3405 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
3407 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
3409 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
3412 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
3413 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
3414 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
3416 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
3418 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
3420 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
3422 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
3424 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
3426 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
3429 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
3430 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
3431 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
3433 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
3435 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
3437 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
3439 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
3441 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
3443 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
3446 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
3447 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
3448 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
3450 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
3452 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
3454 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
3456 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
3458 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
3460 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
3463 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
3464 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
3465 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
3467 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
3469 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
3471 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
3473 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
3475 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
3539 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
3540 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
3541 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
3543 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
3545 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
3547 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3550 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
3551 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
3552 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
3554 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3556 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
3558 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
3560 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
3562 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
3564 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
3583 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
3584 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
3585 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
3587 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
3589 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
3591 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
3593 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
3595 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
3598 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
3599 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
3600 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3602 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3604 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
3607 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
3608 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
3609 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
3611 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
3613 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
3616 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
3617 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
3618 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
3620 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
3622 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
3624 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3626 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
3629 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
3630 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
3631 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
3633 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
3635 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
3637 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
3639 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
3641 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
3643 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
3646 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
3647 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
3648 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
3650 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
3652 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
3654 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
3656 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
3658 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
3660 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
3687 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
3688 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
3689 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
3691 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
3693 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
3695 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
3698 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
3699 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
3700 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
3702 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
3704 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
3707 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
3708 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
3709 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
3711 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
3713 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
3715 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
3717 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
3719 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
3721 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
3724 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
3725 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
3726 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
3728 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
3730 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
3732 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
3734 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
3736 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
3738 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
3779 ETH_OK = 0x00,
3942 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x3F
3943 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
3944 #define ETH_RETURN_CODE_RESERVED_MASK 0x1
3946 #define ETH_RETURN_CODE_RX_TX_MASK 0x1
3968 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
3969 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
3970 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
3972 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
3974 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
3976 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
3978 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
3980 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
3982 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK 0x1
3984 #define ETH_TX_ERR_VALS_RESERVED_MASK 0xFF
3991 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
3992 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
3993 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
3995 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
3997 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
3999 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
4001 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
4003 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
4005 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
4031 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
4032 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
4033 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
4035 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
4037 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
4039 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
4041 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
4043 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK 0x1
4045 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x1FF
4072 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
4073 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
4074 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
4076 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
4078 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
4080 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
4082 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
4227 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
4228 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
4229 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
4231 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
4233 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
4235 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
4237 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x7
4393 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
4394 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
4395 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1
4397 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1
4399 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
4401 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1
4403 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1
4405 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1
4407 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1
4410 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1
4411 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0
4412 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1
4414 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1
4416 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
4418 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1
4420 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1
4422 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1
4424 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1
4427 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3
4428 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0
4429 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3
4431 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3
4433 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3
4436 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3
4437 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0
4438 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3
4440 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3
4442 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3
4445 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3
4446 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0
4447 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3
4449 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3
4451 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3
4454 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3
4455 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0
4456 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3
4458 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3
4460 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3
4463 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3
4464 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0
4465 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3
4467 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3
4469 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3
4472 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3
4473 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0
4474 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3
4476 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
4478 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
4480 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
4483 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
4484 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
4485 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
4487 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
4489 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
4491 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
4493 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1
4495 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
4497 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
4500 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
4501 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
4502 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
4504 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
4506 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
4508 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
4510 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
4512 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1
4514 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1
4517 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1
4518 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0
4519 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1
4521 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1
4523 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1
4525 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
4527 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1
4529 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1
4531 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1
4534 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1
4535 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0
4536 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1
4538 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1
4540 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
4542 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
4544 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
4546 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
4548 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
4551 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
4552 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
4553 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
4555 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
4557 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
4559 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
4561 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
4563 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
4565 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
4568 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
4569 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
4570 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
4572 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
4574 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
4576 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
4578 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
4580 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
4582 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
4585 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1
4586 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0
4587 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1
4589 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1
4591 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1
4593 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1
4595 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
4597 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3
4622 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
4623 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
4624 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
4626 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
4628 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
4630 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
4633 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
4634 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0
4635 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
4637 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
4639 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
4641 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
4643 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
4645 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
4647 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
4659 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
4660 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
4661 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1
4663 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1
4665 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
4667 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1
4669 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1
4671 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1
4673 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1
4676 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1
4677 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0
4678 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1
4680 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1
4682 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1
4684 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
4686 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
4688 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
4690 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
4693 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3
4694 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0
4695 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3
4697 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3
4699 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3
4702 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3
4703 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0
4704 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3
4706 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3
4708 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3
4711 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3
4712 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0
4713 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3
4715 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3
4717 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3
4720 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3
4721 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0
4722 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3
4724 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3
4726 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3
4729 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
4730 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
4731 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
4733 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3
4735 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
4738 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
4739 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
4740 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3
4742 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3
4744 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1
4746 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1
4749 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1
4750 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0
4751 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1
4753 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1
4755 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1
4757 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1
4759 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1
4761 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1
4763 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1
4766 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1
4767 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0
4768 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1
4770 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1
4772 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1
4774 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1
4776 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1
4778 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
4780 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
4783 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
4784 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
4785 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
4787 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
4789 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1
4791 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
4793 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
4795 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1
4797 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1
4800 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1
4801 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0
4802 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1
4804 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
4806 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1
4808 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1
4810 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1
4812 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
4814 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1
4817 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1
4818 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0
4819 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1
4821 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
4823 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
4825 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1
4827 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1
4829 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1
4831 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1
4834 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1
4835 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0
4836 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1
4838 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
4840 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
4842 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
4844 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
4846 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
4848 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
4851 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
4852 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
4853 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
4855 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
4857 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
4859 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
4861 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
4863 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
4878 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1
4879 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0
4880 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1
4882 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1
4884 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF
4886 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF
4888 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF
4890 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1
4892 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1
4894 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF
4896 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF
4898 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF
4900 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7
4906 GFT_PROFILE_IPV4 = 0,
4914 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1
4915 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0
4916 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1
4918 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF
4920 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF
4922 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF
4924 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3
4930 GFT_PROFILE_NO_TUNNEL = 0,
4941 GFT_PROFILE_ROCE_PROTOCOL = 0,
4963 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3
4964 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0
4965 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1
4967 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1
4969 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1
4971 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1
4973 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1
4975 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1
4977 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1
4979 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1
4981 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1
4983 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1
4985 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1
4987 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1
4989 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1
4991 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1
4993 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1
4995 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1
4997 #define GFT_RAM_LINE_TTL_MASK 0x1
4999 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1
5001 #define GFT_RAM_LINE_RESERVED0_MASK 0x1
5003 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1
5005 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1
5007 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1
5009 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1
5011 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1
5013 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1
5015 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1
5017 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1
5019 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1
5021 #define GFT_RAM_LINE_DST_PORT_MASK 0x1
5023 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1
5026 #define GFT_RAM_LINE_DSCP_MASK 0x1
5027 #define GFT_RAM_LINE_DSCP_SHIFT 0
5028 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1
5030 #define GFT_RAM_LINE_DST_IP_MASK 0x1
5032 #define GFT_RAM_LINE_SRC_IP_MASK 0x1
5034 #define GFT_RAM_LINE_PRIORITY_MASK 0x1
5036 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1
5038 #define GFT_RAM_LINE_VLAN_MASK 0x1
5040 #define GFT_RAM_LINE_DST_MAC_MASK 0x1
5042 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1
5044 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1
5046 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF
5052 INNER_PROVIDER_VLAN = 0,
5069 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5070 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5071 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5073 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5075 #define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1
5077 #define YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1
5080 #define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5081 #define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
5082 #define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5084 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
5086 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
5088 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
5091 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
5092 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
5093 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5095 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5097 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5099 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5101 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5103 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5105 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5125 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5126 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5127 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5129 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5131 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
5133 #define MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1
5136 #define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
5137 #define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0
5138 #define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
5140 #define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
5142 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
5144 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
5147 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
5148 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0
5149 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5151 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5153 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5155 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
5157 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5159 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
5161 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5191 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
5192 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
5193 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
5195 #define USTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
5197 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3
5200 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3
5201 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0
5202 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3
5204 #define USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK 0x3
5206 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
5209 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1
5210 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0
5211 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1
5213 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1
5215 #define USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK 0x1
5217 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
5219 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
5221 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
5223 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
5226 #define USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK 0x1
5227 #define USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_SHIFT 0
5228 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
5230 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK 0x1
5232 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1
5234 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
5297 #define YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5298 #define YSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5299 #define YSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
5301 #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK 0x3
5303 #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_MASK 0x3
5305 #define YSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5308 #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK 0x1
5309 #define YSTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_SHIFT 0
5310 #define YSTORM_TOE_CONN_AG_CTX_RESET_RECEIVED_CF_EN_MASK 0x1
5312 #define YSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
5314 #define YSTORM_TOE_CONN_AG_CTX_REL_SEQ_EN_MASK 0x1
5316 #define YSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
5318 #define YSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
5320 #define YSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5322 #define YSTORM_TOE_CONN_AG_CTX_CONS_PROD_EN_MASK 0x1
5341 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5342 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5343 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
5345 #define XSTORM_TOE_CONN_AG_CTX_RESERVED1_MASK 0x1
5347 #define XSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
5349 #define XSTORM_TOE_CONN_AG_CTX_TX_DEC_RULE_RES_MASK 0x1
5351 #define XSTORM_TOE_CONN_AG_CTX_RESERVED2_MASK 0x1
5353 #define XSTORM_TOE_CONN_AG_CTX_BIT6_MASK 0x1
5355 #define XSTORM_TOE_CONN_AG_CTX_BIT7_MASK 0x1
5358 #define XSTORM_TOE_CONN_AG_CTX_BIT8_MASK 0x1
5359 #define XSTORM_TOE_CONN_AG_CTX_BIT8_SHIFT 0
5360 #define XSTORM_TOE_CONN_AG_CTX_BIT9_MASK 0x1
5362 #define XSTORM_TOE_CONN_AG_CTX_BIT10_MASK 0x1
5364 #define XSTORM_TOE_CONN_AG_CTX_BIT11_MASK 0x1
5366 #define XSTORM_TOE_CONN_AG_CTX_BIT12_MASK 0x1
5368 #define XSTORM_TOE_CONN_AG_CTX_BIT13_MASK 0x1
5370 #define XSTORM_TOE_CONN_AG_CTX_BIT14_MASK 0x1
5372 #define XSTORM_TOE_CONN_AG_CTX_BIT15_MASK 0x1
5375 #define XSTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
5376 #define XSTORM_TOE_CONN_AG_CTX_CF0_SHIFT 0
5377 #define XSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5379 #define XSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5381 #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5384 #define XSTORM_TOE_CONN_AG_CTX_CF4_MASK 0x3
5385 #define XSTORM_TOE_CONN_AG_CTX_CF4_SHIFT 0
5386 #define XSTORM_TOE_CONN_AG_CTX_CF5_MASK 0x3
5388 #define XSTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
5390 #define XSTORM_TOE_CONN_AG_CTX_CF7_MASK 0x3
5393 #define XSTORM_TOE_CONN_AG_CTX_CF8_MASK 0x3
5394 #define XSTORM_TOE_CONN_AG_CTX_CF8_SHIFT 0
5395 #define XSTORM_TOE_CONN_AG_CTX_CF9_MASK 0x3
5397 #define XSTORM_TOE_CONN_AG_CTX_CF10_MASK 0x3
5399 #define XSTORM_TOE_CONN_AG_CTX_CF11_MASK 0x3
5402 #define XSTORM_TOE_CONN_AG_CTX_CF12_MASK 0x3
5403 #define XSTORM_TOE_CONN_AG_CTX_CF12_SHIFT 0
5404 #define XSTORM_TOE_CONN_AG_CTX_CF13_MASK 0x3
5406 #define XSTORM_TOE_CONN_AG_CTX_CF14_MASK 0x3
5408 #define XSTORM_TOE_CONN_AG_CTX_CF15_MASK 0x3
5411 #define XSTORM_TOE_CONN_AG_CTX_CF16_MASK 0x3
5412 #define XSTORM_TOE_CONN_AG_CTX_CF16_SHIFT 0
5413 #define XSTORM_TOE_CONN_AG_CTX_CF17_MASK 0x3
5415 #define XSTORM_TOE_CONN_AG_CTX_CF18_MASK 0x3
5417 #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
5420 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5421 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
5422 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
5424 #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
5426 #define XSTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1
5428 #define XSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
5431 #define XSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
5432 #define XSTORM_TOE_CONN_AG_CTX_CF2EN_SHIFT 0
5433 #define XSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
5435 #define XSTORM_TOE_CONN_AG_CTX_CF4EN_MASK 0x1
5437 #define XSTORM_TOE_CONN_AG_CTX_CF5EN_MASK 0x1
5439 #define XSTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1
5441 #define XSTORM_TOE_CONN_AG_CTX_CF7EN_MASK 0x1
5443 #define XSTORM_TOE_CONN_AG_CTX_CF8EN_MASK 0x1
5445 #define XSTORM_TOE_CONN_AG_CTX_CF9EN_MASK 0x1
5448 #define XSTORM_TOE_CONN_AG_CTX_CF10EN_MASK 0x1
5449 #define XSTORM_TOE_CONN_AG_CTX_CF10EN_SHIFT 0
5450 #define XSTORM_TOE_CONN_AG_CTX_CF11EN_MASK 0x1
5452 #define XSTORM_TOE_CONN_AG_CTX_CF12EN_MASK 0x1
5454 #define XSTORM_TOE_CONN_AG_CTX_CF13EN_MASK 0x1
5456 #define XSTORM_TOE_CONN_AG_CTX_CF14EN_MASK 0x1
5458 #define XSTORM_TOE_CONN_AG_CTX_CF15EN_MASK 0x1
5460 #define XSTORM_TOE_CONN_AG_CTX_CF16EN_MASK 0x1
5462 #define XSTORM_TOE_CONN_AG_CTX_CF17EN_MASK 0x1
5465 #define XSTORM_TOE_CONN_AG_CTX_CF18EN_MASK 0x1
5466 #define XSTORM_TOE_CONN_AG_CTX_CF18EN_SHIFT 0
5467 #define XSTORM_TOE_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
5469 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
5471 #define XSTORM_TOE_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
5473 #define XSTORM_TOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
5475 #define XSTORM_TOE_CONN_AG_CTX_CF23EN_MASK 0x1
5477 #define XSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
5479 #define XSTORM_TOE_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
5482 #define XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
5483 #define XSTORM_TOE_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
5484 #define XSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5486 #define XSTORM_TOE_CONN_AG_CTX_RESERVED3_MASK 0x1
5488 #define XSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1
5490 #define XSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1
5492 #define XSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1
5494 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
5496 #define XSTORM_TOE_CONN_AG_CTX_RULE9EN_MASK 0x1
5499 #define XSTORM_TOE_CONN_AG_CTX_RULE10EN_MASK 0x1
5500 #define XSTORM_TOE_CONN_AG_CTX_RULE10EN_SHIFT 0
5501 #define XSTORM_TOE_CONN_AG_CTX_RULE11EN_MASK 0x1
5503 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
5505 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
5507 #define XSTORM_TOE_CONN_AG_CTX_RULE14EN_MASK 0x1
5509 #define XSTORM_TOE_CONN_AG_CTX_RULE15EN_MASK 0x1
5511 #define XSTORM_TOE_CONN_AG_CTX_RULE16EN_MASK 0x1
5513 #define XSTORM_TOE_CONN_AG_CTX_RULE17EN_MASK 0x1
5516 #define XSTORM_TOE_CONN_AG_CTX_RULE18EN_MASK 0x1
5517 #define XSTORM_TOE_CONN_AG_CTX_RULE18EN_SHIFT 0
5518 #define XSTORM_TOE_CONN_AG_CTX_RULE19EN_MASK 0x1
5520 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
5522 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
5524 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
5526 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
5528 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
5530 #define XSTORM_TOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
5533 #define XSTORM_TOE_CONN_AG_CTX_BIT16_MASK 0x1
5534 #define XSTORM_TOE_CONN_AG_CTX_BIT16_SHIFT 0
5535 #define XSTORM_TOE_CONN_AG_CTX_BIT17_MASK 0x1
5537 #define XSTORM_TOE_CONN_AG_CTX_BIT18_MASK 0x1
5539 #define XSTORM_TOE_CONN_AG_CTX_BIT19_MASK 0x1
5541 #define XSTORM_TOE_CONN_AG_CTX_BIT20_MASK 0x1
5543 #define XSTORM_TOE_CONN_AG_CTX_BIT21_MASK 0x1
5545 #define XSTORM_TOE_CONN_AG_CTX_CF23_MASK 0x3
5598 #define TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5599 #define TSTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5600 #define TSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
5602 #define TSTORM_TOE_CONN_AG_CTX_BIT2_MASK 0x1
5604 #define TSTORM_TOE_CONN_AG_CTX_BIT3_MASK 0x1
5606 #define TSTORM_TOE_CONN_AG_CTX_BIT4_MASK 0x1
5608 #define TSTORM_TOE_CONN_AG_CTX_BIT5_MASK 0x1
5610 #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_MASK 0x3
5613 #define TSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5614 #define TSTORM_TOE_CONN_AG_CTX_CF1_SHIFT 0
5615 #define TSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
5617 #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5619 #define TSTORM_TOE_CONN_AG_CTX_CF4_MASK 0x3
5622 #define TSTORM_TOE_CONN_AG_CTX_CF5_MASK 0x3
5623 #define TSTORM_TOE_CONN_AG_CTX_CF5_SHIFT 0
5624 #define TSTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
5626 #define TSTORM_TOE_CONN_AG_CTX_CF7_MASK 0x3
5628 #define TSTORM_TOE_CONN_AG_CTX_CF8_MASK 0x3
5631 #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
5632 #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
5633 #define TSTORM_TOE_CONN_AG_CTX_CF10_MASK 0x3
5635 #define TSTORM_TOE_CONN_AG_CTX_TIMEOUT_CF_EN_MASK 0x1
5637 #define TSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
5639 #define TSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
5641 #define TSTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
5644 #define TSTORM_TOE_CONN_AG_CTX_CF4EN_MASK 0x1
5645 #define TSTORM_TOE_CONN_AG_CTX_CF4EN_SHIFT 0
5646 #define TSTORM_TOE_CONN_AG_CTX_CF5EN_MASK 0x1
5648 #define TSTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1
5650 #define TSTORM_TOE_CONN_AG_CTX_CF7EN_MASK 0x1
5652 #define TSTORM_TOE_CONN_AG_CTX_CF8EN_MASK 0x1
5654 #define TSTORM_TOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
5656 #define TSTORM_TOE_CONN_AG_CTX_CF10EN_MASK 0x1
5658 #define TSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
5661 #define TSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
5662 #define TSTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT 0
5663 #define TSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
5665 #define TSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5667 #define TSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1
5669 #define TSTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1
5671 #define TSTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1
5673 #define TSTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1
5675 #define TSTORM_TOE_CONN_AG_CTX_RULE8EN_MASK 0x1
5695 #define USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
5696 #define USTORM_TOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
5697 #define USTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
5699 #define USTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
5701 #define USTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
5703 #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_MASK 0x3
5706 #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
5707 #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 0
5708 #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_MASK 0x3
5710 #define USTORM_TOE_CONN_AG_CTX_DQ_CF_MASK 0x3
5712 #define USTORM_TOE_CONN_AG_CTX_CF6_MASK 0x3
5715 #define USTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1
5716 #define USTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT 0
5717 #define USTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
5719 #define USTORM_TOE_CONN_AG_CTX_PUSH_TIMER_CF_EN_MASK 0x1
5721 #define USTORM_TOE_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
5723 #define USTORM_TOE_CONN_AG_CTX_SLOW_PATH_CF_EN_MASK 0x1
5725 #define USTORM_TOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
5727 #define USTORM_TOE_CONN_AG_CTX_CF6EN_MASK 0x1
5729 #define USTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
5732 #define USTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
5733 #define USTORM_TOE_CONN_AG_CTX_RULE1EN_SHIFT 0
5734 #define USTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
5736 #define USTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
5738 #define USTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1
5740 #define USTORM_TOE_CONN_AG_CTX_RULE5EN_MASK 0x1
5742 #define USTORM_TOE_CONN_AG_CTX_RULE6EN_MASK 0x1
5744 #define USTORM_TOE_CONN_AG_CTX_RULE7EN_MASK 0x1
5746 #define USTORM_TOE_CONN_AG_CTX_RULE8EN_MASK 0x1
5876 #define TOE_RX_BD_START_MASK 0x1
5877 #define TOE_RX_BD_START_SHIFT 0
5878 #define TOE_RX_BD_END_MASK 0x1
5880 #define TOE_RX_BD_NO_PUSH_MASK 0x1
5882 #define TOE_RX_BD_SPLIT_MASK 0x1
5884 #define TOE_RX_BD_RESERVED0_MASK 0xFFF
5889 /* TOE RX completion queue opcodes (opcode 0 is illegal) */
5989 #define TOE_TX_BD_PUSH_MASK 0x1
5990 #define TOE_TX_BD_PUSH_SHIFT 0
5991 #define TOE_TX_BD_NOTIFY_MASK 0x1
5993 #define TOE_TX_BD_LARGE_IO_MASK 0x1
5995 #define TOE_TX_BD_BD_CONS_MASK 0x1FFF
6033 #define TOE_UPDATE_PARAMS_RCV_INDICATION_SIZE_CHANGED_MASK 0x1
6034 #define TOE_UPDATE_PARAMS_RCV_INDICATION_SIZE_CHANGED_SHIFT 0
6035 #define TOE_UPDATE_PARAMS_RESERVED_MASK 0x7FFF
6051 #define MSTORM_TOE_CONN_AG_CTX_BIT0_MASK 0x1
6052 #define MSTORM_TOE_CONN_AG_CTX_BIT0_SHIFT 0
6053 #define MSTORM_TOE_CONN_AG_CTX_BIT1_MASK 0x1
6055 #define MSTORM_TOE_CONN_AG_CTX_CF0_MASK 0x3
6057 #define MSTORM_TOE_CONN_AG_CTX_CF1_MASK 0x3
6059 #define MSTORM_TOE_CONN_AG_CTX_CF2_MASK 0x3
6062 #define MSTORM_TOE_CONN_AG_CTX_CF0EN_MASK 0x1
6063 #define MSTORM_TOE_CONN_AG_CTX_CF0EN_SHIFT 0
6064 #define MSTORM_TOE_CONN_AG_CTX_CF1EN_MASK 0x1
6066 #define MSTORM_TOE_CONN_AG_CTX_CF2EN_MASK 0x1
6068 #define MSTORM_TOE_CONN_AG_CTX_RULE0EN_MASK 0x1
6070 #define MSTORM_TOE_CONN_AG_CTX_RULE1EN_MASK 0x1
6072 #define MSTORM_TOE_CONN_AG_CTX_RULE2EN_MASK 0x1
6074 #define MSTORM_TOE_CONN_AG_CTX_RULE3EN_MASK 0x1
6076 #define MSTORM_TOE_CONN_AG_CTX_RULE4EN_MASK 0x1
6087 #define TOE_DB_DATA_DEST_MASK 0x3
6088 #define TOE_DB_DATA_DEST_SHIFT 0
6089 #define TOE_DB_DATA_AGG_CMD_MASK 0x3
6091 #define TOE_DB_DATA_BYPASS_EN_MASK 0x1
6093 #define TOE_DB_DATA_RESERVED_MASK 0x1
6095 #define TOE_DB_DATA_AGG_VAL_SEL_MASK 0x3
6135 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6136 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 0
6137 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_MASK 0x7F
6179 RDMA_RETURN_OK = 0,
6199 #define RDMA_INIT_FUNC_HDR_SEARCHER_MODE_MASK 0x1
6200 #define RDMA_INIT_FUNC_HDR_SEARCHER_MODE_SHIFT 0
6201 #define RDMA_INIT_FUNC_HDR_PVRDMA_MODE_MASK 0x1
6203 #define RDMA_INIT_FUNC_HDR_DPT_MODE_MASK 0x1
6205 #define RDMA_INIT_FUNC_HDR_RESERVED0_MASK 0x1F
6246 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F
6247 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0
6248 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1
6250 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1
6252 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1
6254 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1
6256 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1
6258 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1
6260 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1
6262 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1
6264 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1
6266 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3
6269 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F
6270 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0
6271 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7
6274 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1
6275 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0
6276 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1
6278 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F
6304 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1
6305 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0
6306 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1
6308 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6310 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x1F
6329 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1
6330 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT 0
6331 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
6333 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK 0x3F
6378 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF
6379 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0
6380 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1
6382 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1
6384 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1
6386 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1
6389 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1
6390 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0
6391 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1
6393 #define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3
6395 #define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3
6397 #define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3
6400 #define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3
6401 #define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0
6402 #define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3
6404 #define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3
6406 #define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3
6409 #define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3
6410 #define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0
6411 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1
6413 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1
6415 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1
6417 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1
6419 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1
6421 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1
6424 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1
6425 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0
6426 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1
6428 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1
6430 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1
6432 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1
6434 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1
6436 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1
6438 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1
6456 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6457 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6458 #define USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK 0x1
6460 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6462 #define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3
6464 #define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3
6467 #define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3
6468 #define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0
6469 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
6471 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
6473 #define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3
6476 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6477 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
6478 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1
6480 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1
6482 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1
6484 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
6486 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
6488 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1
6490 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
6493 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1
6494 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0
6495 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1
6497 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1
6499 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1
6501 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1
6503 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1
6505 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1
6507 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1
6525 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6526 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6527 #define XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
6529 #define XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1
6531 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
6533 #define XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1
6535 #define XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1
6537 #define XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK 0x1
6539 #define XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK 0x1
6542 #define XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK 0x1
6543 #define XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT 0
6544 #define XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK 0x1
6546 #define XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK 0x1
6548 #define XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK 0x1
6550 #define XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
6552 #define XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
6554 #define XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK 0x1
6556 #define XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
6559 #define XSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
6560 #define XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 0
6561 #define XSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
6563 #define XSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
6565 #define XSTORM_ROCE_CONN_AG_CTX_CF3_MASK 0x3
6568 #define XSTORM_ROCE_CONN_AG_CTX_CF4_MASK 0x3
6569 #define XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT 0
6570 #define XSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
6572 #define XSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
6574 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6577 #define XSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
6578 #define XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 0
6579 #define XSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
6581 #define XSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
6583 #define XSTORM_ROCE_CONN_AG_CTX_CF11_MASK 0x3
6586 #define XSTORM_ROCE_CONN_AG_CTX_CF12_MASK 0x3
6587 #define XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT 0
6588 #define XSTORM_ROCE_CONN_AG_CTX_CF13_MASK 0x3
6590 #define XSTORM_ROCE_CONN_AG_CTX_CF14_MASK 0x3
6592 #define XSTORM_ROCE_CONN_AG_CTX_CF15_MASK 0x3
6595 #define XSTORM_ROCE_CONN_AG_CTX_CF16_MASK 0x3
6596 #define XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT 0
6597 #define XSTORM_ROCE_CONN_AG_CTX_CF17_MASK 0x3
6599 #define XSTORM_ROCE_CONN_AG_CTX_CF18_MASK 0x3
6601 #define XSTORM_ROCE_CONN_AG_CTX_CF19_MASK 0x3
6604 #define XSTORM_ROCE_CONN_AG_CTX_CF20_MASK 0x3
6605 #define XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT 0
6606 #define XSTORM_ROCE_CONN_AG_CTX_CF21_MASK 0x3
6608 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
6610 #define XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
6612 #define XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
6615 #define XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
6616 #define XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 0
6617 #define XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK 0x1
6619 #define XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK 0x1
6621 #define XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1
6623 #define XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1
6625 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6627 #define XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1
6629 #define XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1
6632 #define XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1
6633 #define XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 0
6634 #define XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK 0x1
6636 #define XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK 0x1
6638 #define XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK 0x1
6640 #define XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK 0x1
6642 #define XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK 0x1
6644 #define XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK 0x1
6646 #define XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK 0x1
6649 #define XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK 0x1
6650 #define XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT 0
6651 #define XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK 0x1
6653 #define XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK 0x1
6655 #define XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK 0x1
6657 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
6659 #define XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK 0x1
6661 #define XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
6663 #define XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
6666 #define XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
6667 #define XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 0
6668 #define XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
6670 #define XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
6672 #define XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1
6674 #define XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1
6676 #define XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1
6678 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
6680 #define XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK 0x1
6683 #define XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK 0x1
6684 #define XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT 0
6685 #define XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK 0x1
6687 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
6689 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
6691 #define XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK 0x1
6693 #define XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK 0x1
6695 #define XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK 0x1
6697 #define XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK 0x1
6700 #define XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK 0x1
6701 #define XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT 0
6702 #define XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK 0x1
6704 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
6706 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
6708 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
6710 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
6712 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
6714 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
6717 #define XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK 0x1
6718 #define XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT 0
6719 #define XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK 0x1
6721 #define XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
6723 #define XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK 0x1
6725 #define XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
6727 #define XSTORM_ROCE_CONN_AG_CTX_CF23_MASK 0x3
6754 #define TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
6755 #define TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
6756 #define TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
6758 #define TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1
6760 #define TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK 0x1
6762 #define TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1
6764 #define TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1
6766 #define TSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
6769 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
6770 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
6771 #define TSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
6773 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
6775 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
6778 #define TSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3
6779 #define TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 0
6780 #define TSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3
6782 #define TSTORM_ROCE_CONN_AG_CTX_CF7_MASK 0x3
6784 #define TSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3
6787 #define TSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3
6788 #define TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 0
6789 #define TSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3
6791 #define TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
6793 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
6795 #define TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
6797 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
6800 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
6801 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
6802 #define TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1
6804 #define TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1
6806 #define TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK 0x1
6808 #define TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1
6810 #define TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1
6812 #define TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1
6814 #define TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
6817 #define TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
6818 #define TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 0
6819 #define TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
6821 #define TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
6823 #define TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
6825 #define TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1
6827 #define TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1
6829 #define TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1
6831 #define TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1
6915 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
6916 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
6917 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
6919 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
6921 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
6923 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1
6925 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
6927 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
6957 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK 0x1
6958 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT 0
6959 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6961 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FORCE_LB_MASK 0x1
6963 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1F
6974 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3
6975 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0
6976 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
6978 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
6980 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
6982 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1
6984 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
6986 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
6988 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
6990 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
6992 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1
6994 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK 0x1
6996 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_FORCE_LB_MASK 0x1
6998 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x1FFF
7039 #define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_ERR_FLG_MASK 0x1
7040 #define ROCE_CREATE_SUSPENDED_QP_REQ_RUNTIME_RAMROD_DATA_ERR_FLG_SHIFT 0
7042 0x7FFFFFFF
7059 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_MASK 0x1
7060 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_SHIFT 0
7061 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_MASK 0x1
7063 #define ROCE_CREATE_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7198 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
7199 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0
7200 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
7202 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK 0x3F
7220 #define ROCE_LL2_CQE_DATA_QP_SUSPENDED_MASK 0x1
7221 #define ROCE_LL2_CQE_DATA_QP_SUSPENDED_SHIFT 0
7222 #define ROCE_LL2_CQE_DATA_RESERVED0_MASK 0x7F
7231 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7232 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7233 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1
7235 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1
7237 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7239 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7241 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1
7243 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1
7245 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1
7247 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1
7249 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1
7251 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7
7253 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
7255 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_FORCE_LB_MASK 0x1
7257 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x1
7260 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF
7261 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0
7262 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF
7282 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
7283 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0
7284 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
7286 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
7288 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
7290 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1
7292 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1
7294 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1
7296 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1
7298 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1
7300 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
7302 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
7304 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_FORCE_LB_MASK 0x1
7306 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0xF
7309 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
7310 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0
7311 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
7330 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7331 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
7332 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1
7334 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7347 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
7348 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
7349 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
7362 #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1
7363 #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0
7364 #define ROCE_QUERY_SUSPENDED_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
7381 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_MASK 0x1
7382 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_ERR_FLG_SHIFT 0
7383 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RDMA_ACTIVE_MASK 0x1
7385 #define ROCE_QUERY_SUSPENDED_QP_RESP_RUNTIME_PARAMS_RESERVED0_MASK 0x3FFFFFFF
7430 ROCE_QP_RDB_ENTRY_RDMA_RESPONSE = 0,
7441 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1
7442 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0
7443 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1
7445 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK 0x3FFF
7454 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1
7455 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0
7456 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1
7458 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1
7460 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1
7462 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1
7464 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1
7466 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1
7468 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1
7471 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1
7472 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0
7473 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1
7475 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1
7477 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1
7479 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1
7481 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1
7483 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1
7485 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1
7488 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3
7489 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0
7490 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3
7492 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3
7494 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3
7497 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3
7498 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0
7499 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3
7501 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3
7503 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3
7506 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3
7507 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0
7508 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3
7510 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3
7512 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3
7515 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3
7516 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0
7517 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3
7519 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3
7521 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3
7524 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3
7525 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0
7526 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3
7528 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3
7530 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3
7533 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3
7534 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0
7535 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3
7537 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3
7539 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1
7541 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1
7544 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1
7545 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0
7546 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1
7548 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1
7550 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1
7552 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1
7554 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1
7556 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1
7558 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1
7561 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1
7562 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0
7563 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1
7565 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1
7567 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1
7569 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1
7571 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1
7573 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1
7575 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1
7578 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1
7579 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0
7580 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1
7582 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1
7584 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1
7586 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1
7588 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1
7590 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1
7592 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1
7595 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1
7596 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0
7597 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1
7599 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1
7601 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1
7603 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1
7605 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1
7607 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1
7609 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1
7612 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1
7613 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0
7614 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1
7616 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1
7618 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1
7620 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1
7622 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1
7624 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1
7626 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1
7629 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1
7630 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0
7631 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1
7633 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1
7635 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1
7637 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1
7639 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1
7641 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1
7643 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1
7646 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1
7647 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0
7648 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1
7650 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3
7652 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1
7654 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1
7656 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3
7681 #define MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1
7682 #define MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0
7683 #define MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
7685 #define MSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
7687 #define MSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
7689 #define MSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
7692 #define MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
7693 #define MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0
7694 #define MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
7696 #define MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
7698 #define MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
7700 #define MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
7702 #define MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
7704 #define MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
7706 #define MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
7718 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
7719 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
7720 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
7722 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
7724 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
7726 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
7729 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
7730 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
7731 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
7733 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
7735 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7737 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7739 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
7741 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7743 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7755 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
7756 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
7757 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
7759 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7761 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
7763 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
7766 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7767 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
7768 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
7770 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
7772 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7774 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7776 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7778 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7780 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7792 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7793 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7794 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1
7796 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1
7798 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1
7800 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7802 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
7804 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3
7807 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7808 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7809 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3
7811 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
7813 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7816 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK 0x3
7817 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT 0
7818 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3
7820 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3
7822 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3
7825 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3
7826 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0
7827 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3
7829 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1
7831 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7833 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1
7835 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
7838 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7839 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7840 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK 0x1
7842 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1
7844 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1
7846 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1
7848 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1
7850 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1
7852 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
7855 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
7856 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
7857 #define TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK 0x1
7859 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
7861 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
7863 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
7865 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1
7867 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
7869 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
7896 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
7897 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
7898 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1
7900 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1
7902 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1
7904 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1
7906 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1
7908 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
7911 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3
7912 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0
7913 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3
7915 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
7917 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
7920 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
7921 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0
7922 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
7924 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3
7926 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
7929 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
7930 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0
7931 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
7933 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
7935 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1
7937 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1
7939 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
7942 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
7943 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0
7944 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
7946 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
7948 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1
7950 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
7952 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
7954 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
7956 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
7959 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
7960 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
7961 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
7963 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
7965 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
7967 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
7969 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1
7971 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
7973 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
8000 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8001 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8002 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8004 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8006 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8008 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8011 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8012 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0
8013 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3
8015 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3
8017 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3
8020 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8021 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8022 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8024 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8026 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
8028 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1
8030 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1
8032 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1
8034 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8037 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8038 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0
8039 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8041 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8043 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8045 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8047 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
8049 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1
8051 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1
8069 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8070 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8071 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8073 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8075 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8077 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8080 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8081 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0
8082 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3
8084 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3
8086 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3
8089 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8090 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8091 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8093 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8095 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8097 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1
8099 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1
8101 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1
8103 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8106 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8107 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0
8108 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8110 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8112 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8114 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8116 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8118 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8120 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1
8138 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8139 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8140 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1
8142 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1
8144 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8146 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1
8148 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1
8150 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1
8152 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1
8155 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1
8156 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0
8157 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1
8159 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1
8161 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1
8163 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
8165 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
8167 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8169 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8172 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8173 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0
8174 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8176 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8178 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3
8181 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8182 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0
8183 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8185 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3
8187 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8190 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK 0x3
8191 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT 0
8192 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK 0x3
8194 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3
8196 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3
8199 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3
8200 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0
8201 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3
8203 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3
8205 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3
8208 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3
8209 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0
8210 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3
8212 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3
8214 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3
8217 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3
8218 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0
8219 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3
8221 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8223 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8225 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8228 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8229 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0
8230 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1
8232 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8234 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8236 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1
8238 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8240 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
8242 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK 0x1
8245 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1
8246 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0
8247 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1
8249 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1
8251 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1
8253 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1
8255 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1
8257 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1
8259 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1
8262 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1
8263 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0
8264 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1
8266 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1
8268 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1
8270 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8272 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1
8274 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8276 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8279 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8280 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0
8281 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8283 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8285 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1
8287 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1
8289 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1
8291 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8293 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1
8296 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1
8297 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0
8298 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1
8300 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8302 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8304 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1
8306 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1
8308 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1
8310 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1
8313 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1
8314 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0
8315 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1
8317 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8319 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8321 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8323 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8325 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8327 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8330 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1
8331 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0
8332 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1
8334 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3
8336 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1
8338 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
8340 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3
8367 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8368 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8369 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1
8371 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1
8373 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8375 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1
8377 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1
8379 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1
8381 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1
8384 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1
8385 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0
8386 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1
8388 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1
8390 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1
8392 #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1
8394 #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1
8396 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1
8398 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1
8401 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8402 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0
8403 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8405 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8407 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3
8410 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3
8411 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0
8412 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3
8414 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3
8416 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
8419 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3
8420 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0
8421 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3
8423 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3
8425 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3
8428 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3
8429 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0
8430 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3
8432 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3
8434 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3
8437 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3
8438 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0
8439 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3
8441 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3
8443 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3
8446 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3
8447 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0
8448 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3
8450 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8452 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8454 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8457 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8458 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0
8459 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1
8461 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1
8463 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1
8465 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1
8467 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
8469 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1
8471 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1
8474 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1
8475 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0
8476 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1
8478 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1
8480 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1
8482 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1
8484 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1
8486 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1
8488 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1
8491 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1
8492 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0
8493 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1
8495 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1
8497 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1
8499 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8501 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1
8503 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8505 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8508 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8509 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0
8510 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8512 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8514 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1
8516 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1
8518 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1
8520 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8522 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1
8525 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1
8526 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0
8527 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1
8529 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8531 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8533 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1
8535 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1
8537 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1
8539 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1
8542 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1
8543 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0
8544 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1
8546 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
8548 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
8550 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8552 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
8554 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8556 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8559 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1
8560 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0
8561 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1
8563 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1
8565 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1
8567 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1
8569 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1
8571 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3
8598 #define YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1
8599 #define YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0
8600 #define YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1
8602 #define YSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3
8604 #define YSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3
8606 #define YSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3
8609 #define YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1
8610 #define YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0
8611 #define YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1
8613 #define YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1
8615 #define YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1
8617 #define YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1
8619 #define YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1
8621 #define YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1
8623 #define YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1
8642 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1
8643 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0
8644 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1
8646 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3
8648 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3
8650 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3
8653 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1
8654 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0
8655 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1
8657 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1
8659 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1
8661 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1
8663 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1
8665 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1
8667 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1
8686 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1
8687 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0
8688 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1
8690 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3
8692 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3
8694 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3
8697 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1
8698 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0
8699 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1
8701 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1
8703 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1
8705 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1
8707 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1
8709 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1
8711 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1
8753 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
8754 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
8755 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
8757 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1
8759 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
8761 #define XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
8763 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1
8765 #define XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1
8767 #define XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1
8770 #define XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1
8771 #define XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0
8772 #define XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1
8774 #define XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1
8776 #define XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1
8778 #define XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1
8780 #define XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1
8782 #define XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1
8784 #define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1
8787 #define XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
8788 #define XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0
8789 #define XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
8791 #define XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
8793 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
8796 #define XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
8797 #define XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0
8798 #define XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
8800 #define XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
8802 #define XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
8805 #define XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
8806 #define XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0
8807 #define XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3
8809 #define XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3
8811 #define XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3
8814 #define XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3
8815 #define XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0
8816 #define XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3
8818 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3
8820 #define XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3
8823 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3
8824 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
8825 #define XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3
8827 #define XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3
8829 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
8832 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
8833 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
8834 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3
8836 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3
8838 #define XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
8840 #define XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
8843 #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
8844 #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0
8845 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
8847 #define XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
8849 #define XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
8851 #define XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
8853 #define XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
8855 #define XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
8857 #define XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1
8860 #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1
8861 #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0
8862 #define XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1
8864 #define XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1
8866 #define XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1
8868 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1
8870 #define XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1
8872 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
8874 #define XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1
8877 #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1
8878 #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0
8879 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
8881 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
8883 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1
8885 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
8887 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK 0x1
8889 #define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
8891 #define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1
8894 #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
8895 #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
8896 #define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
8898 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1
8900 #define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
8902 #define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
8904 #define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
8906 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
8908 #define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1
8911 #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1
8912 #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0
8913 #define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1
8915 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
8917 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
8919 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1
8921 #define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1
8923 #define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1
8925 #define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1
8928 #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1
8929 #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0
8930 #define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1
8932 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1
8934 #define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1
8936 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
8938 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1
8940 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
8942 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
8945 #define XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1
8946 #define XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0
8947 #define XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1
8949 #define XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1
8951 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1
8953 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1
8955 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1
8957 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK 0x3
9010 #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9011 #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9012 #define TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9014 #define TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1
9016 #define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK 0x1
9018 #define TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1
9020 #define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1
9022 #define TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9025 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3
9026 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0
9027 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3
9029 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
9031 #define TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3
9034 #define TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3
9035 #define TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0
9036 #define TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9038 #define TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3
9040 #define TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3
9043 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
9044 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0
9045 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3
9047 #define TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9049 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1
9051 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1
9053 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
9056 #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1
9057 #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0
9058 #define TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1
9060 #define TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9062 #define TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1
9064 #define TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1
9066 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1
9068 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1
9070 #define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9073 #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9074 #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0
9075 #define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9077 #define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9079 #define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9081 #define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9083 #define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1
9085 #define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9087 #define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
9146 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1
9147 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0
9148 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1
9150 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9152 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9154 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9156 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1
9158 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK 0x1
9160 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x1
9271 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1
9272 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0
9273 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1
9275 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1
9277 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1
9279 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1
9281 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1
9283 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x3FF
9321 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7
9322 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0
9323 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F
9353 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1
9354 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
9355 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF
9401 MPA_RTR_TYPE_NONE = 0,
9417 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1
9418 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0
9419 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1
9421 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F
9430 #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9431 #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9432 #define MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9434 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3
9436 #define MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9438 #define MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9441 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1
9442 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0
9443 #define MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9445 #define MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9447 #define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9449 #define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9451 #define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9453 #define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1
9455 #define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9467 #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9468 #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9469 #define USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9471 #define USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9473 #define USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9475 #define USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9478 #define USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3
9479 #define USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0
9480 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3
9482 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3
9484 #define USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3
9487 #define USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9488 #define USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
9489 #define USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9491 #define USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9493 #define USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1
9495 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1
9497 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1
9499 #define USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1
9501 #define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1
9504 #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1
9505 #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0
9506 #define USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9508 #define USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9510 #define USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9512 #define USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1
9514 #define USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1
9516 #define USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1
9518 #define USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1
9536 #define YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1
9537 #define YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0
9538 #define YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1
9540 #define YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3
9542 #define YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3
9544 #define YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3
9547 #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1
9548 #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0
9549 #define YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1
9551 #define YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1
9553 #define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1
9555 #define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1
9557 #define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1
9559 #define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1
9561 #define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1
9592 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
9593 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0
9594 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
9596 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F
9602 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9603 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0
9604 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
9606 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F
9614 #define FCOE_VLAN_FIELDS_VID_MASK 0xFFF
9615 #define FCOE_VLAN_FIELDS_VID_SHIFT 0
9616 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1
9618 #define FCOE_VLAN_FIELDS_PRI_MASK 0x7
9668 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1
9669 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0
9670 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1
9672 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9674 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1
9676 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1
9678 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x7
9697 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1
9698 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0
9699 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1
9701 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1
9703 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3
9705 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7
9732 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1
9733 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0
9734 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1
9736 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1
9738 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1
9740 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF
9742 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF
9756 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
9757 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
9758 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1
9760 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1
9762 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
9764 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1
9766 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1
9768 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1
9770 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1
9773 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1
9774 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0
9775 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1
9777 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1
9779 #define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1
9781 #define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1
9783 #define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1
9785 #define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1
9787 #define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1
9790 #define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
9791 #define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0
9792 #define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
9794 #define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
9796 #define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
9799 #define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
9800 #define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0
9801 #define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
9803 #define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
9805 #define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
9808 #define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
9809 #define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0
9810 #define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
9812 #define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
9814 #define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3
9817 #define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3
9818 #define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0
9819 #define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3
9821 #define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3
9823 #define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3
9826 #define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3
9827 #define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0
9828 #define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3
9830 #define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3
9832 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3
9835 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
9836 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
9837 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3
9839 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
9841 #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
9843 #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
9846 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
9847 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0
9848 #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
9850 #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
9852 #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
9854 #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
9856 #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
9858 #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
9860 #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
9863 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
9864 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0
9865 #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1
9867 #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1
9869 #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1
9871 #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1
9873 #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1
9875 #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1
9877 #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1
9880 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1
9881 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0
9882 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
9884 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
9886 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1
9888 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
9890 #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1
9892 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1
9894 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1
9897 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1
9898 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0
9899 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1
9901 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1
9903 #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
9905 #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
9907 #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
9909 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
9911 #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1
9914 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1
9915 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0
9916 #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1
9918 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
9920 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
9922 #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1
9924 #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1
9926 #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1
9928 #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1
9931 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1
9932 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0
9933 #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1
9935 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
9937 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
9939 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
9941 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
9943 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
9945 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
9948 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1
9949 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0
9950 #define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1
9952 #define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1
9954 #define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1
9956 #define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1
9958 #define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1
9960 #define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3
10003 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10004 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10005 #define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10007 #define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1
10009 #define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1
10011 #define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1
10013 #define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1
10015 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3
10018 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3
10019 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0
10020 #define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10022 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3
10024 #define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10027 #define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10028 #define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0
10029 #define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10031 #define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3
10033 #define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3
10036 #define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3
10037 #define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0
10038 #define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3
10040 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1
10042 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1
10044 #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10046 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1
10049 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
10050 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0
10051 #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10053 #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10055 #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1
10057 #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1
10059 #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1
10061 #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1
10063 #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10066 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10067 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
10068 #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10070 #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10072 #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10074 #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10076 #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10078 #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10080 #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
10090 #define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10091 #define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10092 #define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10094 #define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10096 #define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10098 #define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10101 #define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3
10102 #define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0
10103 #define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3
10105 #define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3
10107 #define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3
10110 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10111 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10112 #define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10114 #define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10116 #define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1
10118 #define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1
10120 #define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1
10122 #define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1
10124 #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10127 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10128 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0
10129 #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10131 #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10133 #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10135 #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1
10137 #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1
10139 #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1
10141 #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1
10161 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1
10162 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0
10163 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1
10165 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F
10173 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3
10174 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0
10175 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F
10187 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10188 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10189 #define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10191 #define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10193 #define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10195 #define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10198 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10199 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10200 #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10202 #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10204 #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10206 #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10208 #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10210 #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10212 #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10226 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1
10227 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
10228 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1
10230 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F
10328 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1
10329 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0
10330 #define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1
10332 #define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3
10334 #define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3
10336 #define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3
10339 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1
10340 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0
10341 #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1
10343 #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1
10345 #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1
10347 #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1
10349 #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1
10351 #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1
10353 #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1
10389 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10390 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10391 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1
10393 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1
10395 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
10397 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10399 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1
10401 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1
10403 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1
10406 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1
10407 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0
10408 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1
10410 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1
10412 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1
10414 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1
10416 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1
10418 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1
10420 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1
10423 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10424 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0
10425 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10427 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10429 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10432 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10433 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0
10434 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10436 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10438 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10441 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10442 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0
10443 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3
10445 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3
10447 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3
10450 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3
10451 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0
10452 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3
10454 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3
10456 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3
10459 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3
10460 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0
10461 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3
10463 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3
10465 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3
10468 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3
10469 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0
10470 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3
10472 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3
10474 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10476 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10479 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10480 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0
10481 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10483 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10485 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10487 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10489 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
10491 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
10493 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1
10496 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1
10497 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0
10498 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1
10500 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1
10502 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1
10504 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1
10506 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1
10508 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1
10510 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1
10513 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1
10514 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0
10515 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1
10517 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1
10519 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1
10521 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
10523 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1
10525 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10527 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1
10530 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1
10531 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0
10532 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10534 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1
10536 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10538 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10540 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10542 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
10544 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1
10547 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1
10548 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0
10549 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1
10551 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
10553 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
10555 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1
10557 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1
10559 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1
10561 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1
10564 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1
10565 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0
10566 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1
10568 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
10570 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
10572 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
10574 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
10576 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
10578 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
10581 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1
10582 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0
10583 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1
10585 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1
10587 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1
10589 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1
10591 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1
10593 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3
10646 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
10647 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
10648 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10650 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1
10652 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1
10654 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1
10656 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1
10658 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10661 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3
10662 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0
10663 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3
10665 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3
10667 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10670 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10671 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0
10672 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10674 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3
10676 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3
10679 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
10680 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
10681 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK 0x3
10683 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10685 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1
10687 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1
10689 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
10692 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10693 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0
10694 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10696 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10698 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1
10700 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1
10702 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
10704 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_MASK 0x1
10706 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10709 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10710 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
10711 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10713 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10715 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10717 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10719 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10721 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10723 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
10743 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10744 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10745 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10747 #define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10749 #define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10751 #define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10754 #define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3
10755 #define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0
10756 #define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3
10758 #define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3
10760 #define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3
10763 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10764 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10765 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10767 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10769 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1
10771 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1
10773 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1
10775 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1
10777 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10780 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10781 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0
10782 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10784 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10786 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10788 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1
10790 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1
10792 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1
10794 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1
10817 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10818 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10819 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10821 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10823 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10825 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10828 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10829 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10830 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10832 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10834 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10836 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10838 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10840 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10842 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1
10892 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1
10893 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0
10894 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1
10896 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3
10898 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3
10900 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3
10903 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1
10904 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0
10905 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1
10907 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1
10909 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1
10911 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1
10913 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1
10915 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1
10917 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1