Lines Matching refs:XAXIDMA_TX_CR_OFFSET
26 #define XAXIDMA_TX_CR_OFFSET 0x00 /* Channel control */ macro
358 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_hw_dma_bd_init()
368 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr); in nixge_hw_dma_bd_init()
385 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_hw_dma_bd_init()
386 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, in nixge_hw_dma_bd_init()
417 __nixge_device_reset(priv, XAXIDMA_TX_CR_OFFSET); in nixge_device_reset()
724 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_tx_irq()
728 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr); in nixge_tx_irq()
773 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_rx_irq()
777 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr); in nixge_rx_irq()
799 __nixge_device_reset(lp, XAXIDMA_TX_CR_OFFSET); in nixge_dma_err_handler()
836 cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET); in nixge_dma_err_handler()
846 nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET, cr); in nixge_dma_err_handler()
863 cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET); in nixge_dma_err_handler()
864 nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET, in nixge_dma_err_handler()
928 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_stop()
929 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, in nixge_stop()
1011 regval = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_ethtools_get_coalesce()