12 	u32 mask[3];  in sparx5_vlant_set_mask()  local
14 	/* Divide up mask in 32 bit words */  in sparx5_vlant_set_mask()
15 	bitmap_to_arr32(mask, sparx5->vlan_mask[vid], SPX5_PORTS);  in sparx5_vlant_set_mask()
17 	/* Output mask to respective registers */  in sparx5_vlant_set_mask()
18 	spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid));  in sparx5_vlant_set_mask()
19 	spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid));  in sparx5_vlant_set_mask()
20 	spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid));  in sparx5_vlant_set_mask()
121 	u32 val, mask;  in sparx5_pgid_update_mask()  local
123 	/* mask is spread across 3 registers x 32 bit */  in sparx5_pgid_update_mask()
125 		mask = BIT(port->portno);  in sparx5_pgid_update_mask()
126 		val = enable ? mask : 0;  in sparx5_pgid_update_mask()
127 		spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG(pgid));  in sparx5_pgid_update_mask()
129 		mask = BIT(port->portno - 32);  in sparx5_pgid_update_mask()
130 		val = enable ? mask : 0;  in sparx5_pgid_update_mask()
131 		spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG1(pgid));  in sparx5_pgid_update_mask()
133 		mask = BIT(port->portno - 64);  in sparx5_pgid_update_mask()
134 		val = enable ? mask : 0;  in sparx5_pgid_update_mask()
135 		spx5_rmw(val, mask, sparx5, ANA_AC_PGID_CFG2(pgid));  in sparx5_pgid_update_mask()
158 	u32 mask[3];  in sparx5_update_fwd()  local
161 	/* Divide up fwd mask in 32 bit words */  in sparx5_update_fwd()
162 	bitmap_to_arr32(mask, sparx5->bridge_fwd_mask, SPX5_PORTS);  in sparx5_update_fwd()
166 		spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port));  in sparx5_update_fwd()
167 		spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port));  in sparx5_update_fwd()
168 		spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port));  in sparx5_update_fwd()
177 			bitmap_to_arr32(mask, workmask, SPX5_PORTS);  in sparx5_update_fwd()
178 			spx5_wr(mask[0], sparx5, ANA_AC_SRC_CFG(port));  in sparx5_update_fwd()
179 			spx5_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port));  in sparx5_update_fwd()
180 			spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port));  in sparx5_update_fwd()
191 	bitmap_to_arr32(mask, workmask, SPX5_PORTS);  in sparx5_update_fwd()
193 	/* Apply learning mask */  in sparx5_update_fwd()
194 	spx5_wr(mask[0], sparx5, ANA_L2_AUTO_LRN_CFG);  in sparx5_update_fwd()
195 	spx5_wr(mask[1], sparx5, ANA_L2_AUTO_LRN_CFG1);  in sparx5_update_fwd()
196 	spx5_wr(mask[2], sparx5, ANA_L2_AUTO_LRN_CFG2);  in sparx5_update_fwd()