21 	TARGET_ANA_AC_POL = 4,
58 #define ANA_AC_RAM_INIT           __REG(TARGET_ANA_AC, 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4)
61 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\  argument
62 	FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
63 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\  argument
64 	FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x)
67 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
68 	FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
69 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
70 	FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
73 #define ANA_AC_OWN_UPSID(r)       __REG(TARGET_ANA_AC, 0, 1, 894472, 0, 1, 352, 52, r, 3, 4)
75 #define ANA_AC_OWN_UPSID_OWN_UPSID               GENMASK(4, 0)
76 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\  argument
77 	FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)
78 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\  argument
79 	FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x)
82 #define ANA_AC_SRC_CFG(g)         __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 0, 0, 1, 4)
85 #define ANA_AC_SRC_CFG1(g)        __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 4, 0, 1, 4)
88 #define ANA_AC_SRC_CFG2(g)        __REG(TARGET_ANA_AC, 0, 1, 849920, g, 102, 16, 8, 0, 1, 4)
91 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\  argument
92 	FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x)
93 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\  argument
94 	FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x)
97 #define ANA_AC_PGID_CFG(g)        __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4)
100 #define ANA_AC_PGID_CFG1(g)       __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4)
103 #define ANA_AC_PGID_CFG2(g)       __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4)
106 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\  argument
107 	FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x)
108 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\  argument
109 	FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x)
112 #define ANA_AC_PGID_MISC_CFG(g)   __REG(TARGET_ANA_AC, 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4)
114 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU         GENMASK(6, 4)
115 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\  argument
116 	FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
117 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\  argument
118 	FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
121 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\  argument
122 	FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
123 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\  argument
124 	FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
127 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\  argument
128 	FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
129 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\  argument
130 	FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
133 #define ANA_AC_PORT_SGE_CFG(r)    __REG(TARGET_ANA_AC, 0, 1, 851552, 0, 1, 20, 0, r, 4, 4)
136 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\  argument
137 	FIELD_PREP(ANA_AC_PORT_SGE_CFG_MASK, x)
138 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\  argument
139 	FIELD_GET(ANA_AC_PORT_SGE_CFG_MASK, x)
142 #define ANA_AC_STAT_RESET         __REG(TARGET_ANA_AC, 0, 1, 851552, 0, 1, 20, 16, 0, 1, 4)
145 #define ANA_AC_STAT_RESET_RESET_SET(x)\  argument
146 	FIELD_PREP(ANA_AC_STAT_RESET_RESET, x)
147 #define ANA_AC_STAT_RESET_RESET_GET(x)\  argument
148 	FIELD_GET(ANA_AC_STAT_RESET_RESET, x)
151 #define ANA_AC_PORT_STAT_CFG(g, r) __REG(TARGET_ANA_AC, 0, 1, 843776, g, 70, 64, 4, r, 4, 4)
153 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK       GENMASK(11, 4)
154 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\  argument
155 	FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
156 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\  argument
157 	FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
160 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\  argument
161 	FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
162 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\  argument
163 	FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
166 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\  argument
167 	FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
168 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\  argument
169 	FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
172 #define ANA_AC_PORT_STAT_LSB_CNT(g, r) __REG(TARGET_ANA_AC, 0, 1, 843776, g, 70, 64, 20, r, 4, 4)
175 #define ANA_ACL_OWN_UPSID(r)      __REG(TARGET_ANA_ACL, 0, 1, 32768, 0, 1, 592, 580, r, 3, 4)
177 #define ANA_ACL_OWN_UPSID_OWN_UPSID              GENMASK(4, 0)
178 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\  argument
179 	FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
180 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\  argument
181 	FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
184 #define ANA_AC_POL_POL_UPD_INT_CFG __REG(TARGET_ANA_AC_POL, 0, 1, 75968, 0, 1, 1160, 1148, 0, 1, 4)
187 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\  argument
188 	FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
189 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\  argument
190 	FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
193 #define ANA_AC_POL_BDLB_DLB_CTRL  __REG(TARGET_ANA_AC_POL, 0, 1, 79048, 0, 1, 8, 0, 0, 1, 4)
196 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\  argument
197 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
198 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\  argument
199 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
201 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT   GENMASK(18, 4)
202 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\  argument
203 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
204 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\  argument
205 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
208 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\  argument
209 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
210 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\  argument
211 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
214 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\  argument
215 	FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
216 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\  argument
217 	FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
220 #define ANA_AC_POL_SLB_DLB_CTRL   __REG(TARGET_ANA_AC_POL, 0, 1, 79056, 0, 1, 20, 0, 0, 1, 4)
223 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\  argument
224 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
225 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\  argument
226 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
228 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT    GENMASK(18, 4)
229 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\  argument
230 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
231 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\  argument
232 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
235 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\  argument
236 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
237 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\  argument
238 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
241 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\  argument
242 	FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
243 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\  argument
244 	FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
247 #define ANA_CL_FILTER_CTRL(g)     __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 4, 0, 1, 4)
250 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\  argument
251 	FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
252 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\  argument
253 	FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
256 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\  argument
257 	FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
258 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\  argument
259 	FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
262 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\  argument
263 	FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
264 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\  argument
265 	FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
268 #define ANA_CL_VLAN_FILTER_CTRL(g, r) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 8, r, 3, 4)
271 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\  argument
272 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
273 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\  argument
274 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
277 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\  argument
278 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
279 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\  argument
280 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
283 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\  argument
284 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
285 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\  argument
286 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
289 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\  argument
290 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
291 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\  argument
292 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
295 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\  argument
296 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
297 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\  argument
298 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
301 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\  argument
302 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
303 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\  argument
304 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
306 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS BIT(4)
307 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\  argument
308 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
309 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\  argument
310 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
313 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\  argument
314 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
315 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\  argument
316 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
319 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\  argument
320 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
321 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\  argument
322 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
325 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\  argument
326 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
327 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\  argument
328 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
331 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\  argument
332 	FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
333 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\  argument
334 	FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
337 #define ANA_CL_ETAG_FILTER_CTRL(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 20, 0, 1, 4)
340 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\  argument
341 	FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
342 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\  argument
343 	FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
346 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\  argument
347 	FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
348 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\  argument
349 	FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
352 #define ANA_CL_VLAN_CTRL(g)       __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 32, 0, 1, 4)
355 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\  argument
356 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
357 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\  argument
358 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
361 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\  argument
362 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
363 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\  argument
364 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
367 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\  argument
368 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
369 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\  argument
370 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
373 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\  argument
374 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
375 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\  argument
376 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
379 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\  argument
380 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
381 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\  argument
382 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
385 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\  argument
386 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
387 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\  argument
388 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
391 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\  argument
392 	FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
393 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\  argument
394 	FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
397 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\  argument
398 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
399 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\  argument
400 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
403 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\  argument
404 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x)
405 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\  argument
406 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x)
409 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\  argument
410 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x)
411 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\  argument
412 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x)
415 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\  argument
416 	FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x)
417 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\  argument
418 	FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x)
421 #define ANA_CL_VLAN_CTRL_2(g)     __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 36, 0, 1, 4)
424 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\  argument
425 	FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
426 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\  argument
427 	FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
430 #define ANA_CL_CAPTURE_BPDU_CFG(g) __REG(TARGET_ANA_CL, 0, 1, 131072, g, 70, 512, 196, 0, 1, 4)
433 #define ANA_CL_OWN_UPSID(r)       __REG(TARGET_ANA_CL, 0, 1, 166912, 0, 1, 756, 0, r, 3, 4)
435 #define ANA_CL_OWN_UPSID_OWN_UPSID               GENMASK(4, 0)
436 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\  argument
437 	FIELD_PREP(ANA_CL_OWN_UPSID_OWN_UPSID, x)
438 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\  argument
439 	FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x)
442 #define ANA_L2_AUTO_LRN_CFG       __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 24, 0, 1, 4)
445 #define ANA_L2_AUTO_LRN_CFG1      __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 28, 0, 1, 4)
448 #define ANA_L2_AUTO_LRN_CFG2      __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 32, 0, 1, 4)
451 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\  argument
452 	FIELD_PREP(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
453 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\  argument
454 	FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
457 #define ANA_L2_OWN_UPSID(r)       __REG(TARGET_ANA_L2, 0, 1, 566024, 0, 1, 700, 672, r, 3, 4)
459 #define ANA_L2_OWN_UPSID_OWN_UPSID               GENMASK(4, 0)
460 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\  argument
461 	FIELD_PREP(ANA_L2_OWN_UPSID_OWN_UPSID, x)
462 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\  argument
463 	FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x)
466 #define ANA_L3_VLAN_CTRL          __REG(TARGET_ANA_L3, 0, 1, 493632, 0, 1, 184, 4, 0, 1, 4)
469 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\  argument
470 	FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
471 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\  argument
472 	FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
475 #define ANA_L3_VLAN_CFG(g)        __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 8, 0, 1, 4)
478 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\  argument
479 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
480 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\  argument
481 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
484 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\  argument
485 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x)
486 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\  argument
487 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x)
490 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\  argument
491 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
492 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\  argument
493 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
496 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\  argument
497 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
498 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\  argument
499 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
501 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS           BIT(4)
502 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\  argument
503 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
504 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\  argument
505 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
508 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\  argument
509 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
510 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\  argument
511 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
514 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\  argument
515 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
516 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\  argument
517 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
520 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\  argument
521 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
522 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\  argument
523 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
526 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\  argument
527 	FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
528 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\  argument
529 	FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
532 #define ANA_L3_VLAN_MASK_CFG(g)   __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 16, 0, 1, 4)
535 #define ANA_L3_VLAN_MASK_CFG1(g)  __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 20, 0, 1, 4)
538 #define ANA_L3_VLAN_MASK_CFG2(g)  __REG(TARGET_ANA_L3, 0, 1, 0, g, 5120, 64, 24, 0, 1, 4)
541 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\  argument
542 	FIELD_PREP(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
543 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\  argument
544 	FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
547 #define ASM_RX_IN_BYTES_CNT(g)    __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 0, 0, 1, 4)
550 #define ASM_RX_SYMBOL_ERR_CNT(g)  __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 4, 0, 1, 4)
553 #define ASM_RX_PAUSE_CNT(g)       __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 8, 0, 1, 4)
556 #define ASM_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 12, 0, 1, 4)
559 #define ASM_RX_OK_BYTES_CNT(g)    __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 16, 0, 1, 4)
562 #define ASM_RX_BAD_BYTES_CNT(g)   __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 20, 0, 1, 4)
565 #define ASM_RX_UC_CNT(g)          __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 24, 0, 1, 4)
568 #define ASM_RX_MC_CNT(g)          __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 28, 0, 1, 4)
571 #define ASM_RX_BC_CNT(g)          __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 32, 0, 1, 4)
574 #define ASM_RX_CRC_ERR_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 36, 0, 1, 4)
577 #define ASM_RX_UNDERSIZE_CNT(g)   __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 40, 0, 1, 4)
580 #define ASM_RX_FRAGMENTS_CNT(g)   __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 44, 0, 1, 4)
583 #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 48, 0, 1, 4)
586 #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 52, 0, 1, 4)
589 #define ASM_RX_OVERSIZE_CNT(g)    __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 56, 0, 1, 4)
592 #define ASM_RX_JABBERS_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 60, 0, 1, 4)
595 #define ASM_RX_SIZE64_CNT(g)      __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 64, 0, 1, 4)
598 #define ASM_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 68, 0, 1, 4)
601 #define ASM_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 72, 0, 1, 4)
604 #define ASM_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 76, 0, 1, 4)
607 #define ASM_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 80, 0, 1, 4)
610 #define ASM_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 84, 0, 1, 4)
613 #define ASM_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 88, 0, 1, 4)
616 #define ASM_RX_IPG_SHRINK_CNT(g)  __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 92, 0, 1, 4)
619 #define ASM_TX_OUT_BYTES_CNT(g)   __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 96, 0, 1, 4)
622 #define ASM_TX_PAUSE_CNT(g)       __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 100, 0, 1, 4)
625 #define ASM_TX_OK_BYTES_CNT(g)    __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 104, 0, 1, 4)
628 #define ASM_TX_UC_CNT(g)          __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 108, 0, 1, 4)
631 #define ASM_TX_MC_CNT(g)          __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 112, 0, 1, 4)
634 #define ASM_TX_BC_CNT(g)          __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 116, 0, 1, 4)
637 #define ASM_TX_SIZE64_CNT(g)      __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 120, 0, 1, 4)
640 #define ASM_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 124, 0, 1, 4)
643 #define ASM_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 128, 0, 1, 4)
646 #define ASM_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 132, 0, 1, 4)
649 #define ASM_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 136, 0, 1, 4)
652 #define ASM_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 140, 0, 1, 4)
655 #define ASM_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 144, 0, 1, 4)
658 #define ASM_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 148, 0, 1, 4)
661 #define ASM_RX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 152, 0, 1, 4)
664 #define ASM_RX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 156, 0, 1, 4)
667 #define ASM_TX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 160, 0, 1, 4)
670 #define ASM_TX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 164, 0, 1, 4)
673 #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 168, 0, 1, 4)
676 #define ASM_PMAC_RX_PAUSE_CNT(g)  __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 172, 0, 1, 4)
679 #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 176, 0, 1, 4)
682 #define ASM_PMAC_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 180, 0, 1, 4)
685 #define ASM_PMAC_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 184, 0, 1, 4)
688 #define ASM_PMAC_RX_UC_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 188, 0, 1, 4)
691 #define ASM_PMAC_RX_MC_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 192, 0, 1, 4)
694 #define ASM_PMAC_RX_BC_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 196, 0, 1, 4)
697 #define ASM_PMAC_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 200, 0, 1, 4)
700 #define ASM_PMAC_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 204, 0, 1, 4)
703 #define ASM_PMAC_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 208, 0, 1, 4)
706 #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 212, 0, 1, 4)
709 #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 216, 0, 1, 4)
712 #define ASM_PMAC_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 220, 0, 1, 4)
715 #define ASM_PMAC_RX_JABBERS_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 224, 0, 1, 4)
718 #define ASM_PMAC_RX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 228, 0, 1, 4)
721 #define ASM_PMAC_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 232, 0, 1, 4)
724 #define ASM_PMAC_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 236, 0, 1, 4)
727 #define ASM_PMAC_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 240, 0, 1, 4)
730 #define ASM_PMAC_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 244, 0, 1, 4)
733 #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 248, 0, 1, 4)
736 #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 252, 0, 1, 4)
739 #define ASM_PMAC_TX_PAUSE_CNT(g)  __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 256, 0, 1, 4)
742 #define ASM_PMAC_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 260, 0, 1, 4)
745 #define ASM_PMAC_TX_UC_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 264, 0, 1, 4)
748 #define ASM_PMAC_TX_MC_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 268, 0, 1, 4)
751 #define ASM_PMAC_TX_BC_CNT(g)     __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 272, 0, 1, 4)
754 #define ASM_PMAC_TX_SIZE64_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 276, 0, 1, 4)
757 #define ASM_PMAC_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 280, 0, 1, 4)
760 #define ASM_PMAC_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 284, 0, 1, 4)
763 #define ASM_PMAC_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 288, 0, 1, 4)
766 #define ASM_PMAC_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 292, 0, 1, 4)
769 #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 296, 0, 1, 4)
772 #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 300, 0, 1, 4)
775 #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 304, 0, 1, 4)
778 #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 308, 0, 1, 4)
781 #define ASM_MM_RX_SMD_ERR_CNT(g)  __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 312, 0, 1, 4)
784 #define ASM_MM_RX_ASSEMBLY_OK_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 316, 0, 1, 4)
787 #define ASM_MM_RX_MERGE_FRAG_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 320, 0, 1, 4)
790 #define ASM_MM_TX_PFRAGMENT_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 324, 0, 1, 4)
793 #define ASM_TX_MULTI_COLL_CNT(g)  __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 328, 0, 1, 4)
796 #define ASM_TX_LATE_COLL_CNT(g)   __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 332, 0, 1, 4)
799 #define ASM_TX_XCOLL_CNT(g)       __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 336, 0, 1, 4)
802 #define ASM_TX_DEFER_CNT(g)       __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 340, 0, 1, 4)
805 #define ASM_TX_XDEFER_CNT(g)      __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 344, 0, 1, 4)
808 #define ASM_TX_BACKOFF1_CNT(g)    __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 348, 0, 1, 4)
811 #define ASM_TX_CSENSE_CNT(g)      __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 352, 0, 1, 4)
814 #define ASM_RX_IN_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 356, 0, 1, 4)
817 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\  argument
818 	FIELD_PREP(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
819 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\  argument
820 	FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
823 #define ASM_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 360, 0, 1, 4)
826 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
827 	FIELD_PREP(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
828 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
829 	FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
832 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 364, 0, 1, 4)
835 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
836 	FIELD_PREP(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
837 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
838 	FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
841 #define ASM_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 368, 0, 1, 4)
844 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
845 	FIELD_PREP(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
846 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
847 	FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
850 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 372, 0, 1, 4)
853 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
854 	FIELD_PREP(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
855 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
856 	FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
859 #define ASM_TX_OUT_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 376, 0, 1, 4)
862 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\  argument
863 	FIELD_PREP(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
864 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\  argument
865 	FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
868 #define ASM_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 380, 0, 1, 4)
871 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
872 	FIELD_PREP(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
873 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
874 	FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
877 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 384, 0, 1, 4)
880 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
881 	FIELD_PREP(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
882 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
883 	FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
886 #define ASM_RX_SYNC_LOST_ERR_CNT(g) __REG(TARGET_ASM, 0, 1, 0, g, 65, 512, 388, 0, 1, 4)
889 #define ASM_STAT_CFG              __REG(TARGET_ASM, 0, 1, 33280, 0, 1, 1088, 0, 0, 1, 4)
892 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\  argument
893 	FIELD_PREP(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
894 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\  argument
895 	FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
898 #define ASM_PORT_CFG(r)           __REG(TARGET_ASM, 0, 1, 33280, 0, 1, 1088, 540, r, 67, 4)
901 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\  argument
902 	FIELD_PREP(ASM_PORT_CFG_CSC_STAT_DIS, x)
903 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\  argument
904 	FIELD_GET(ASM_PORT_CFG_CSC_STAT_DIS, x)
907 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\  argument
908 	FIELD_PREP(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
909 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\  argument
910 	FIELD_GET(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
913 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\  argument
914 	FIELD_PREP(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
915 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\  argument
916 	FIELD_GET(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
919 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\  argument
920 	FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
921 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\  argument
922 	FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
925 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\  argument
926 	FIELD_PREP(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
927 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\  argument
928 	FIELD_GET(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
931 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\  argument
932 	FIELD_PREP(ASM_PORT_CFG_FRM_AGING_DIS, x)
933 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\  argument
934 	FIELD_GET(ASM_PORT_CFG_FRM_AGING_DIS, x)
937 #define ASM_PORT_CFG_PAD_ENA_SET(x)\  argument
938 	FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x)
939 #define ASM_PORT_CFG_PAD_ENA_GET(x)\  argument
940 	FIELD_GET(ASM_PORT_CFG_PAD_ENA, x)
942 #define ASM_PORT_CFG_INJ_DISCARD_CFG             GENMASK(5, 4)
943 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\  argument
944 	FIELD_PREP(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
945 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\  argument
946 	FIELD_GET(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
949 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\  argument
950 	FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
951 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\  argument
952 	FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
955 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\  argument
956 	FIELD_PREP(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
957 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\  argument
958 	FIELD_GET(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
961 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\  argument
962 	FIELD_PREP(ASM_PORT_CFG_PFRM_FLUSH, x)
963 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\  argument
964 	FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x)
967 #define ASM_RAM_INIT              __REG(TARGET_ASM, 0, 1, 34832, 0, 1, 4, 0, 0, 1, 4)
970 #define ASM_RAM_INIT_RAM_INIT_SET(x)\  argument
971 	FIELD_PREP(ASM_RAM_INIT_RAM_INIT, x)
972 #define ASM_RAM_INIT_RAM_INIT_GET(x)\  argument
973 	FIELD_GET(ASM_RAM_INIT_RAM_INIT, x)
976 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
977 	FIELD_PREP(ASM_RAM_INIT_RAM_CFG_HOOK, x)
978 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
979 	FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x)
982 #define CLKGEN_LCPLL1_CORE_CLK_CFG __REG(TARGET_CLKGEN, 0, 1, 12, 0, 1, 36, 0, 0, 1, 4)
985 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\  argument
986 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
987 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\  argument
988 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
991 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\  argument
992 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
993 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\  argument
994 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
997 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\  argument
998 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
999 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\  argument
1000 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
1003 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\  argument
1004 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
1005 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\  argument
1006 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
1009 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\  argument
1010 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
1011 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\  argument
1012 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
1015 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\  argument
1016 	FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
1017 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\  argument
1018 	FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
1021 #define CPU_PROC_CTRL             __REG(TARGET_CPU, 0, 1, 0, 0, 1, 204, 176, 0, 1, 4)
1024 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\  argument
1025 	FIELD_PREP(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
1026 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\  argument
1027 	FIELD_GET(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
1030 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\  argument
1031 	FIELD_PREP(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
1032 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\  argument
1033 	FIELD_GET(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
1036 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\  argument
1037 	FIELD_PREP(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
1038 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\  argument
1039 	FIELD_GET(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
1042 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\  argument
1043 	FIELD_PREP(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
1044 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\  argument
1045 	FIELD_GET(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
1048 #define CPU_PROC_CTRL_VINITHI_SET(x)\  argument
1049 	FIELD_PREP(CPU_PROC_CTRL_VINITHI, x)
1050 #define CPU_PROC_CTRL_VINITHI_GET(x)\  argument
1051 	FIELD_GET(CPU_PROC_CTRL_VINITHI, x)
1054 #define CPU_PROC_CTRL_CFGTE_SET(x)\  argument
1055 	FIELD_PREP(CPU_PROC_CTRL_CFGTE, x)
1056 #define CPU_PROC_CTRL_CFGTE_GET(x)\  argument
1057 	FIELD_GET(CPU_PROC_CTRL_CFGTE, x)
1060 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\  argument
1061 	FIELD_PREP(CPU_PROC_CTRL_CP15S_DISABLE, x)
1062 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\  argument
1063 	FIELD_GET(CPU_PROC_CTRL_CP15S_DISABLE, x)
1066 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\  argument
1067 	FIELD_PREP(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
1068 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\  argument
1069 	FIELD_GET(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
1071 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA        BIT(4)
1072 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\  argument
1073 	FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
1074 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\  argument
1075 	FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
1078 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\  argument
1079 	FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x)
1080 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\  argument
1081 	FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x)
1084 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\  argument
1085 	FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x)
1086 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\  argument
1087 	FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x)
1090 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\  argument
1091 	FIELD_PREP(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
1092 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\  argument
1093 	FIELD_GET(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
1096 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\  argument
1097 	FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x)
1098 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\  argument
1099 	FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x)
1102 #define DEV10G_MAC_ENA_CFG(t)     __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 0, 0, 1, 4)
1104 #define DEV10G_MAC_ENA_CFG_RX_ENA                BIT(4)
1105 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
1106 	FIELD_PREP(DEV10G_MAC_ENA_CFG_RX_ENA, x)
1107 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
1108 	FIELD_GET(DEV10G_MAC_ENA_CFG_RX_ENA, x)
1111 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
1112 	FIELD_PREP(DEV10G_MAC_ENA_CFG_TX_ENA, x)
1113 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
1114 	FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x)
1117 #define DEV10G_MAC_MAXLEN_CFG(t)  __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 8, 0, 1, 4)
1120 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
1121 	FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1122 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
1123 	FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1126 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
1127 	FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
1128 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
1129 	FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
1132 #define DEV10G_MAC_NUM_TAGS_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 12, 0, 1, 4)
1135 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\  argument
1136 	FIELD_PREP(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
1137 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\  argument
1138 	FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
1141 #define DEV10G_MAC_TAGS_CFG(t, r) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 16, r, 3, 4)
1144 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\  argument
1145 	FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
1146 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\  argument
1147 	FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
1149 #define DEV10G_MAC_TAGS_CFG_TAG_ENA              BIT(4)
1150 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\  argument
1151 	FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
1152 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\  argument
1153 	FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
1156 #define DEV10G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 28, 0, 1, 4)
1159 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
1160 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1161 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
1162 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1165 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
1166 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1167 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
1168 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1171 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
1172 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1173 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
1174 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1177 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
1178 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1179 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
1180 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1183 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
1184 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1185 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
1186 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1188 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA       BIT(4)
1189 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
1190 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1191 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
1192 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1195 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
1196 	FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1197 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
1198 	FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1201 #define DEV10G_MAC_TX_MONITOR_STICKY(t) __REG(TARGET_DEV10G, t, 12, 0, 0, 1, 60, 48, 0, 1, 4)
1203 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY BIT(4)
1204 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\  argument
1205 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
1206 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\  argument
1207 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
1210 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\  argument
1211 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
1212 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\  argument
1213 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
1216 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\  argument
1217 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
1218 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\  argument
1219 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
1222 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\  argument
1223 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
1224 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\  argument
1225 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
1228 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\  argument
1229 	FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
1230 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\  argument
1231 	FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
1234 #define DEV10G_DEV_RST_CTRL(t)    __REG(TARGET_DEV10G, t, 12, 436, 0, 1, 52, 0, 0, 1, 4)
1237 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
1238 	FIELD_PREP(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1239 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
1240 	FIELD_GET(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1243 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
1244 	FIELD_PREP(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1245 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
1246 	FIELD_GET(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1249 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
1250 	FIELD_PREP(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1251 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
1252 	FIELD_GET(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1255 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
1256 	FIELD_PREP(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1257 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
1258 	FIELD_GET(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1261 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
1262 	FIELD_PREP(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
1263 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
1264 	FIELD_GET(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
1267 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
1268 	FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
1269 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
1270 	FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
1273 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
1274 	FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
1275 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
1276 	FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
1278 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST           BIT(4)
1279 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
1280 	FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
1281 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
1282 	FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
1285 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
1286 	FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
1287 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
1288 	FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
1291 #define DEV10G_PCS25G_CFG(t)      __REG(TARGET_DEV10G, t, 12, 488, 0, 1, 32, 0, 0, 1, 4)
1294 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\  argument
1295 	FIELD_PREP(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
1296 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\  argument
1297 	FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
1300 #define DEV25G_MAC_ENA_CFG(t)     __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 0, 0, 1, 4)
1302 #define DEV25G_MAC_ENA_CFG_RX_ENA                BIT(4)
1303 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
1304 	FIELD_PREP(DEV25G_MAC_ENA_CFG_RX_ENA, x)
1305 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
1306 	FIELD_GET(DEV25G_MAC_ENA_CFG_RX_ENA, x)
1309 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
1310 	FIELD_PREP(DEV25G_MAC_ENA_CFG_TX_ENA, x)
1311 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
1312 	FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x)
1315 #define DEV25G_MAC_MAXLEN_CFG(t)  __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 8, 0, 1, 4)
1318 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
1319 	FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1320 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
1321 	FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
1324 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
1325 	FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
1326 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
1327 	FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
1330 #define DEV25G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 28, 0, 1, 4)
1333 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
1334 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1335 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
1336 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
1339 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
1340 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1341 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
1342 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
1345 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
1346 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1347 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
1348 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
1351 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
1352 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1353 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
1354 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
1357 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
1358 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1359 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
1360 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
1362 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA       BIT(4)
1363 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
1364 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1365 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
1366 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
1369 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
1370 	FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1371 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
1372 	FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
1375 #define DEV25G_DEV_RST_CTRL(t)    __REG(TARGET_DEV25G, t, 8, 436, 0, 1, 52, 0, 0, 1, 4)
1378 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
1379 	FIELD_PREP(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1380 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
1381 	FIELD_GET(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
1384 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
1385 	FIELD_PREP(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1386 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
1387 	FIELD_GET(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1390 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
1391 	FIELD_PREP(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1392 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
1393 	FIELD_GET(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
1396 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
1397 	FIELD_PREP(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1398 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
1399 	FIELD_GET(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
1402 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
1403 	FIELD_PREP(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
1404 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
1405 	FIELD_GET(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
1408 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
1409 	FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
1410 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
1411 	FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
1414 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
1415 	FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
1416 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
1417 	FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
1419 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST           BIT(4)
1420 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
1421 	FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
1422 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
1423 	FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
1426 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
1427 	FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
1428 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
1429 	FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
1432 #define DEV25G_PCS25G_CFG(t)      __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 0, 0, 1, 4)
1435 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\  argument
1436 	FIELD_PREP(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
1437 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\  argument
1438 	FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
1441 #define DEV25G_PCS25G_SD_CFG(t)   __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 4, 0, 1, 4)
1444 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\  argument
1445 	FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
1446 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\  argument
1447 	FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
1449 #define DEV25G_PCS25G_SD_CFG_SD_POL              BIT(4)
1450 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\  argument
1451 	FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_POL, x)
1452 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\  argument
1453 	FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_POL, x)
1456 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\  argument
1457 	FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
1458 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\  argument
1459 	FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
1462 #define DEV2G5_DEV_RST_CTRL(t)    __REG(TARGET_DEV2G5, t, 65, 0, 0, 1, 36, 0, 0, 1, 4)
1465 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
1466 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1467 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
1468 	FIELD_GET(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
1471 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
1472 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
1473 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
1474 	FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
1477 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\  argument
1478 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
1479 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\  argument
1480 	FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
1483 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\  argument
1484 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
1485 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\  argument
1486 	FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
1489 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
1490 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
1491 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
1492 	FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
1495 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
1496 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
1497 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
1498 	FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
1500 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST           BIT(4)
1501 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
1502 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
1503 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
1504 	FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
1507 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
1508 	FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
1509 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
1510 	FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
1513 #define DEV2G5_MAC_ENA_CFG(t)     __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 0, 0, 1, 4)
1515 #define DEV2G5_MAC_ENA_CFG_RX_ENA                BIT(4)
1516 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
1517 	FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
1518 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
1519 	FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
1522 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
1523 	FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
1524 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
1525 	FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
1528 #define DEV2G5_MAC_MODE_CFG(t)    __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 4, 0, 1, 4)
1531 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\  argument
1532 	FIELD_PREP(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
1533 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\  argument
1534 	FIELD_GET(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
1536 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA        BIT(4)
1537 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\  argument
1538 	FIELD_PREP(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
1539 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\  argument
1540 	FIELD_GET(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
1543 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\  argument
1544 	FIELD_PREP(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
1545 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\  argument
1546 	FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
1549 #define DEV2G5_MAC_MAXLEN_CFG(t)  __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 8, 0, 1, 4)
1552 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
1553 	FIELD_PREP(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
1554 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
1555 	FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
1558 #define DEV2G5_MAC_TAGS_CFG(t)    __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 12, 0, 1, 4)
1561 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\  argument
1562 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
1563 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\  argument
1564 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
1567 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\  argument
1568 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
1569 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\  argument
1570 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
1573 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\  argument
1574 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
1575 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\  argument
1576 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
1579 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\  argument
1580 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
1581 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\  argument
1582 	FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
1585 #define DEV2G5_MAC_TAGS_CFG2(t)   __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 16, 0, 1, 4)
1588 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\  argument
1589 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
1590 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\  argument
1591 	FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
1594 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\  argument
1595 	FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
1596 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\  argument
1597 	FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
1600 #define DEV2G5_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 20, 0, 1, 4)
1603 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\  argument
1604 	FIELD_PREP(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
1605 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\  argument
1606 	FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
1609 #define DEV2G5_MAC_IFG_CFG(t)     __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 24, 0, 1, 4)
1612 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\  argument
1613 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
1614 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\  argument
1615 	FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
1618 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\  argument
1619 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
1620 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\  argument
1621 	FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
1623 #define DEV2G5_MAC_IFG_CFG_RX_IFG2               GENMASK(7, 4)
1624 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\  argument
1625 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
1626 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\  argument
1627 	FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
1630 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\  argument
1631 	FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
1632 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\  argument
1633 	FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
1636 #define DEV2G5_MAC_HDX_CFG(t)     __REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 28, 0, 1, 4)
1639 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\  argument
1640 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
1641 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\  argument
1642 	FIELD_GET(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
1645 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\  argument
1646 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED, x)
1647 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\  argument
1648 	FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED, x)
1651 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\  argument
1652 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
1653 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\  argument
1654 	FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
1657 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\  argument
1658 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
1659 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\  argument
1660 	FIELD_GET(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
1663 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\  argument
1664 	FIELD_PREP(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
1665 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\  argument
1666 	FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
1669 #define DEV2G5_PCS1G_CFG(t)       __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 0, 0, 1, 4)
1671 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE        BIT(4)
1672 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\  argument
1673 	FIELD_PREP(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
1674 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\  argument
1675 	FIELD_GET(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
1678 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
1679 	FIELD_PREP(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
1680 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
1681 	FIELD_GET(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
1684 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\  argument
1685 	FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x)
1686 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\  argument
1687 	FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x)
1690 #define DEV2G5_PCS1G_MODE_CFG(t)  __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 4, 0, 1, 4)
1692 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA    BIT(4)
1693 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\  argument
1694 	FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
1695 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\  argument
1696 	FIELD_GET(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
1699 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\  argument
1700 	FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
1701 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\  argument
1702 	FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
1705 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\  argument
1706 	FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
1707 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\  argument
1708 	FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
1711 #define DEV2G5_PCS1G_SD_CFG(t)    __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 8, 0, 1, 4)
1714 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\  argument
1715 	FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
1716 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\  argument
1717 	FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
1719 #define DEV2G5_PCS1G_SD_CFG_SD_POL               BIT(4)
1720 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\  argument
1721 	FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
1722 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\  argument
1723 	FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
1726 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\  argument
1727 	FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
1728 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\  argument
1729 	FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
1732 #define DEV2G5_PCS1G_ANEG_CFG(t)  __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 12, 0, 1, 4)
1735 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\  argument
1736 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
1737 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\  argument
1738 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
1741 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\  argument
1742 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
1743 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\  argument
1744 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
1747 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\  argument
1748 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
1749 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\  argument
1750 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
1753 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\  argument
1754 	FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
1755 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\  argument
1756 	FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
1759 #define DEV2G5_PCS1G_LB_CFG(t)    __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 20, 0, 1, 4)
1761 #define DEV2G5_PCS1G_LB_CFG_RA_ENA               BIT(4)
1762 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\  argument
1763 	FIELD_PREP(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
1764 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\  argument
1765 	FIELD_GET(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
1768 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\  argument
1769 	FIELD_PREP(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
1770 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\  argument
1771 	FIELD_GET(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
1774 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\  argument
1775 	FIELD_PREP(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
1776 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\  argument
1777 	FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
1780 #define DEV2G5_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 32, 0, 1, 4)
1783 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\  argument
1784 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
1785 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\  argument
1786 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
1788 #define DEV2G5_PCS1G_ANEG_STATUS_PR              BIT(4)
1789 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\  argument
1790 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
1791 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\  argument
1792 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
1795 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\  argument
1796 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
1797 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\  argument
1798 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
1801 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\  argument
1802 	FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
1803 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\  argument
1804 	FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
1807 #define DEV2G5_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 40, 0, 1, 4)
1810 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\  argument
1811 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
1812 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\  argument
1813 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
1816 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\  argument
1817 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
1818 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\  argument
1819 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
1821 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS     BIT(4)
1822 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\  argument
1823 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
1824 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\  argument
1825 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
1828 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\  argument
1829 	FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
1830 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\  argument
1831 	FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
1834 #define DEV2G5_PCS1G_STICKY(t)    __REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 48, 0, 1, 4)
1836 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY     BIT(4)
1837 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\  argument
1838 	FIELD_PREP(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
1839 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\  argument
1840 	FIELD_GET(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
1843 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\  argument
1844 	FIELD_PREP(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
1845 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\  argument
1846 	FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
1849 #define DEV2G5_PCS_FX100_CFG(t)   __REG(TARGET_DEV2G5, t, 65, 164, 0, 1, 4, 0, 0, 1, 4)
1852 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\  argument
1853 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
1854 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\  argument
1855 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
1858 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\  argument
1859 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_POL, x)
1860 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\  argument
1861 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_POL, x)
1864 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\  argument
1865 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
1866 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\  argument
1867 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
1870 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\  argument
1871 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
1872 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\  argument
1873 	FIELD_GET(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
1876 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\  argument
1877 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
1878 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\  argument
1879 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
1882 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\  argument
1883 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
1884 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\  argument
1885 	FIELD_GET(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
1888 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\  argument
1889 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
1890 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\  argument
1891 	FIELD_GET(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
1894 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\  argument
1895 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
1896 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\  argument
1897 	FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
1899 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER       GENMASK(7, 4)
1900 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\  argument
1901 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
1902 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\  argument
1903 	FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
1906 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\  argument
1907 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
1908 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\  argument
1909 	FIELD_GET(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
1912 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\  argument
1913 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
1914 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\  argument
1915 	FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
1918 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\  argument
1919 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
1920 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\  argument
1921 	FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
1924 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\  argument
1925 	FIELD_PREP(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
1926 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\  argument
1927 	FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
1930 #define DEV2G5_PCS_FX100_STATUS(t) __REG(TARGET_DEV2G5, t, 65, 168, 0, 1, 4, 0, 0, 1, 4)
1933 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\  argument
1934 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
1935 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\  argument
1936 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
1939 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\  argument
1940 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
1941 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\  argument
1942 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
1945 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\  argument
1946 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
1947 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\  argument
1948 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
1951 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\  argument
1952 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
1953 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\  argument
1954 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
1956 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4)
1957 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\  argument
1958 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
1959 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\  argument
1960 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
1963 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\  argument
1964 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
1965 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\  argument
1966 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
1969 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\  argument
1970 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
1971 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\  argument
1972 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
1975 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\  argument
1976 	FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
1977 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\  argument
1978 	FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
1981 #define DEV5G_MAC_ENA_CFG(t)      __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 0, 0, 1, 4)
1983 #define DEV5G_MAC_ENA_CFG_RX_ENA                 BIT(4)
1984 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
1985 	FIELD_PREP(DEV5G_MAC_ENA_CFG_RX_ENA, x)
1986 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
1987 	FIELD_GET(DEV5G_MAC_ENA_CFG_RX_ENA, x)
1990 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
1991 	FIELD_PREP(DEV5G_MAC_ENA_CFG_TX_ENA, x)
1992 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
1993 	FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x)
1996 #define DEV5G_MAC_MAXLEN_CFG(t)   __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 8, 0, 1, 4)
1999 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
2000 	FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2001 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
2002 	FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2005 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
2006 	FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
2007 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
2008 	FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
2011 #define DEV5G_MAC_ADV_CHK_CFG(t)  __REG(TARGET_DEV5G, t, 13, 0, 0, 1, 60, 28, 0, 1, 4)
2014 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
2015 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2016 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
2017 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2020 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
2021 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2022 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
2023 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2026 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
2027 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2028 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
2029 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2032 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
2033 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2034 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
2035 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2038 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
2039 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2040 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
2041 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2043 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA        BIT(4)
2044 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
2045 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2046 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
2047 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2050 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
2051 	FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2052 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
2053 	FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2056 #define DEV5G_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 0, 0, 1, 4)
2059 #define DEV5G_RX_PAUSE_CNT(t)     __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 4, 0, 1, 4)
2062 #define DEV5G_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 8, 0, 1, 4)
2065 #define DEV5G_RX_UC_CNT(t)        __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 12, 0, 1, 4)
2068 #define DEV5G_RX_MC_CNT(t)        __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 16, 0, 1, 4)
2071 #define DEV5G_RX_BC_CNT(t)        __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 20, 0, 1, 4)
2074 #define DEV5G_RX_CRC_ERR_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 24, 0, 1, 4)
2077 #define DEV5G_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 28, 0, 1, 4)
2080 #define DEV5G_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 32, 0, 1, 4)
2083 #define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 36, 0, 1, 4)
2086 #define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 40, 0, 1, 4)
2089 #define DEV5G_RX_OVERSIZE_CNT(t)  __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 44, 0, 1, 4)
2092 #define DEV5G_RX_JABBERS_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 48, 0, 1, 4)
2095 #define DEV5G_RX_SIZE64_CNT(t)    __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 52, 0, 1, 4)
2098 #define DEV5G_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 56, 0, 1, 4)
2101 #define DEV5G_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 60, 0, 1, 4)
2104 #define DEV5G_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 64, 0, 1, 4)
2107 #define DEV5G_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 68, 0, 1, 4)
2110 #define DEV5G_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 72, 0, 1, 4)
2113 #define DEV5G_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 76, 0, 1, 4)
2116 #define DEV5G_RX_IPG_SHRINK_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 80, 0, 1, 4)
2119 #define DEV5G_TX_PAUSE_CNT(t)     __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 84, 0, 1, 4)
2122 #define DEV5G_TX_UC_CNT(t)        __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 88, 0, 1, 4)
2125 #define DEV5G_TX_MC_CNT(t)        __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 92, 0, 1, 4)
2128 #define DEV5G_TX_BC_CNT(t)        __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 96, 0, 1, 4)
2131 #define DEV5G_TX_SIZE64_CNT(t)    __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 100, 0, 1, 4)
2134 #define DEV5G_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 104, 0, 1, 4)
2137 #define DEV5G_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 108, 0, 1, 4)
2140 #define DEV5G_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 112, 0, 1, 4)
2143 #define DEV5G_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 116, 0, 1, 4)
2146 #define DEV5G_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 120, 0, 1, 4)
2149 #define DEV5G_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 124, 0, 1, 4)
2152 #define DEV5G_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 128, 0, 1, 4)
2155 #define DEV5G_RX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 132, 0, 1, 4)
2158 #define DEV5G_RX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 136, 0, 1, 4)
2161 #define DEV5G_TX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 140, 0, 1, 4)
2164 #define DEV5G_TX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 144, 0, 1, 4)
2167 #define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 148, 0, 1, 4)
2170 #define DEV5G_PMAC_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 152, 0, 1, 4)
2173 #define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 156, 0, 1, 4)
2176 #define DEV5G_PMAC_RX_UC_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 160, 0, 1, 4)
2179 #define DEV5G_PMAC_RX_MC_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 164, 0, 1, 4)
2182 #define DEV5G_PMAC_RX_BC_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 168, 0, 1, 4)
2185 #define DEV5G_PMAC_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 172, 0, 1, 4)
2188 #define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 176, 0, 1, 4)
2191 #define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 180, 0, 1, 4)
2195 					t, 13, 60, 0, 1, 312, 184, 0, 1, 4)
2199 					t, 13, 60, 0, 1, 312, 188, 0, 1, 4)
2202 #define DEV5G_PMAC_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 192, 0, 1, 4)
2205 #define DEV5G_PMAC_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 196, 0, 1, 4)
2208 #define DEV5G_PMAC_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 200, 0, 1, 4)
2211 #define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 204, 0, 1, 4)
2214 #define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 208, 0, 1, 4)
2217 #define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 212, 0, 1, 4)
2220 #define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 216, 0, 1, 4)
2223 #define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 220, 0, 1, 4)
2226 #define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 224, 0, 1, 4)
2229 #define DEV5G_PMAC_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 228, 0, 1, 4)
2232 #define DEV5G_PMAC_TX_UC_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 232, 0, 1, 4)
2235 #define DEV5G_PMAC_TX_MC_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 236, 0, 1, 4)
2238 #define DEV5G_PMAC_TX_BC_CNT(t)   __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 240, 0, 1, 4)
2241 #define DEV5G_PMAC_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 244, 0, 1, 4)
2244 #define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 248, 0, 1, 4)
2247 #define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 252, 0, 1, 4)
2250 #define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 256, 0, 1, 4)
2253 #define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 260, 0, 1, 4)
2256 #define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 264, 0, 1, 4)
2259 #define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 268, 0, 1, 4)
2262 #define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 272, 0, 1, 4)
2265 #define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 276, 0, 1, 4)
2268 #define DEV5G_MM_RX_SMD_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 280, 0, 1, 4)
2271 #define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 284, 0, 1, 4)
2274 #define DEV5G_MM_RX_MERGE_FRAG_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 288, 0, 1, 4)
2277 #define DEV5G_MM_TX_PFRAGMENT_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 292, 0, 1, 4)
2280 #define DEV5G_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 296, 0, 1, 4)
2283 #define DEV5G_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 300, 0, 1, 4)
2286 #define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 304, 0, 1, 4)
2289 #define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G, t, 13, 60, 0, 1, 312, 308, 0, 1, 4)
2292 #define DEV5G_RX_IN_BYTES_CNT(t)  __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 0, 0, 1, 4)
2295 #define DEV5G_RX_IN_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 4, 0, 1, 4)
2298 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\  argument
2299 	FIELD_PREP(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2300 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\  argument
2301 	FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2304 #define DEV5G_RX_OK_BYTES_CNT(t)  __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 8, 0, 1, 4)
2307 #define DEV5G_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 12, 0, 1, 4)
2310 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
2311 	FIELD_PREP(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2312 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
2313 	FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2316 #define DEV5G_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 16, 0, 1, 4)
2319 #define DEV5G_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 20, 0, 1, 4)
2322 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
2323 	FIELD_PREP(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2324 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
2325 	FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2328 #define DEV5G_TX_OUT_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 24, 0, 1, 4)
2331 #define DEV5G_TX_OUT_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 28, 0, 1, 4)
2334 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\  argument
2335 	FIELD_PREP(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2336 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\  argument
2337 	FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2340 #define DEV5G_TX_OK_BYTES_CNT(t)  __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 32, 0, 1, 4)
2343 #define DEV5G_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 36, 0, 1, 4)
2346 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
2347 	FIELD_PREP(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2348 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
2349 	FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2352 #define DEV5G_PMAC_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 40, 0, 1, 4)
2355 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 44, 0, 1, 4)
2358 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
2359 	FIELD_PREP(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2360 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
2361 	FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2364 #define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 48, 0, 1, 4)
2367 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 52, 0, 1, 4)
2370 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
2371 	FIELD_PREP(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2372 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
2373 	FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2376 #define DEV5G_PMAC_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 56, 0, 1, 4)
2379 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G, t, 13, 372, 0, 1, 64, 60, 0, 1, 4)
2382 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
2383 	FIELD_PREP(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2384 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
2385 	FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2388 #define DEV5G_DEV_RST_CTRL(t)     __REG(TARGET_DEV5G, t, 13, 436, 0, 1, 52, 0, 0, 1, 4)
2391 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
2392 	FIELD_PREP(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2393 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
2394 	FIELD_GET(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2397 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
2398 	FIELD_PREP(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2399 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
2400 	FIELD_GET(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2403 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
2404 	FIELD_PREP(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2405 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
2406 	FIELD_GET(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2409 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
2410 	FIELD_PREP(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2411 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
2412 	FIELD_GET(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2415 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
2416 	FIELD_PREP(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
2417 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
2418 	FIELD_GET(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
2421 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
2422 	FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
2423 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
2424 	FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
2427 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
2428 	FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
2429 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
2430 	FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
2432 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST            BIT(4)
2433 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
2434 	FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
2435 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
2436 	FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
2439 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
2440 	FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
2441 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
2442 	FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
2445 #define DSM_RAM_INIT              __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4)
2448 #define DSM_RAM_INIT_RAM_INIT_SET(x)\  argument
2449 	FIELD_PREP(DSM_RAM_INIT_RAM_INIT, x)
2450 #define DSM_RAM_INIT_RAM_INIT_GET(x)\  argument
2451 	FIELD_GET(DSM_RAM_INIT_RAM_INIT, x)
2454 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
2455 	FIELD_PREP(DSM_RAM_INIT_RAM_CFG_HOOK, x)
2456 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
2457 	FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x)
2460 #define DSM_BUF_CFG(r)            __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 0, r, 67, 4)
2463 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\  argument
2464 	FIELD_PREP(DSM_BUF_CFG_CSC_STAT_DIS, x)
2465 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\  argument
2466 	FIELD_GET(DSM_BUF_CFG_CSC_STAT_DIS, x)
2469 #define DSM_BUF_CFG_AGING_ENA_SET(x)\  argument
2470 	FIELD_PREP(DSM_BUF_CFG_AGING_ENA, x)
2471 #define DSM_BUF_CFG_AGING_ENA_GET(x)\  argument
2472 	FIELD_GET(DSM_BUF_CFG_AGING_ENA, x)
2475 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\  argument
2476 	FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
2477 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\  argument
2478 	FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
2481 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\  argument
2482 	FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
2483 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\  argument
2484 	FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
2487 #define DSM_DEV_TX_STOP_WM_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r, 67, 4)
2490 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\  argument
2491 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
2492 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\  argument
2493 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
2496 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\  argument
2497 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
2498 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\  argument
2499 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
2502 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\  argument
2503 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
2504 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\  argument
2505 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
2508 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\  argument
2509 	FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
2510 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\  argument
2511 	FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
2514 #define DSM_RX_PAUSE_CFG(r)       __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1628, r, 67, 4)
2517 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\  argument
2518 	FIELD_PREP(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
2519 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\  argument
2520 	FIELD_GET(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
2523 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\  argument
2524 	FIELD_PREP(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
2525 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\  argument
2526 	FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
2529 #define DSM_MAC_CFG(r)            __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2432, r, 67, 4)
2532 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\  argument
2533 	FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_VAL, x)
2534 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\  argument
2535 	FIELD_GET(DSM_MAC_CFG_TX_PAUSE_VAL, x)
2538 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\  argument
2539 	FIELD_PREP(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
2540 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\  argument
2541 	FIELD_GET(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
2544 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\  argument
2545 	FIELD_PREP(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
2546 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\  argument
2547 	FIELD_GET(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
2550 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\  argument
2551 	FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
2552 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\  argument
2553 	FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
2556 #define DSM_MAC_ADDR_BASE_HIGH_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2700, r, 65, 4)
2559 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\  argument
2560 	FIELD_PREP(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
2561 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\  argument
2562 	FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
2565 #define DSM_MAC_ADDR_BASE_LOW_CFG(r) __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2960, r, 65, 4)
2568 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\  argument
2569 	FIELD_PREP(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
2570 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\  argument
2571 	FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
2574 #define DSM_TAXI_CAL_CFG(r)       __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 3224, r, 9, 4)
2577 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\  argument
2578 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x)
2579 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\  argument
2580 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x)
2583 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\  argument
2584 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
2585 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\  argument
2586 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
2589 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\  argument
2590 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
2591 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\  argument
2592 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
2594 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL             GENMASK(4, 1)
2595 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\  argument
2596 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
2597 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\  argument
2598 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
2601 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\  argument
2602 	FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
2603 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\  argument
2604 	FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
2607 #define EACL_POL_EACL_CFG         __REG(TARGET_EACL, 0, 1, 150608, 0, 1, 780, 768, 0, 1, 4)
2610 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\  argument
2611 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
2612 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\  argument
2613 	FIELD_GET(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
2615 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY     BIT(4)
2616 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\  argument
2617 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
2618 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\  argument
2619 	FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
2622 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\  argument
2623 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
2624 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\  argument
2625 	FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
2628 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\  argument
2629 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
2630 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\  argument
2631 	FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
2634 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\  argument
2635 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
2636 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\  argument
2637 	FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
2640 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\  argument
2641 	FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
2642 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\  argument
2643 	FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
2646 #define EACL_RAM_INIT             __REG(TARGET_EACL, 0, 1, 118736, 0, 1, 4, 0, 0, 1, 4)
2649 #define EACL_RAM_INIT_RAM_INIT_SET(x)\  argument
2650 	FIELD_PREP(EACL_RAM_INIT_RAM_INIT, x)
2651 #define EACL_RAM_INIT_RAM_INIT_GET(x)\  argument
2652 	FIELD_GET(EACL_RAM_INIT_RAM_INIT, x)
2655 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
2656 	FIELD_PREP(EACL_RAM_INIT_RAM_CFG_HOOK, x)
2657 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
2658 	FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x)
2661 #define FDMA_CH_ACTIVATE          __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 0, 0, 1, 4)
2664 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\  argument
2665 	FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
2666 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\  argument
2667 	FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
2670 #define FDMA_CH_RELOAD            __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 4, 0, 1, 4)
2673 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\  argument
2674 	FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x)
2675 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\  argument
2676 	FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x)
2679 #define FDMA_CH_DISABLE           __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 8, 0, 1, 4)
2682 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\  argument
2683 	FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x)
2684 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\  argument
2685 	FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x)
2688 #define FDMA_DCB_LLP(r)           __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 52, r, 8, 4)
2691 #define FDMA_DCB_LLP1(r)          __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 84, r, 8, 4)
2694 #define FDMA_DCB_LLP_PREV(r)      __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 116, r, 8, 4)
2697 #define FDMA_DCB_LLP_PREV1(r)     __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 148, r, 8, 4)
2700 #define FDMA_CH_CFG(r)            __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 224, r, 8, 4)
2703 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\  argument
2704 	FIELD_PREP(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
2705 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\  argument
2706 	FIELD_GET(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
2709 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\  argument
2710 	FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
2711 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\  argument
2712 	FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
2715 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\  argument
2716 	FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x)
2717 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\  argument
2718 	FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x)
2720 #define FDMA_CH_CFG_CH_DCB_DB_CNT                GENMASK(4, 1)
2721 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\  argument
2722 	FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
2723 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\  argument
2724 	FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
2727 #define FDMA_CH_CFG_CH_MEM_SET(x)\  argument
2728 	FIELD_PREP(FDMA_CH_CFG_CH_MEM, x)
2729 #define FDMA_CH_CFG_CH_MEM_GET(x)\  argument
2730 	FIELD_GET(FDMA_CH_CFG_CH_MEM, x)
2733 #define FDMA_CH_TRANSLATE(r)      __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 256, r, 8, 4)
2736 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\  argument
2737 	FIELD_PREP(FDMA_CH_TRANSLATE_OFFSET, x)
2738 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\  argument
2739 	FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x)
2742 #define FDMA_XTR_CFG              __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 364, 0, 1, 4)
2745 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\  argument
2746 	FIELD_PREP(FDMA_XTR_CFG_XTR_FIFO_WM, x)
2747 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\  argument
2748 	FIELD_GET(FDMA_XTR_CFG_XTR_FIFO_WM, x)
2751 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\  argument
2752 	FIELD_PREP(FDMA_XTR_CFG_XTR_ARB_SAT, x)
2753 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\  argument
2754 	FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x)
2757 #define FDMA_PORT_CTRL(r)         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 376, r, 2, 4)
2759 #define FDMA_PORT_CTRL_INJ_STOP                  BIT(4)
2760 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\  argument
2761 	FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x)
2762 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\  argument
2763 	FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x)
2766 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\  argument
2767 	FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
2768 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\  argument
2769 	FIELD_GET(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
2772 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\  argument
2773 	FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x)
2774 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\  argument
2775 	FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x)
2778 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\  argument
2779 	FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
2780 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\  argument
2781 	FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
2784 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\  argument
2785 	FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_RST, x)
2786 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\  argument
2787 	FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x)
2790 #define FDMA_INTR_DCB             __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 384, 0, 1, 4)
2793 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\  argument
2794 	FIELD_PREP(FDMA_INTR_DCB_INTR_DCB, x)
2795 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\  argument
2796 	FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x)
2799 #define FDMA_INTR_DCB_ENA         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 388, 0, 1, 4)
2802 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\  argument
2803 	FIELD_PREP(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
2804 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\  argument
2805 	FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
2808 #define FDMA_INTR_DB              __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 392, 0, 1, 4)
2811 #define FDMA_INTR_DB_INTR_DB_SET(x)\  argument
2812 	FIELD_PREP(FDMA_INTR_DB_INTR_DB, x)
2813 #define FDMA_INTR_DB_INTR_DB_GET(x)\  argument
2814 	FIELD_GET(FDMA_INTR_DB_INTR_DB, x)
2817 #define FDMA_INTR_DB_ENA          __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 396, 0, 1, 4)
2820 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\  argument
2821 	FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
2822 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\  argument
2823 	FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
2826 #define FDMA_INTR_ERR             __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 400, 0, 1, 4)
2829 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\  argument
2830 	FIELD_PREP(FDMA_INTR_ERR_INTR_PORT_ERR, x)
2831 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\  argument
2832 	FIELD_GET(FDMA_INTR_ERR_INTR_PORT_ERR, x)
2835 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\  argument
2836 	FIELD_PREP(FDMA_INTR_ERR_INTR_CH_ERR, x)
2837 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\  argument
2838 	FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x)
2841 #define FDMA_ERRORS               __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 412, 0, 1, 4)
2844 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\  argument
2845 	FIELD_PREP(FDMA_ERRORS_ERR_XTR_WR, x)
2846 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\  argument
2847 	FIELD_GET(FDMA_ERRORS_ERR_XTR_WR, x)
2850 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\  argument
2851 	FIELD_PREP(FDMA_ERRORS_ERR_XTR_OVF, x)
2852 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\  argument
2853 	FIELD_GET(FDMA_ERRORS_ERR_XTR_OVF, x)
2856 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\  argument
2857 	FIELD_PREP(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
2858 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\  argument
2859 	FIELD_GET(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
2862 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\  argument
2863 	FIELD_PREP(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
2864 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\  argument
2865 	FIELD_GET(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
2868 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\  argument
2869 	FIELD_PREP(FDMA_ERRORS_ERR_DCB_RD, x)
2870 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\  argument
2871 	FIELD_GET(FDMA_ERRORS_ERR_DCB_RD, x)
2874 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\  argument
2875 	FIELD_PREP(FDMA_ERRORS_ERR_INJ_RD, x)
2876 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\  argument
2877 	FIELD_GET(FDMA_ERRORS_ERR_INJ_RD, x)
2880 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\  argument
2881 	FIELD_PREP(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
2882 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\  argument
2883 	FIELD_GET(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
2886 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\  argument
2887 	FIELD_PREP(FDMA_ERRORS_ERR_CH_WR, x)
2888 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\  argument
2889 	FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x)
2892 #define FDMA_ERRORS_2             __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 416, 0, 1, 4)
2895 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\  argument
2896 	FIELD_PREP(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
2897 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\  argument
2898 	FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
2901 #define FDMA_CTRL                 __REG(TARGET_FDMA, 0, 1, 8, 0, 1, 428, 424, 0, 1, 4)
2904 #define FDMA_CTRL_NRESET_SET(x)\  argument
2905 	FIELD_PREP(FDMA_CTRL_NRESET, x)
2906 #define FDMA_CTRL_NRESET_GET(x)\  argument
2907 	FIELD_GET(FDMA_CTRL_NRESET, x)
2910 #define GCB_CHIP_ID               __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 0, 0, 1, 4)
2913 #define GCB_CHIP_ID_REV_ID_SET(x)\  argument
2914 	FIELD_PREP(GCB_CHIP_ID_REV_ID, x)
2915 #define GCB_CHIP_ID_REV_ID_GET(x)\  argument
2916 	FIELD_GET(GCB_CHIP_ID_REV_ID, x)
2919 #define GCB_CHIP_ID_PART_ID_SET(x)\  argument
2920 	FIELD_PREP(GCB_CHIP_ID_PART_ID, x)
2921 #define GCB_CHIP_ID_PART_ID_GET(x)\  argument
2922 	FIELD_GET(GCB_CHIP_ID_PART_ID, x)
2925 #define GCB_CHIP_ID_MFG_ID_SET(x)\  argument
2926 	FIELD_PREP(GCB_CHIP_ID_MFG_ID, x)
2927 #define GCB_CHIP_ID_MFG_ID_GET(x)\  argument
2928 	FIELD_GET(GCB_CHIP_ID_MFG_ID, x)
2931 #define GCB_CHIP_ID_ONE_SET(x)\  argument
2932 	FIELD_PREP(GCB_CHIP_ID_ONE, x)
2933 #define GCB_CHIP_ID_ONE_GET(x)\  argument
2934 	FIELD_GET(GCB_CHIP_ID_ONE, x)
2937 #define GCB_SOFT_RST              __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 8, 0, 1, 4)
2940 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\  argument
2941 	FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
2942 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\  argument
2943 	FIELD_GET(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
2946 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\  argument
2947 	FIELD_PREP(GCB_SOFT_RST_SOFT_SWC_RST, x)
2948 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\  argument
2949 	FIELD_GET(GCB_SOFT_RST_SOFT_SWC_RST, x)
2952 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\  argument
2953 	FIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x)
2954 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\  argument
2955 	FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x)
2958 #define GCB_HW_SGPIO_SD_CFG       __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 20, 0, 1, 4)
2961 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\  argument
2962 	FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
2963 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\  argument
2964 	FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
2967 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\  argument
2968 	FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
2969 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\  argument
2970 	FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
2973 #define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, 24, r, 65, 4)
2976 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\  argument
2977 	FIELD_PREP(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
2978 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\  argument
2979 	FIELD_GET(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
2982 #define GCB_SIO_CLOCK(g)          __REG(TARGET_GCB, 0, 1, 876, g, 3, 280, 20, 0, 1, 4)
2985 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\  argument
2986 	FIELD_PREP(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
2987 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\  argument
2988 	FIELD_GET(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
2991 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\  argument
2992 	FIELD_PREP(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
2993 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\  argument
2994 	FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
2997 #define HSCH_CIR_CFG(g)           __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 0, 0, 1, 4)
3000 #define HSCH_CIR_CFG_CIR_RATE_SET(x)\  argument
3001 	FIELD_PREP(HSCH_CIR_CFG_CIR_RATE, x)
3002 #define HSCH_CIR_CFG_CIR_RATE_GET(x)\  argument
3003 	FIELD_GET(HSCH_CIR_CFG_CIR_RATE, x)
3006 #define HSCH_CIR_CFG_CIR_BURST_SET(x)\  argument
3007 	FIELD_PREP(HSCH_CIR_CFG_CIR_BURST, x)
3008 #define HSCH_CIR_CFG_CIR_BURST_GET(x)\  argument
3009 	FIELD_GET(HSCH_CIR_CFG_CIR_BURST, x)
3012 #define HSCH_EIR_CFG(g)           __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 4, 0, 1, 4)
3015 #define HSCH_EIR_CFG_EIR_RATE_SET(x)\  argument
3016 	FIELD_PREP(HSCH_EIR_CFG_EIR_RATE, x)
3017 #define HSCH_EIR_CFG_EIR_RATE_GET(x)\  argument
3018 	FIELD_GET(HSCH_EIR_CFG_EIR_RATE, x)
3021 #define HSCH_EIR_CFG_EIR_BURST_SET(x)\  argument
3022 	FIELD_PREP(HSCH_EIR_CFG_EIR_BURST, x)
3023 #define HSCH_EIR_CFG_EIR_BURST_GET(x)\  argument
3024 	FIELD_GET(HSCH_EIR_CFG_EIR_BURST, x)
3027 #define HSCH_SE_CFG(g)            __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 8, 0, 1, 4)
3030 #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\  argument
3031 	FIELD_PREP(HSCH_SE_CFG_SE_DWRR_CNT, x)
3032 #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\  argument
3033 	FIELD_GET(HSCH_SE_CFG_SE_DWRR_CNT, x)
3036 #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\  argument
3037 	FIELD_PREP(HSCH_SE_CFG_SE_AVB_ENA, x)
3038 #define HSCH_SE_CFG_SE_AVB_ENA_GET(x)\  argument
3039 	FIELD_GET(HSCH_SE_CFG_SE_AVB_ENA, x)
3041 #define HSCH_SE_CFG_SE_FRM_MODE                  GENMASK(4, 3)
3042 #define HSCH_SE_CFG_SE_FRM_MODE_SET(x)\  argument
3043 	FIELD_PREP(HSCH_SE_CFG_SE_FRM_MODE, x)
3044 #define HSCH_SE_CFG_SE_FRM_MODE_GET(x)\  argument
3045 	FIELD_GET(HSCH_SE_CFG_SE_FRM_MODE, x)
3048 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_SET(x)\  argument
3049 	FIELD_PREP(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x)
3050 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_GET(x)\  argument
3051 	FIELD_GET(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x)
3054 #define HSCH_SE_CFG_SE_STOP_SET(x)\  argument
3055 	FIELD_PREP(HSCH_SE_CFG_SE_STOP, x)
3056 #define HSCH_SE_CFG_SE_STOP_GET(x)\  argument
3057 	FIELD_GET(HSCH_SE_CFG_SE_STOP, x)
3060 #define HSCH_SE_CONNECT(g)        __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 12, 0, 1, 4)
3063 #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\  argument
3064 	FIELD_PREP(HSCH_SE_CONNECT_SE_LEAK_LINK, x)
3065 #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\  argument
3066 	FIELD_GET(HSCH_SE_CONNECT_SE_LEAK_LINK, x)
3069 #define HSCH_SE_DLB_SENSE(g)      __REG(TARGET_HSCH, 0, 1, 0, g, 5040, 32, 16, 0, 1, 4)
3072 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\  argument
3073 	FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x)
3074 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\  argument
3075 	FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x)
3078 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\  argument
3079 	FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x)
3080 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\  argument
3081 	FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x)
3084 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\  argument
3085 	FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x)
3086 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_GET(x)\  argument
3087 	FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x)
3090 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_SET(x)\  argument
3091 	FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x)
3092 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_GET(x)\  argument
3093 	FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x)
3096 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_SET(x)\  argument
3097 	FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x)
3098 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\  argument
3099 	FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x)
3102 #define HSCH_DWRR_ENTRY(g)        __REG(TARGET_HSCH, 0, 1, 162816, g, 72, 4, 0, 0, 1, 4)
3105 #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\  argument
3106 	FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_COST, x)
3107 #define HSCH_DWRR_ENTRY_DWRR_COST_GET(x)\  argument
3108 	FIELD_GET(HSCH_DWRR_ENTRY_DWRR_COST, x)
3111 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x)\  argument
3112 	FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_BALANCE, x)
3113 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\  argument
3114 	FIELD_GET(HSCH_DWRR_ENTRY_DWRR_BALANCE, x)
3117 #define HSCH_HSCH_CFG_CFG         __REG(TARGET_HSCH, 0, 1, 163104, 0, 1, 648, 284, 0, 1, 4)
3120 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\  argument
3121 	FIELD_PREP(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x)
3122 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\  argument
3123 	FIELD_GET(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x)
3126 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\  argument
3127 	FIELD_PREP(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x)
3128 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_GET(x)\  argument
3129 	FIELD_GET(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x)
3132 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_SET(x)\  argument
3133 	FIELD_PREP(HSCH_HSCH_CFG_CFG_CSR_GRANT, x)
3134 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\  argument
3135 	FIELD_GET(HSCH_HSCH_CFG_CFG_CSR_GRANT, x)
3138 #define HSCH_SYS_CLK_PER          __REG(TARGET_HSCH, 0, 1, 163104, 0, 1, 648, 640, 0, 1, 4)
3141 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_SET(x)\  argument
3142 	FIELD_PREP(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS, x)
3143 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_GET(x)\  argument
3144 	FIELD_GET(HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS, x)
3147 #define HSCH_HSCH_TIMER_CFG(g, r) __REG(TARGET_HSCH, 0, 1, 161664, g, 4, 32, 0, r, 4, 4)
3150 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\  argument
3151 	FIELD_PREP(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x)
3152 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\  argument
3153 	FIELD_GET(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x)
3156 #define HSCH_HSCH_LEAK_CFG(g, r)  __REG(TARGET_HSCH, 0, 1, 161664, g, 4, 32, 16, r, 4, 4)
3159 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\  argument
3160 	FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x)
3161 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\  argument
3162 	FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x)
3165 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\  argument
3166 	FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x)
3167 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\  argument
3168 	FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x)
3171 #define HSCH_FLUSH_CTRL           __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 4, 0, 1, 4)
3174 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\  argument
3175 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
3176 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\  argument
3177 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
3180 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\  argument
3181 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
3182 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\  argument
3183 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
3186 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\  argument
3187 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_DST, x)
3188 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\  argument
3189 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x)
3192 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\  argument
3193 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
3194 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\  argument
3195 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
3198 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\  argument
3199 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
3200 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\  argument
3201 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
3204 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\  argument
3205 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SE, x)
3206 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\  argument
3207 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x)
3210 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\  argument
3211 	FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
3212 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\  argument
3213 	FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
3216 #define HSCH_PORT_MODE(r)         __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 8, r, 70, 4)
3218 #define HSCH_PORT_MODE_DEQUEUE_DIS               BIT(4)
3219 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\  argument
3220 	FIELD_PREP(HSCH_PORT_MODE_DEQUEUE_DIS, x)
3221 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\  argument
3222 	FIELD_GET(HSCH_PORT_MODE_DEQUEUE_DIS, x)
3225 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\  argument
3226 	FIELD_PREP(HSCH_PORT_MODE_AGE_DIS, x)
3227 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\  argument
3228 	FIELD_GET(HSCH_PORT_MODE_AGE_DIS, x)
3231 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\  argument
3232 	FIELD_PREP(HSCH_PORT_MODE_TRUNC_ENA, x)
3233 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\  argument
3234 	FIELD_GET(HSCH_PORT_MODE_TRUNC_ENA, x)
3237 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\  argument
3238 	FIELD_PREP(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
3239 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\  argument
3240 	FIELD_GET(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
3243 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\  argument
3244 	FIELD_PREP(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
3245 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\  argument
3246 	FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
3249 #define HSCH_OUTB_SHARE_ENA(r)    __REG(TARGET_HSCH, 0, 1, 184000, 0, 1, 312, 288, r, 5, 4)
3252 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\  argument
3253 	FIELD_PREP(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
3254 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\  argument
3255 	FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
3258 #define HSCH_RESET_CFG            __REG(TARGET_HSCH, 0, 1, 162368, 0, 1, 16, 8, 0, 1, 4)
3261 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\  argument
3262 	FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x)
3263 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\  argument
3264 	FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x)
3267 #define HSCH_TAS_STATEMACHINE_CFG __REG(TARGET_HSCH, 0, 1, 162384, 0, 1, 12, 8, 0, 1, 4)
3270 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\  argument
3271 	FIELD_PREP(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
3272 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\  argument
3273 	FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
3276 #define LRN_COMMON_ACCESS_CTRL    __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4)
3279 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\  argument
3280 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
3281 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\  argument
3282 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
3285 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\  argument
3286 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
3287 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\  argument
3288 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
3291 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\  argument
3292 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
3293 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\  argument
3294 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
3296 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD    GENMASK(4, 1)
3297 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\  argument
3298 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
3299 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\  argument
3300 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
3303 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\  argument
3304 	FIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
3305 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\  argument
3306 	FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
3309 #define LRN_MAC_ACCESS_CFG_0      __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4)
3312 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\  argument
3313 	FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
3314 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\  argument
3315 	FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
3318 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\  argument
3319 	FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
3320 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\  argument
3321 	FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
3324 #define LRN_MAC_ACCESS_CFG_1      __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4)
3327 #define LRN_MAC_ACCESS_CFG_2      __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 12, 0, 1, 4)
3330 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\  argument
3331 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
3332 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\  argument
3333 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
3336 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\  argument
3337 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
3338 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\  argument
3339 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
3342 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\  argument
3343 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
3344 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\  argument
3345 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
3348 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\  argument
3349 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
3350 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\  argument
3351 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
3354 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\  argument
3355 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
3356 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\  argument
3357 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
3360 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\  argument
3361 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
3362 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\  argument
3363 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
3366 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\  argument
3367 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
3368 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\  argument
3369 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
3372 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\  argument
3373 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
3374 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\  argument
3375 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
3378 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\  argument
3379 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
3380 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\  argument
3381 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
3384 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\  argument
3385 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
3386 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\  argument
3387 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
3390 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\  argument
3391 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
3392 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\  argument
3393 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
3396 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\  argument
3397 	FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
3398 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\  argument
3399 	FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
3402 #define LRN_MAC_ACCESS_CFG_3      __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 16, 0, 1, 4)
3405 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\  argument
3406 	FIELD_PREP(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
3407 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\  argument
3408 	FIELD_GET(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
3411 #define LRN_SCAN_NEXT_CFG         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 20, 0, 1, 4)
3414 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\  argument
3415 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
3416 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\  argument
3417 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
3420 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\  argument
3421 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
3422 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\  argument
3423 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
3426 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\  argument
3427 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
3428 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\  argument
3429 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
3432 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\  argument
3433 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
3434 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\  argument
3435 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
3438 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\  argument
3439 	FIELD_PREP(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
3440 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\  argument
3441 	FIELD_GET(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
3444 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\  argument
3445 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
3446 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\  argument
3447 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
3450 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\  argument
3451 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
3452 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\  argument
3453 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
3456 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\  argument
3457 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
3458 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\  argument
3459 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
3462 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\  argument
3463 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
3464 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\  argument
3465 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
3468 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\  argument
3469 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
3470 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\  argument
3471 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
3474 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\  argument
3475 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
3476 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\  argument
3477 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
3480 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\  argument
3481 	FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
3482 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\  argument
3483 	FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
3486 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\  argument
3487 	FIELD_PREP(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
3488 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\  argument
3489 	FIELD_GET(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
3492 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\  argument
3493 	FIELD_PREP(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
3494 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\  argument
3495 	FIELD_GET(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
3498 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\  argument
3499 	FIELD_PREP(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
3500 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\  argument
3501 	FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
3504 #define LRN_SCAN_NEXT_CFG_1       __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 24, 0, 1, 4)
3507 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\  argument
3508 	FIELD_PREP(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
3509 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\  argument
3510 	FIELD_GET(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
3513 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\  argument
3514 	FIELD_PREP(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
3515 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\  argument
3516 	FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
3519 #define LRN_AUTOAGE_CFG(r)        __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 36, r, 4, 4)
3522 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\  argument
3523 	FIELD_PREP(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
3524 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\  argument
3525 	FIELD_GET(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
3528 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\  argument
3529 	FIELD_PREP(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
3530 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\  argument
3531 	FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
3534 #define LRN_AUTOAGE_CFG_1         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 52, 0, 1, 4)
3537 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\  argument
3538 	FIELD_PREP(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
3539 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\  argument
3540 	FIELD_GET(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
3543 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\  argument
3544 	FIELD_PREP(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
3545 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\  argument
3546 	FIELD_GET(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
3549 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\  argument
3550 	FIELD_PREP(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
3551 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\  argument
3552 	FIELD_GET(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
3555 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\  argument
3556 	FIELD_PREP(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
3557 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\  argument
3558 	FIELD_GET(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
3561 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\  argument
3562 	FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
3563 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\  argument
3564 	FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
3567 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\  argument
3568 	FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
3569 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\  argument
3570 	FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
3573 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\  argument
3574 	FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
3575 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\  argument
3576 	FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
3579 #define LRN_AUTOAGE_CFG_2         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 56, 0, 1, 4)
3581 #define LRN_AUTOAGE_CFG_2_NEXT_ROW               GENMASK(17, 4)
3582 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\  argument
3583 	FIELD_PREP(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
3584 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\  argument
3585 	FIELD_GET(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
3588 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\  argument
3589 	FIELD_PREP(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
3590 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\  argument
3591 	FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
3594 #define PCEP_RCTRL_2_OUT_0        __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4)
3597 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\  argument
3598 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
3599 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\  argument
3600 	FIELD_GET(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
3603 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\  argument
3604 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG, x)
3605 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\  argument
3606 	FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG, x)
3609 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\  argument
3610 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
3611 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\  argument
3612 	FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
3615 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\  argument
3616 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
3617 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\  argument
3618 	FIELD_GET(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
3621 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\  argument
3622 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_SNP, x)
3623 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\  argument
3624 	FIELD_GET(PCEP_RCTRL_2_OUT_0_SNP, x)
3627 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\  argument
3628 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
3629 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\  argument
3630 	FIELD_GET(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
3633 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\  argument
3634 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
3635 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\  argument
3636 	FIELD_GET(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
3639 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\  argument
3640 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
3641 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\  argument
3642 	FIELD_GET(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
3645 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\  argument
3646 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
3647 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\  argument
3648 	FIELD_GET(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
3651 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\  argument
3652 	FIELD_PREP(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
3653 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\  argument
3654 	FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
3657 #define PCEP_ADDR_LWR_OUT_0       __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4)
3660 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\  argument
3661 	FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
3662 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\  argument
3663 	FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
3666 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\  argument
3667 	FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
3668 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\  argument
3669 	FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
3672 #define PCEP_ADDR_UPR_OUT_0       __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4)
3675 #define PCEP_ADDR_LIM_OUT_0       __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4)
3678 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\  argument
3679 	FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
3680 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\  argument
3681 	FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
3684 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\  argument
3685 	FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
3686 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\  argument
3687 	FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
3690 #define PCEP_ADDR_LWR_TGT_OUT_0   __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4)
3693 #define PCEP_ADDR_UPR_TGT_OUT_0   __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4)
3696 #define PCEP_ADDR_UPR_LIM_OUT_0   __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4)
3699 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\  argument
3700 	FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
3701 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\  argument
3702 	FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
3705 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\  argument
3706 	FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
3707 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\  argument
3708 	FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
3711 #define PCS10G_BR_PCS_CFG(t)      __REG(TARGET_PCS10G_BR, t, 12, 0, 0, 1, 56, 0, 0, 1, 4)
3714 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
3715 	FIELD_PREP(PCS10G_BR_PCS_CFG_PCS_ENA, x)
3716 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
3717 	FIELD_GET(PCS10G_BR_PCS_CFG_PCS_ENA, x)
3720 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
3721 	FIELD_PREP(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3722 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
3723 	FIELD_GET(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3726 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
3727 	FIELD_PREP(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
3728 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
3729 	FIELD_GET(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
3732 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
3733 	FIELD_PREP(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
3734 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
3735 	FIELD_GET(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
3738 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
3739 	FIELD_PREP(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
3740 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
3741 	FIELD_GET(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
3744 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
3745 	FIELD_PREP(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
3746 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
3747 	FIELD_GET(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
3750 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
3751 	FIELD_PREP(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
3752 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
3753 	FIELD_GET(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
3756 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
3757 	FIELD_PREP(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3758 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
3759 	FIELD_GET(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3762 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
3763 	FIELD_PREP(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
3764 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
3765 	FIELD_GET(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
3768 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
3769 	FIELD_PREP(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3770 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
3771 	FIELD_GET(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3773 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE           BIT(4)
3774 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
3775 	FIELD_PREP(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
3776 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
3777 	FIELD_GET(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
3780 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
3781 	FIELD_PREP(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3782 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
3783 	FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3786 #define PCS10G_BR_PCS_SD_CFG(t)   __REG(TARGET_PCS10G_BR, t, 12, 0, 0, 1, 56, 4, 0, 1, 4)
3789 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
3790 	FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
3791 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
3792 	FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
3794 #define PCS10G_BR_PCS_SD_CFG_SD_POL              BIT(4)
3795 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
3796 	FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
3797 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
3798 	FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
3801 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
3802 	FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
3803 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
3804 	FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
3807 #define PCS25G_BR_PCS_CFG(t)      __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 0, 0, 1, 4)
3810 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
3811 	FIELD_PREP(PCS25G_BR_PCS_CFG_PCS_ENA, x)
3812 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
3813 	FIELD_GET(PCS25G_BR_PCS_CFG_PCS_ENA, x)
3816 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
3817 	FIELD_PREP(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3818 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
3819 	FIELD_GET(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3822 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
3823 	FIELD_PREP(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
3824 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
3825 	FIELD_GET(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
3828 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
3829 	FIELD_PREP(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
3830 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
3831 	FIELD_GET(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
3834 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
3835 	FIELD_PREP(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
3836 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
3837 	FIELD_GET(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
3840 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
3841 	FIELD_PREP(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
3842 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
3843 	FIELD_GET(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
3846 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
3847 	FIELD_PREP(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
3848 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
3849 	FIELD_GET(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
3852 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
3853 	FIELD_PREP(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3854 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
3855 	FIELD_GET(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3858 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
3859 	FIELD_PREP(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
3860 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
3861 	FIELD_GET(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
3864 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
3865 	FIELD_PREP(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3866 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
3867 	FIELD_GET(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3869 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE           BIT(4)
3870 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
3871 	FIELD_PREP(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
3872 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
3873 	FIELD_GET(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
3876 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
3877 	FIELD_PREP(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3878 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
3879 	FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3882 #define PCS25G_BR_PCS_SD_CFG(t)   __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 4, 0, 1, 4)
3885 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
3886 	FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
3887 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
3888 	FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
3890 #define PCS25G_BR_PCS_SD_CFG_SD_POL              BIT(4)
3891 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
3892 	FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
3893 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
3894 	FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
3897 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
3898 	FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
3899 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
3900 	FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
3903 #define PCS5G_BR_PCS_CFG(t)       __REG(TARGET_PCS5G_BR, t, 13, 0, 0, 1, 56, 0, 0, 1, 4)
3906 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
3907 	FIELD_PREP(PCS5G_BR_PCS_CFG_PCS_ENA, x)
3908 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
3909 	FIELD_GET(PCS5G_BR_PCS_CFG_PCS_ENA, x)
3912 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
3913 	FIELD_PREP(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3914 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
3915 	FIELD_GET(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
3918 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
3919 	FIELD_PREP(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
3920 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
3921 	FIELD_GET(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
3924 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
3925 	FIELD_PREP(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
3926 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
3927 	FIELD_GET(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
3930 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
3931 	FIELD_PREP(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
3932 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
3933 	FIELD_GET(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
3936 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
3937 	FIELD_PREP(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
3938 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
3939 	FIELD_GET(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
3942 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
3943 	FIELD_PREP(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
3944 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
3945 	FIELD_GET(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
3948 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
3949 	FIELD_PREP(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3950 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
3951 	FIELD_GET(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
3954 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
3955 	FIELD_PREP(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
3956 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
3957 	FIELD_GET(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
3960 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
3961 	FIELD_PREP(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3962 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
3963 	FIELD_GET(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
3965 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE            BIT(4)
3966 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
3967 	FIELD_PREP(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
3968 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
3969 	FIELD_GET(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
3972 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
3973 	FIELD_PREP(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3974 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
3975 	FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
3978 #define PCS5G_BR_PCS_SD_CFG(t)    __REG(TARGET_PCS5G_BR, t, 13, 0, 0, 1, 56, 4, 0, 1, 4)
3981 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
3982 	FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
3983 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
3984 	FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
3986 #define PCS5G_BR_PCS_SD_CFG_SD_POL               BIT(4)
3987 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
3988 	FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
3989 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
3990 	FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
3993 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
3994 	FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
3995 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
3996 	FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
3999 #define PORT_CONF_DEV5G_MODES     __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 0, 0, 1, 4)
4002 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\  argument
4003 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
4004 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\  argument
4005 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
4008 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\  argument
4009 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
4010 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\  argument
4011 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
4014 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\  argument
4015 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
4016 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\  argument
4017 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
4020 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\  argument
4021 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
4022 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\  argument
4023 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
4025 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE      BIT(4)
4026 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\  argument
4027 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
4028 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\  argument
4029 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
4032 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\  argument
4033 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
4034 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\  argument
4035 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
4038 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\  argument
4039 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
4040 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\  argument
4041 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
4044 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\  argument
4045 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
4046 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\  argument
4047 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
4050 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\  argument
4051 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
4052 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\  argument
4053 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
4056 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\  argument
4057 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
4058 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\  argument
4059 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
4062 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\  argument
4063 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
4064 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\  argument
4065 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
4068 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\  argument
4069 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
4070 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\  argument
4071 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
4074 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\  argument
4075 	FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
4076 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\  argument
4077 	FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
4080 #define PORT_CONF_DEV10G_MODES    __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 4, 0, 1, 4)
4083 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\  argument
4084 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
4085 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\  argument
4086 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
4089 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\  argument
4090 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
4091 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\  argument
4092 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
4095 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\  argument
4096 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
4097 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\  argument
4098 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
4101 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\  argument
4102 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
4103 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\  argument
4104 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
4106 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE   BIT(4)
4107 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\  argument
4108 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
4109 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\  argument
4110 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
4113 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\  argument
4114 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
4115 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\  argument
4116 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
4119 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\  argument
4120 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
4121 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\  argument
4122 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
4125 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\  argument
4126 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
4127 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\  argument
4128 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
4131 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\  argument
4132 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
4133 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\  argument
4134 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
4137 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\  argument
4138 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
4139 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\  argument
4140 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
4143 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\  argument
4144 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
4145 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\  argument
4146 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
4149 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\  argument
4150 	FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
4151 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\  argument
4152 	FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
4155 #define PORT_CONF_DEV25G_MODES    __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 8, 0, 1, 4)
4158 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\  argument
4159 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
4160 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\  argument
4161 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
4164 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\  argument
4165 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
4166 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\  argument
4167 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
4170 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\  argument
4171 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
4172 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\  argument
4173 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
4176 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\  argument
4177 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
4178 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\  argument
4179 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
4181 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE   BIT(4)
4182 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\  argument
4183 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
4184 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\  argument
4185 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
4188 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\  argument
4189 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
4190 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\  argument
4191 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
4194 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\  argument
4195 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
4196 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\  argument
4197 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
4200 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\  argument
4201 	FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
4202 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\  argument
4203 	FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
4206 #define PORT_CONF_QSGMII_ENA      __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 12, 0, 1, 4)
4209 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\  argument
4210 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
4211 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\  argument
4212 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
4215 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\  argument
4216 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
4217 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\  argument
4218 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
4221 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\  argument
4222 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
4223 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\  argument
4224 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
4227 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\  argument
4228 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
4229 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\  argument
4230 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
4232 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4        BIT(4)
4233 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\  argument
4234 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
4235 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\  argument
4236 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
4239 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\  argument
4240 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
4241 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\  argument
4242 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
4245 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\  argument
4246 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
4247 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\  argument
4248 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
4251 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\  argument
4252 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
4253 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\  argument
4254 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
4257 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\  argument
4258 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
4259 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\  argument
4260 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
4263 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\  argument
4264 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
4265 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\  argument
4266 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
4269 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\  argument
4270 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
4271 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\  argument
4272 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
4275 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\  argument
4276 	FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
4277 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\  argument
4278 	FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
4281 #define PORT_CONF_USGMII_CFG(g)   __REG(TARGET_PORT_CONF, 0, 1, 72, g, 6, 8, 0, 0, 1, 4)
4284 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\  argument
4285 	FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
4286 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\  argument
4287 	FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
4290 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\  argument
4291 	FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
4292 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\  argument
4293 	FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
4296 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\  argument
4297 	FIELD_PREP(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
4298 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\  argument
4299 	FIELD_GET(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
4302 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\  argument
4303 	FIELD_PREP(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
4304 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\  argument
4305 	FIELD_GET(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
4308 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\  argument
4309 	FIELD_PREP(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
4310 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\  argument
4311 	FIELD_GET(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
4313 #define PORT_CONF_USGMII_CFG_USE_I1_ENA          BIT(4)
4314 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\  argument
4315 	FIELD_PREP(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
4316 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\  argument
4317 	FIELD_GET(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
4320 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\  argument
4321 	FIELD_PREP(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
4322 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\  argument
4323 	FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
4326 #define PTP_PTP_PIN_INTR          __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 0, 0, 1, 4)
4328 #define PTP_PTP_PIN_INTR_INTR_PTP                GENMASK(4, 0)
4329 #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\  argument
4330 	FIELD_PREP(PTP_PTP_PIN_INTR_INTR_PTP, x)
4331 #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\  argument
4332 	FIELD_GET(PTP_PTP_PIN_INTR_INTR_PTP, x)
4335 #define PTP_PTP_PIN_INTR_ENA      __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 4, 0, 1, 4)
4337 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA        GENMASK(4, 0)
4338 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\  argument
4339 	FIELD_PREP(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x)
4340 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\  argument
4341 	FIELD_GET(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x)
4344 #define PTP_PTP_INTR_IDENT        __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 8, 0, 1, 4)
4346 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT        GENMASK(4, 0)
4347 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\  argument
4348 	FIELD_PREP(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x)
4349 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\  argument
4350 	FIELD_GET(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x)
4353 #define PTP_PTP_DOM_CFG           __REG(TARGET_PTP, 0, 1, 320, 0, 1, 16, 12, 0, 1, 4)
4356 #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\  argument
4357 	FIELD_PREP(PTP_PTP_DOM_CFG_PTP_ENA, x)
4358 #define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\  argument
4359 	FIELD_GET(PTP_PTP_DOM_CFG_PTP_ENA, x)
4362 #define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\  argument
4363 	FIELD_PREP(PTP_PTP_DOM_CFG_PTP_HOLD, x)
4364 #define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\  argument
4365 	FIELD_GET(PTP_PTP_DOM_CFG_PTP_HOLD, x)
4368 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\  argument
4369 	FIELD_PREP(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x)
4370 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\  argument
4371 	FIELD_GET(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x)
4374 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\  argument
4375 	FIELD_PREP(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x)
4376 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\  argument
4377 	FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x)
4380 #define PTP_CLK_PER_CFG(g, r)     __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 0, r, 2, 4)
4383 #define PTP_PTP_CUR_NSEC(g)       __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 8, 0, 1, 4)
4386 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\  argument
4387 	FIELD_PREP(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x)
4388 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\  argument
4389 	FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x)
4392 #define PTP_PTP_CUR_NSEC_FRAC(g)  __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 12, 0, 1, 4)
4395 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\  argument
4396 	FIELD_PREP(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x)
4397 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\  argument
4398 	FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x)
4401 #define PTP_PTP_CUR_SEC_LSB(g)    __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 16, 0, 1, 4)
4404 #define PTP_PTP_CUR_SEC_MSB(g)    __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 20, 0, 1, 4)
4407 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\  argument
4408 	FIELD_PREP(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x)
4409 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\  argument
4410 	FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x)
4413 #define PTP_NTP_CUR_NSEC(g)       __REG(TARGET_PTP, 0, 1, 336, g, 3, 28, 24, 0, 1, 4)
4416 #define PTP_PTP_PIN_CFG(g)        __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 0, 0, 1, 4)
4419 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\  argument
4420 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x)
4421 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\  argument
4422 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x)
4425 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\  argument
4426 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x)
4427 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\  argument
4428 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x)
4431 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\  argument
4432 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x)
4433 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\  argument
4434 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x)
4437 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\  argument
4438 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x)
4439 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\  argument
4440 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x)
4443 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\  argument
4444 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x)
4445 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\  argument
4446 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x)
4449 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\  argument
4450 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x)
4451 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\  argument
4452 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x)
4455 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\  argument
4456 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x)
4457 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\  argument
4458 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x)
4461 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\  argument
4462 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x)
4463 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\  argument
4464 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x)
4467 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\  argument
4468 	FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x)
4469 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\  argument
4470 	FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x)
4473 #define PTP_PTP_TOD_SEC_MSB(g)    __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 4, 0, 1, 4)
4476 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\  argument
4477 	FIELD_PREP(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x)
4478 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\  argument
4479 	FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x)
4482 #define PTP_PTP_TOD_SEC_LSB(g)    __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 8, 0, 1, 4)
4485 #define PTP_PTP_TOD_NSEC(g)       __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 12, 0, 1, 4)
4488 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\  argument
4489 	FIELD_PREP(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x)
4490 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\  argument
4491 	FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x)
4494 #define PTP_PTP_TOD_NSEC_FRAC(g)  __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 16, 0, 1, 4)
4497 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\  argument
4498 	FIELD_PREP(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x)
4499 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\  argument
4500 	FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x)
4503 #define PTP_NTP_NSEC(g)           __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 20, 0, 1, 4)
4506 #define PTP_PIN_WF_HIGH_PERIOD(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 24, 0, 1, 4)
4509 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\  argument
4510 	FIELD_PREP(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x)
4511 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\  argument
4512 	FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x)
4515 #define PTP_PIN_WF_LOW_PERIOD(g)  __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 28, 0, 1, 4)
4518 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\  argument
4519 	FIELD_PREP(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x)
4520 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\  argument
4521 	FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x)
4524 #define PTP_PIN_IOBOUNCH_DELAY(g) __REG(TARGET_PTP, 0, 1, 0, g, 5, 64, 32, 0, 1, 4)
4527 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\  argument
4528 	FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x)
4529 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\  argument
4530 	FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x)
4533 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\  argument
4534 	FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x)
4535 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\  argument
4536 	FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x)
4539 #define PTP_PHAD_CTRL(g)          __REG(TARGET_PTP, 0, 1, 420, g, 5, 8, 0, 0, 1, 4)
4542 #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\  argument
4543 	FIELD_PREP(PTP_PHAD_CTRL_PHAD_ENA, x)
4544 #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\  argument
4545 	FIELD_GET(PTP_PHAD_CTRL_PHAD_ENA, x)
4548 #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\  argument
4549 	FIELD_PREP(PTP_PHAD_CTRL_PHAD_FAILED, x)
4550 #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\  argument
4551 	FIELD_GET(PTP_PHAD_CTRL_PHAD_FAILED, x)
4554 #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\  argument
4555 	FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x)
4556 #define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\  argument
4557 	FIELD_GET(PTP_PHAD_CTRL_REDUCED_RES, x)
4560 #define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\  argument
4561 	FIELD_PREP(PTP_PHAD_CTRL_LOCK_ACC, x)
4562 #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\  argument
4563 	FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x)
4566 #define PTP_PHAD_CYC_STAT(g)      __REG(TARGET_PTP, 0, 1, 420, g, 5, 8, 4, 0, 1, 4)
4569 #define QFWD_SWITCH_PORT_MODE(r)  __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, 70, 4)
4572 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\  argument
4573 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
4574 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\  argument
4575 	FIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
4578 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\  argument
4579 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
4580 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\  argument
4581 	FIELD_GET(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
4584 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\  argument
4585 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
4586 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\  argument
4587 	FIELD_GET(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
4590 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\  argument
4591 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
4592 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\  argument
4593 	FIELD_GET(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
4595 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING     BIT(4)
4596 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\  argument
4597 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
4598 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\  argument
4599 	FIELD_GET(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
4602 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\  argument
4603 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
4604 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\  argument
4605 	FIELD_GET(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
4608 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\  argument
4609 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
4610 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\  argument
4611 	FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
4614 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\  argument
4615 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
4616 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\  argument
4617 	FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
4620 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\  argument
4621 	FIELD_PREP(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
4622 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\  argument
4623 	FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
4626 #define QRES_RES_CFG(g)           __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 0, 0, 1, 4)
4629 #define QRES_RES_CFG_WM_HIGH_SET(x)\  argument
4630 	FIELD_PREP(QRES_RES_CFG_WM_HIGH, x)
4631 #define QRES_RES_CFG_WM_HIGH_GET(x)\  argument
4632 	FIELD_GET(QRES_RES_CFG_WM_HIGH, x)
4635 #define QRES_RES_STAT(g)          __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 4, 0, 1, 4)
4638 #define QRES_RES_STAT_MAXUSE_SET(x)\  argument
4639 	FIELD_PREP(QRES_RES_STAT_MAXUSE, x)
4640 #define QRES_RES_STAT_MAXUSE_GET(x)\  argument
4641 	FIELD_GET(QRES_RES_STAT_MAXUSE, x)
4644 #define QRES_RES_STAT_CUR(g)      __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 8, 0, 1, 4)
4647 #define QRES_RES_STAT_CUR_INUSE_SET(x)\  argument
4648 	FIELD_PREP(QRES_RES_STAT_CUR_INUSE, x)
4649 #define QRES_RES_STAT_CUR_INUSE_GET(x)\  argument
4650 	FIELD_GET(QRES_RES_STAT_CUR_INUSE, x)
4653 #define QS_XTR_GRP_CFG(r)         __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
4656 #define QS_XTR_GRP_CFG_MODE_SET(x)\  argument
4657 	FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)
4658 #define QS_XTR_GRP_CFG_MODE_GET(x)\  argument
4659 	FIELD_GET(QS_XTR_GRP_CFG_MODE, x)
4662 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\  argument
4663 	FIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
4664 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\  argument
4665 	FIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
4668 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\  argument
4669 	FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)
4670 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\  argument
4671 	FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)
4674 #define QS_XTR_RD(r)              __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4)
4677 #define QS_XTR_FLUSH              __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)
4680 #define QS_XTR_FLUSH_FLUSH_SET(x)\  argument
4681 	FIELD_PREP(QS_XTR_FLUSH_FLUSH, x)
4682 #define QS_XTR_FLUSH_FLUSH_GET(x)\  argument
4683 	FIELD_GET(QS_XTR_FLUSH_FLUSH, x)
4686 #define QS_XTR_DATA_PRESENT       __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)
4689 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\  argument
4690 	FIELD_PREP(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
4691 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\  argument
4692 	FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
4695 #define QS_INJ_GRP_CFG(r)         __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4)
4698 #define QS_INJ_GRP_CFG_MODE_SET(x)\  argument
4699 	FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)
4700 #define QS_INJ_GRP_CFG_MODE_GET(x)\  argument
4701 	FIELD_GET(QS_INJ_GRP_CFG_MODE, x)
4704 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\  argument
4705 	FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)
4706 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\  argument
4707 	FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)
4710 #define QS_INJ_WR(r)              __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4)
4713 #define QS_INJ_CTRL(r)            __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4)
4716 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\  argument
4717 	FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x)
4718 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\  argument
4719 	FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x)
4722 #define QS_INJ_CTRL_ABORT_SET(x)\  argument
4723 	FIELD_PREP(QS_INJ_CTRL_ABORT, x)
4724 #define QS_INJ_CTRL_ABORT_GET(x)\  argument
4725 	FIELD_GET(QS_INJ_CTRL_ABORT, x)
4728 #define QS_INJ_CTRL_EOF_SET(x)\  argument
4729 	FIELD_PREP(QS_INJ_CTRL_EOF, x)
4730 #define QS_INJ_CTRL_EOF_GET(x)\  argument
4731 	FIELD_GET(QS_INJ_CTRL_EOF, x)
4734 #define QS_INJ_CTRL_SOF_SET(x)\  argument
4735 	FIELD_PREP(QS_INJ_CTRL_SOF, x)
4736 #define QS_INJ_CTRL_SOF_GET(x)\  argument
4737 	FIELD_GET(QS_INJ_CTRL_SOF, x)
4740 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\  argument
4741 	FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x)
4742 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\  argument
4743 	FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x)
4746 #define QS_INJ_STATUS             __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4)
4748 #define QS_INJ_STATUS_WMARK_REACHED              GENMASK(5, 4)
4749 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\  argument
4750 	FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x)
4751 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\  argument
4752 	FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x)
4755 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\  argument
4756 	FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x)
4757 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\  argument
4758 	FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x)
4761 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\  argument
4762 	FIELD_PREP(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
4763 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\  argument
4764 	FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
4767 #define QSYS_PAUSE_CFG(r)         __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 0, r, 70, 4)
4770 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\  argument
4771 	FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_START, x)
4772 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\  argument
4773 	FIELD_GET(QSYS_PAUSE_CFG_PAUSE_START, x)
4776 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\  argument
4777 	FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_STOP, x)
4778 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\  argument
4779 	FIELD_GET(QSYS_PAUSE_CFG_PAUSE_STOP, x)
4782 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\  argument
4783 	FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_ENA, x)
4784 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\  argument
4785 	FIELD_GET(QSYS_PAUSE_CFG_PAUSE_ENA, x)
4788 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\  argument
4789 	FIELD_PREP(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
4790 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\  argument
4791 	FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
4794 #define QSYS_ATOP(r)              __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 284, r, 70, 4)
4797 #define QSYS_ATOP_ATOP_SET(x)\  argument
4798 	FIELD_PREP(QSYS_ATOP_ATOP, x)
4799 #define QSYS_ATOP_ATOP_GET(x)\  argument
4800 	FIELD_GET(QSYS_ATOP_ATOP, x)
4803 #define QSYS_FWD_PRESSURE(r)      __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 564, r, 70, 4)
4806 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\  argument
4807 	FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
4808 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\  argument
4809 	FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
4812 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\  argument
4813 	FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
4814 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\  argument
4815 	FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
4818 #define QSYS_ATOP_TOT_CFG         __REG(TARGET_QSYS, 0, 1, 544, 0, 1, 1128, 844, 0, 1, 4)
4821 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\  argument
4822 	FIELD_PREP(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
4823 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\  argument
4824 	FIELD_GET(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
4827 #define QSYS_CAL_AUTO(r)          __REG(TARGET_QSYS, 0, 1, 2304, 0, 1, 40, 0, r, 7, 4)
4830 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\  argument
4831 	FIELD_PREP(QSYS_CAL_AUTO_CAL_AUTO, x)
4832 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\  argument
4833 	FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x)
4836 #define QSYS_CAL_CTRL             __REG(TARGET_QSYS, 0, 1, 2304, 0, 1, 40, 36, 0, 1, 4)
4839 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\  argument
4840 	FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x)
4841 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\  argument
4842 	FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x)
4845 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\  argument
4846 	FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
4847 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\  argument
4848 	FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
4851 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\  argument
4852 	FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
4853 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\  argument
4854 	FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
4857 #define QSYS_RAM_INIT             __REG(TARGET_QSYS, 0, 1, 2344, 0, 1, 4, 0, 0, 1, 4)
4860 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\  argument
4861 	FIELD_PREP(QSYS_RAM_INIT_RAM_INIT, x)
4862 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\  argument
4863 	FIELD_GET(QSYS_RAM_INIT_RAM_INIT, x)
4866 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
4867 	FIELD_PREP(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
4868 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
4869 	FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
4872 #define REW_OWN_UPSID(r)          __REG(TARGET_REW, 0, 1, 387264, 0, 1, 1232, 0, r, 3, 4)
4874 #define REW_OWN_UPSID_OWN_UPSID                  GENMASK(4, 0)
4875 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\  argument
4876 	FIELD_PREP(REW_OWN_UPSID_OWN_UPSID, x)
4877 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\  argument
4878 	FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x)
4881 #define REW_PORT_VLAN_CFG(g)      __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 0, 0, 1, 4)
4884 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\  argument
4885 	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_PCP, x)
4886 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\  argument
4887 	FIELD_GET(REW_PORT_VLAN_CFG_PORT_PCP, x)
4890 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\  argument
4891 	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_DEI, x)
4892 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\  argument
4893 	FIELD_GET(REW_PORT_VLAN_CFG_PORT_DEI, x)
4896 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\  argument
4897 	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x)
4898 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\  argument
4899 	FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x)
4902 #define REW_TAG_CTRL(g)           __REG(TARGET_REW, 0, 1, 360448, g, 70, 256, 132, 0, 1, 4)
4905 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\  argument
4906 	FIELD_PREP(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
4907 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\  argument
4908 	FIELD_GET(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
4911 #define REW_TAG_CTRL_TAG_CFG_SET(x)\  argument
4912 	FIELD_PREP(REW_TAG_CTRL_TAG_CFG, x)
4913 #define REW_TAG_CTRL_TAG_CFG_GET(x)\  argument
4914 	FIELD_GET(REW_TAG_CTRL_TAG_CFG, x)
4917 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\  argument
4918 	FIELD_PREP(REW_TAG_CTRL_TAG_TPID_CFG, x)
4919 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\  argument
4920 	FIELD_GET(REW_TAG_CTRL_TAG_TPID_CFG, x)
4923 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\  argument
4924 	FIELD_PREP(REW_TAG_CTRL_TAG_VID_CFG, x)
4925 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\  argument
4926 	FIELD_GET(REW_TAG_CTRL_TAG_VID_CFG, x)
4929 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\  argument
4930 	FIELD_PREP(REW_TAG_CTRL_TAG_PCP_CFG, x)
4931 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\  argument
4932 	FIELD_GET(REW_TAG_CTRL_TAG_PCP_CFG, x)
4935 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\  argument
4936 	FIELD_PREP(REW_TAG_CTRL_TAG_DEI_CFG, x)
4937 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\  argument
4938 	FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x)
4941 #define REW_PTP_TWOSTEP_CTRL      __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4)
4944 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\  argument
4945 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
4946 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\  argument
4947 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
4950 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\  argument
4951 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x)
4952 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\  argument
4953 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x)
4956 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\  argument
4957 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x)
4958 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\  argument
4959 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x)
4962 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\  argument
4963 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x)
4964 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\  argument
4965 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x)
4968 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\  argument
4969 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
4970 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\  argument
4971 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
4974 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\  argument
4975 	FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
4976 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\  argument
4977 	FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
4980 #define REW_PTP_TWOSTEP_STAMP     __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4)
4983 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\  argument
4984 	FIELD_PREP(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
4985 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\  argument
4986 	FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
4989 #define REW_PTP_TWOSTEP_STAMP_SUBNS __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4)
4992 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\  argument
4993 	FIELD_PREP(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
4994 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\  argument
4995 	FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
4998 #define REW_PTP_RSRV_NOT_ZERO     __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4)
5001 #define REW_PTP_RSRV_NOT_ZERO1    __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4)
5004 #define REW_PTP_RSRV_NOT_ZERO2    __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4)
5007 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\  argument
5008 	FIELD_PREP(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x)
5009 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\  argument
5010 	FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x)
5013 #define REW_PTP_GEN_STAMP_FMT(r)  __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 24, r, 4, 4)
5016 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\  argument
5017 	FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_OFS, x)
5018 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\  argument
5019 	FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_OFS, x)
5022 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\  argument
5023 	FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_FMT, x)
5024 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\  argument
5025 	FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x)
5028 #define REW_RAM_INIT              __REG(TARGET_REW, 0, 1, 378696, 0, 1, 4, 0, 0, 1, 4)
5031 #define REW_RAM_INIT_RAM_INIT_SET(x)\  argument
5032 	FIELD_PREP(REW_RAM_INIT_RAM_INIT, x)
5033 #define REW_RAM_INIT_RAM_INIT_GET(x)\  argument
5034 	FIELD_GET(REW_RAM_INIT_RAM_INIT, x)
5037 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
5038 	FIELD_PREP(REW_RAM_INIT_RAM_CFG_HOOK, x)
5039 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
5040 	FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x)
5043 #define VCAP_SUPER_RAM_INIT       __REG(TARGET_VCAP_SUPER, 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4)
5046 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\  argument
5047 	FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
5048 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\  argument
5049 	FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
5052 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
5053 	FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
5054 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
5055 	FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
5058 #define VOP_RAM_INIT              __REG(TARGET_VOP, 0, 1, 279176, 0, 1, 4, 0, 0, 1, 4)
5061 #define VOP_RAM_INIT_RAM_INIT_SET(x)\  argument
5062 	FIELD_PREP(VOP_RAM_INIT_RAM_INIT, x)
5063 #define VOP_RAM_INIT_RAM_INIT_GET(x)\  argument
5064 	FIELD_GET(VOP_RAM_INIT_RAM_INIT, x)
5067 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
5068 	FIELD_PREP(VOP_RAM_INIT_RAM_CFG_HOOK, x)
5069 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
5070 	FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x)
5073 #define XQS_STAT_CFG              __REG(TARGET_XQS, 0, 1, 6768, 0, 1, 872, 860, 0, 1, 4)
5076 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\  argument
5077 	FIELD_PREP(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
5078 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\  argument
5079 	FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
5082 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\  argument
5083 	FIELD_PREP(XQS_STAT_CFG_STAT_VIEW, x)
5084 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\  argument
5085 	FIELD_GET(XQS_STAT_CFG_STAT_VIEW, x)
5087 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY           BIT(4)
5088 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\  argument
5089 	FIELD_PREP(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
5090 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\  argument
5091 	FIELD_GET(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
5094 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\  argument
5095 	FIELD_PREP(XQS_STAT_CFG_STAT_WRAP_DIS, x)
5096 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\  argument
5097 	FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x)
5100 #define XQS_QLIMIT_SHR_TOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 0, 0, 1, 4)
5103 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\  argument
5104 	FIELD_PREP(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
5105 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\  argument
5106 	FIELD_GET(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
5109 #define XQS_QLIMIT_SHR_ATOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 4, 0, 1, 4)
5112 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\  argument
5113 	FIELD_PREP(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
5114 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\  argument
5115 	FIELD_GET(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
5118 #define XQS_QLIMIT_SHR_CTOP_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 8, 0, 1, 4)
5121 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\  argument
5122 	FIELD_PREP(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
5123 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\  argument
5124 	FIELD_GET(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
5127 #define XQS_QLIMIT_SHR_QLIM_CFG(g) __REG(TARGET_XQS, 0, 1, 7936, g, 4, 48, 12, 0, 1, 4)
5130 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\  argument
5131 	FIELD_PREP(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
5132 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\  argument
5133 	FIELD_GET(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
5136 #define XQS_CNT(g)                __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4)