61 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\  argument
63 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\  argument
67 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
69 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
76 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\  argument
78 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\  argument
91 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\  argument
93 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\  argument
106 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\  argument
108 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\  argument
115 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\  argument
117 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\  argument
121 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\  argument
123 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\  argument
127 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\  argument
129 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\  argument
136 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\  argument
138 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\  argument
145 #define ANA_AC_STAT_RESET_RESET_SET(x)\  argument
147 #define ANA_AC_STAT_RESET_RESET_GET(x)\  argument
154 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\  argument
156 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\  argument
160 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\  argument
162 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\  argument
166 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\  argument
168 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\  argument
178 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\  argument
180 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\  argument
187 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\  argument
189 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\  argument
196 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\  argument
198 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\  argument
202 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\  argument
204 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\  argument
208 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\  argument
210 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\  argument
214 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\  argument
216 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\  argument
223 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\  argument
225 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\  argument
229 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\  argument
231 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\  argument
235 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\  argument
237 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\  argument
241 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\  argument
243 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\  argument
250 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\  argument
252 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\  argument
256 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\  argument
258 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\  argument
262 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\  argument
264 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\  argument
271 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\  argument
273 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\  argument
277 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\  argument
279 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\  argument
283 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\  argument
285 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\  argument
289 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\  argument
291 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\  argument
295 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\  argument
297 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\  argument
301 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\  argument
303 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\  argument
307 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\  argument
309 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\  argument
313 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\  argument
315 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\  argument
319 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\  argument
321 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\  argument
325 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\  argument
327 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\  argument
331 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\  argument
333 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\  argument
340 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\  argument
342 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\  argument
346 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\  argument
348 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\  argument
355 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\  argument
357 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\  argument
361 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\  argument
363 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\  argument
367 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\  argument
369 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\  argument
373 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\  argument
375 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\  argument
379 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\  argument
381 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\  argument
385 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\  argument
387 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\  argument
391 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\  argument
393 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\  argument
397 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\  argument
399 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\  argument
403 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\  argument
405 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\  argument
409 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\  argument
411 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\  argument
415 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\  argument
417 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\  argument
424 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\  argument
426 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\  argument
436 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\  argument
438 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\  argument
451 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\  argument
453 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\  argument
460 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\  argument
462 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\  argument
469 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\  argument
471 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\  argument
478 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\  argument
480 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\  argument
484 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\  argument
486 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\  argument
490 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\  argument
492 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\  argument
496 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\  argument
498 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\  argument
502 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\  argument
504 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\  argument
508 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\  argument
510 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\  argument
514 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\  argument
516 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\  argument
520 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\  argument
522 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\  argument
526 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\  argument
528 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\  argument
541 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\  argument
543 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\  argument
817 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\  argument
819 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\  argument
826 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
828 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
835 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
837 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
844 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
846 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
853 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
855 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
862 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\  argument
864 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\  argument
871 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
873 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
880 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
882 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
892 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\  argument
894 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\  argument
901 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\  argument
903 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\  argument
907 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\  argument
909 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\  argument
913 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\  argument
915 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\  argument
919 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\  argument
921 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\  argument
925 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\  argument
927 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\  argument
931 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\  argument
933 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\  argument
937 #define ASM_PORT_CFG_PAD_ENA_SET(x)\  argument
939 #define ASM_PORT_CFG_PAD_ENA_GET(x)\  argument
943 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\  argument
945 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\  argument
949 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\  argument
951 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\  argument
955 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\  argument
957 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\  argument
961 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\  argument
963 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\  argument
970 #define ASM_RAM_INIT_RAM_INIT_SET(x)\  argument
972 #define ASM_RAM_INIT_RAM_INIT_GET(x)\  argument
976 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
978 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
985 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\  argument
987 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\  argument
991 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\  argument
993 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\  argument
997 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\  argument
999 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\  argument
1003 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\  argument
1005 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\  argument
1009 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\  argument
1011 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\  argument
1015 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\  argument
1017 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\  argument
1024 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\  argument
1026 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\  argument
1030 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\  argument
1032 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\  argument
1036 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\  argument
1038 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\  argument
1042 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\  argument
1044 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\  argument
1048 #define CPU_PROC_CTRL_VINITHI_SET(x)\  argument
1050 #define CPU_PROC_CTRL_VINITHI_GET(x)\  argument
1054 #define CPU_PROC_CTRL_CFGTE_SET(x)\  argument
1056 #define CPU_PROC_CTRL_CFGTE_GET(x)\  argument
1060 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\  argument
1062 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\  argument
1066 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\  argument
1068 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\  argument
1072 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\  argument
1074 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\  argument
1078 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\  argument
1080 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\  argument
1084 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\  argument
1086 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\  argument
1090 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\  argument
1092 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\  argument
1096 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\  argument
1098 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\  argument
1105 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
1107 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
1111 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
1113 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
1120 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
1122 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
1126 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
1128 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
1135 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\  argument
1137 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\  argument
1144 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\  argument
1146 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\  argument
1150 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\  argument
1152 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\  argument
1159 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
1161 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
1165 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
1167 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
1171 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
1173 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
1177 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
1179 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
1183 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
1185 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
1189 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
1191 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
1195 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
1197 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
1204 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\  argument
1206 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\  argument
1210 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\  argument
1212 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\  argument
1216 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\  argument
1218 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\  argument
1222 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\  argument
1224 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\  argument
1228 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\  argument
1230 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\  argument
1237 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
1239 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
1243 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
1245 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
1249 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
1251 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
1255 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
1257 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
1261 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
1263 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
1267 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
1269 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
1273 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
1275 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
1279 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
1281 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
1285 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
1287 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
1294 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\  argument
1296 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\  argument
1303 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
1305 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
1309 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
1311 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
1318 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
1320 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
1324 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
1326 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
1333 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
1335 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
1339 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
1341 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
1345 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
1347 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
1351 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
1353 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
1357 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
1359 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
1363 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
1365 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
1369 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
1371 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
1378 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
1380 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
1384 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
1386 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
1390 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
1392 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
1396 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
1398 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
1402 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
1404 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
1408 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
1410 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
1414 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
1416 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
1420 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
1422 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
1426 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
1428 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
1435 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\  argument
1437 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\  argument
1444 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\  argument
1446 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\  argument
1450 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\  argument
1452 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\  argument
1456 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\  argument
1458 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\  argument
1465 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
1467 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
1471 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
1473 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
1477 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\  argument
1479 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\  argument
1483 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\  argument
1485 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\  argument
1489 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
1491 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
1495 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
1497 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
1501 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
1503 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
1507 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
1509 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
1516 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
1518 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
1522 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
1524 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
1531 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\  argument
1533 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\  argument
1537 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\  argument
1539 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\  argument
1543 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\  argument
1545 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\  argument
1552 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
1554 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
1561 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\  argument
1563 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\  argument
1567 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\  argument
1569 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\  argument
1573 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\  argument
1575 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\  argument
1579 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\  argument
1581 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\  argument
1588 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\  argument
1590 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\  argument
1594 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\  argument
1596 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\  argument
1603 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\  argument
1605 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\  argument
1612 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\  argument
1614 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\  argument
1618 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\  argument
1620 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\  argument
1624 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\  argument
1626 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\  argument
1630 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\  argument
1632 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\  argument
1639 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\  argument
1641 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\  argument
1645 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\  argument
1647 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\  argument
1651 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\  argument
1653 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\  argument
1657 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\  argument
1659 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\  argument
1663 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\  argument
1665 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\  argument
1672 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\  argument
1674 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\  argument
1678 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
1680 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
1684 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\  argument
1686 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\  argument
1693 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\  argument
1695 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\  argument
1699 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\  argument
1701 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\  argument
1705 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\  argument
1707 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\  argument
1714 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\  argument
1716 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\  argument
1720 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\  argument
1722 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\  argument
1726 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\  argument
1728 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\  argument
1735 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\  argument
1737 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\  argument
1741 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\  argument
1743 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\  argument
1747 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\  argument
1749 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\  argument
1753 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\  argument
1755 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\  argument
1762 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\  argument
1764 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\  argument
1768 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\  argument
1770 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\  argument
1774 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\  argument
1776 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\  argument
1783 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\  argument
1785 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\  argument
1789 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\  argument
1791 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\  argument
1795 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\  argument
1797 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\  argument
1801 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\  argument
1803 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\  argument
1810 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\  argument
1812 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\  argument
1816 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\  argument
1818 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\  argument
1822 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\  argument
1824 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\  argument
1828 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\  argument
1830 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\  argument
1837 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\  argument
1839 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\  argument
1843 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\  argument
1845 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\  argument
1852 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\  argument
1854 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\  argument
1858 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\  argument
1860 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\  argument
1864 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\  argument
1866 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\  argument
1870 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\  argument
1872 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\  argument
1876 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\  argument
1878 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\  argument
1882 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\  argument
1884 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\  argument
1888 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\  argument
1890 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\  argument
1894 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\  argument
1896 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\  argument
1900 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\  argument
1902 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\  argument
1906 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\  argument
1908 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\  argument
1912 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\  argument
1914 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\  argument
1918 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\  argument
1920 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\  argument
1924 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\  argument
1926 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\  argument
1933 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\  argument
1935 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\  argument
1939 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\  argument
1941 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\  argument
1945 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\  argument
1947 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\  argument
1951 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\  argument
1953 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\  argument
1957 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\  argument
1959 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\  argument
1963 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\  argument
1965 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\  argument
1969 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\  argument
1971 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\  argument
1975 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\  argument
1977 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\  argument
1984 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
1986 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
1990 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
1992 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
1999 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\  argument
2001 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\  argument
2005 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
2007 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
2014 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\  argument
2016 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\  argument
2020 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\  argument
2022 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\  argument
2026 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\  argument
2028 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\  argument
2032 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\  argument
2034 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\  argument
2038 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\  argument
2040 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\  argument
2044 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\  argument
2046 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\  argument
2050 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\  argument
2052 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\  argument
2298 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\  argument
2300 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\  argument
2310 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
2312 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
2322 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
2324 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
2334 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\  argument
2336 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\  argument
2346 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
2348 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
2358 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\  argument
2360 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\  argument
2370 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\  argument
2372 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\  argument
2382 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\  argument
2384 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\  argument
2391 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\  argument
2393 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\  argument
2397 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\  argument
2399 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\  argument
2403 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\  argument
2405 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\  argument
2409 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\  argument
2411 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\  argument
2415 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\  argument
2417 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\  argument
2421 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\  argument
2423 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\  argument
2427 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\  argument
2429 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\  argument
2433 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\  argument
2435 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\  argument
2439 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\  argument
2441 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\  argument
2448 #define DSM_RAM_INIT_RAM_INIT_SET(x)\  argument
2450 #define DSM_RAM_INIT_RAM_INIT_GET(x)\  argument
2454 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
2456 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
2463 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\  argument
2465 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\  argument
2469 #define DSM_BUF_CFG_AGING_ENA_SET(x)\  argument
2471 #define DSM_BUF_CFG_AGING_ENA_GET(x)\  argument
2475 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\  argument
2477 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\  argument
2481 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\  argument
2483 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\  argument
2490 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\  argument
2492 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\  argument
2496 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\  argument
2498 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\  argument
2502 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\  argument
2504 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\  argument
2508 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\  argument
2510 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\  argument
2517 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\  argument
2519 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\  argument
2523 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\  argument
2525 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\  argument
2532 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\  argument
2534 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\  argument
2538 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\  argument
2540 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\  argument
2544 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\  argument
2546 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\  argument
2550 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\  argument
2552 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\  argument
2559 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\  argument
2561 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\  argument
2568 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\  argument
2570 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\  argument
2577 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\  argument
2579 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\  argument
2583 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\  argument
2585 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\  argument
2589 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\  argument
2591 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\  argument
2595 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\  argument
2597 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\  argument
2601 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\  argument
2603 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\  argument
2610 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\  argument
2612 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\  argument
2616 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\  argument
2618 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\  argument
2622 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\  argument
2624 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\  argument
2628 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\  argument
2630 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\  argument
2634 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\  argument
2636 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\  argument
2640 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\  argument
2642 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\  argument
2649 #define EACL_RAM_INIT_RAM_INIT_SET(x)\  argument
2651 #define EACL_RAM_INIT_RAM_INIT_GET(x)\  argument
2655 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
2657 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
2664 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\  argument
2666 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\  argument
2673 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\  argument
2675 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\  argument
2682 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\  argument
2684 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\  argument
2703 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\  argument
2705 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\  argument
2709 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\  argument
2711 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\  argument
2715 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\  argument
2717 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\  argument
2721 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\  argument
2723 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\  argument
2727 #define FDMA_CH_CFG_CH_MEM_SET(x)\  argument
2729 #define FDMA_CH_CFG_CH_MEM_GET(x)\  argument
2736 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\  argument
2738 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\  argument
2745 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\  argument
2747 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\  argument
2751 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\  argument
2753 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\  argument
2760 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\  argument
2762 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\  argument
2766 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\  argument
2768 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\  argument
2772 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\  argument
2774 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\  argument
2778 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\  argument
2780 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\  argument
2784 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\  argument
2786 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\  argument
2793 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\  argument
2795 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\  argument
2802 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\  argument
2804 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\  argument
2811 #define FDMA_INTR_DB_INTR_DB_SET(x)\  argument
2813 #define FDMA_INTR_DB_INTR_DB_GET(x)\  argument
2820 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\  argument
2822 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\  argument
2829 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\  argument
2831 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\  argument
2835 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\  argument
2837 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\  argument
2844 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\  argument
2846 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\  argument
2850 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\  argument
2852 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\  argument
2856 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\  argument
2858 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\  argument
2862 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\  argument
2864 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\  argument
2868 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\  argument
2870 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\  argument
2874 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\  argument
2876 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\  argument
2880 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\  argument
2882 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\  argument
2886 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\  argument
2888 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\  argument
2895 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\  argument
2897 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\  argument
2904 #define FDMA_CTRL_NRESET_SET(x)\  argument
2906 #define FDMA_CTRL_NRESET_GET(x)\  argument
2913 #define GCB_CHIP_ID_REV_ID_SET(x)\  argument
2915 #define GCB_CHIP_ID_REV_ID_GET(x)\  argument
2919 #define GCB_CHIP_ID_PART_ID_SET(x)\  argument
2921 #define GCB_CHIP_ID_PART_ID_GET(x)\  argument
2925 #define GCB_CHIP_ID_MFG_ID_SET(x)\  argument
2927 #define GCB_CHIP_ID_MFG_ID_GET(x)\  argument
2931 #define GCB_CHIP_ID_ONE_SET(x)\  argument
2933 #define GCB_CHIP_ID_ONE_GET(x)\  argument
2940 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\  argument
2942 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\  argument
2946 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\  argument
2948 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\  argument
2952 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\  argument
2954 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\  argument
2961 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\  argument
2963 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\  argument
2967 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\  argument
2969 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\  argument
2976 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\  argument
2978 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\  argument
2985 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\  argument
2987 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\  argument
2991 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\  argument
2993 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\  argument
3000 #define HSCH_CIR_CFG_CIR_RATE_SET(x)\  argument
3002 #define HSCH_CIR_CFG_CIR_RATE_GET(x)\  argument
3006 #define HSCH_CIR_CFG_CIR_BURST_SET(x)\  argument
3008 #define HSCH_CIR_CFG_CIR_BURST_GET(x)\  argument
3015 #define HSCH_EIR_CFG_EIR_RATE_SET(x)\  argument
3017 #define HSCH_EIR_CFG_EIR_RATE_GET(x)\  argument
3021 #define HSCH_EIR_CFG_EIR_BURST_SET(x)\  argument
3023 #define HSCH_EIR_CFG_EIR_BURST_GET(x)\  argument
3030 #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\  argument
3032 #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\  argument
3036 #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\  argument
3038 #define HSCH_SE_CFG_SE_AVB_ENA_GET(x)\  argument
3042 #define HSCH_SE_CFG_SE_FRM_MODE_SET(x)\  argument
3044 #define HSCH_SE_CFG_SE_FRM_MODE_GET(x)\  argument
3048 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_SET(x)\  argument
3050 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_GET(x)\  argument
3054 #define HSCH_SE_CFG_SE_STOP_SET(x)\  argument
3056 #define HSCH_SE_CFG_SE_STOP_GET(x)\  argument
3063 #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\  argument
3065 #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\  argument
3072 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\  argument
3074 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\  argument
3078 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\  argument
3080 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\  argument
3084 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\  argument
3086 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_GET(x)\  argument
3090 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_SET(x)\  argument
3092 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_GET(x)\  argument
3096 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_SET(x)\  argument
3098 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\  argument
3105 #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\  argument
3107 #define HSCH_DWRR_ENTRY_DWRR_COST_GET(x)\  argument
3111 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x)\  argument
3113 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\  argument
3120 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\  argument
3122 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\  argument
3126 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\  argument
3128 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_GET(x)\  argument
3132 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_SET(x)\  argument
3134 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\  argument
3141 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_SET(x)\  argument
3143 #define HSCH_SYS_CLK_PER_SYS_CLK_PER_100PS_GET(x)\  argument
3150 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\  argument
3152 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\  argument
3159 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\  argument
3161 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\  argument
3165 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\  argument
3167 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\  argument
3174 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\  argument
3176 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\  argument
3180 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\  argument
3182 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\  argument
3186 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\  argument
3188 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\  argument
3192 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\  argument
3194 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\  argument
3198 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\  argument
3200 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\  argument
3204 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\  argument
3206 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\  argument
3210 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\  argument
3212 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\  argument
3219 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\  argument
3221 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\  argument
3225 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\  argument
3227 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\  argument
3231 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\  argument
3233 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\  argument
3237 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\  argument
3239 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\  argument
3243 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\  argument
3245 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\  argument
3252 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\  argument
3254 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\  argument
3261 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\  argument
3263 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\  argument
3270 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\  argument
3272 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\  argument
3279 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\  argument
3281 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\  argument
3285 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\  argument
3287 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\  argument
3291 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\  argument
3293 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\  argument
3297 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\  argument
3299 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\  argument
3303 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\  argument
3305 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\  argument
3312 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\  argument
3314 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\  argument
3318 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\  argument
3320 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\  argument
3330 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\  argument
3332 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\  argument
3336 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\  argument
3338 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\  argument
3342 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\  argument
3344 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\  argument
3348 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\  argument
3350 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\  argument
3354 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\  argument
3356 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\  argument
3360 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\  argument
3362 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\  argument
3366 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\  argument
3368 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\  argument
3372 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\  argument
3374 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\  argument
3378 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\  argument
3380 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\  argument
3384 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\  argument
3386 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\  argument
3390 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\  argument
3392 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\  argument
3396 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\  argument
3398 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\  argument
3405 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\  argument
3407 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\  argument
3414 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\  argument
3416 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\  argument
3420 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\  argument
3422 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\  argument
3426 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\  argument
3428 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\  argument
3432 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\  argument
3434 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\  argument
3438 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\  argument
3440 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\  argument
3444 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\  argument
3446 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\  argument
3450 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\  argument
3452 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\  argument
3456 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\  argument
3458 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\  argument
3462 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\  argument
3464 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\  argument
3468 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\  argument
3470 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\  argument
3474 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\  argument
3476 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\  argument
3480 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\  argument
3482 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\  argument
3486 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\  argument
3488 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\  argument
3492 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\  argument
3494 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\  argument
3498 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\  argument
3500 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\  argument
3507 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\  argument
3509 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\  argument
3513 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\  argument
3515 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\  argument
3522 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\  argument
3524 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\  argument
3528 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\  argument
3530 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\  argument
3537 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\  argument
3539 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\  argument
3543 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\  argument
3545 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\  argument
3549 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\  argument
3551 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\  argument
3555 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\  argument
3557 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\  argument
3561 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\  argument
3563 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\  argument
3567 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\  argument
3569 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\  argument
3573 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\  argument
3575 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\  argument
3582 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\  argument
3584 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\  argument
3588 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\  argument
3590 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\  argument
3597 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\  argument
3599 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\  argument
3603 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\  argument
3605 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\  argument
3609 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\  argument
3611 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\  argument
3615 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\  argument
3617 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\  argument
3621 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\  argument
3623 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\  argument
3627 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\  argument
3629 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\  argument
3633 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\  argument
3635 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\  argument
3639 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\  argument
3641 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\  argument
3645 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\  argument
3647 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\  argument
3651 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\  argument
3653 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\  argument
3660 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\  argument
3662 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\  argument
3666 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\  argument
3668 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\  argument
3678 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\  argument
3680 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\  argument
3684 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\  argument
3686 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\  argument
3699 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\  argument
3701 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\  argument
3705 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\  argument
3707 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\  argument
3714 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
3716 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
3720 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
3722 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
3726 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
3728 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
3732 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
3734 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
3738 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
3740 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
3744 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
3746 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
3750 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
3752 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
3756 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
3758 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
3762 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
3764 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
3768 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
3770 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
3774 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
3776 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
3780 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
3782 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
3789 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
3791 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
3795 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
3797 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
3801 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
3803 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
3810 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
3812 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
3816 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
3818 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
3822 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
3824 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
3828 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
3830 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
3834 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
3836 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
3840 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
3842 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
3846 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
3848 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
3852 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
3854 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
3858 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
3860 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
3864 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
3866 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
3870 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
3872 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
3876 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
3878 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
3885 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
3887 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
3891 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
3893 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
3897 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
3899 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
3906 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\  argument
3908 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\  argument
3912 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\  argument
3914 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\  argument
3918 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\  argument
3920 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\  argument
3924 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\  argument
3926 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\  argument
3930 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\  argument
3932 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\  argument
3936 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\  argument
3938 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\  argument
3942 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\  argument
3944 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\  argument
3948 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\  argument
3950 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\  argument
3954 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\  argument
3956 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\  argument
3960 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\  argument
3962 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\  argument
3966 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\  argument
3968 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\  argument
3972 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\  argument
3974 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\  argument
3981 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\  argument
3983 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\  argument
3987 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\  argument
3989 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\  argument
3993 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\  argument
3995 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\  argument
4002 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\  argument
4004 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\  argument
4008 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\  argument
4010 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\  argument
4014 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\  argument
4016 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\  argument
4020 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\  argument
4022 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\  argument
4026 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\  argument
4028 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\  argument
4032 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\  argument
4034 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\  argument
4038 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\  argument
4040 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\  argument
4044 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\  argument
4046 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\  argument
4050 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\  argument
4052 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\  argument
4056 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\  argument
4058 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\  argument
4062 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\  argument
4064 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\  argument
4068 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\  argument
4070 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\  argument
4074 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\  argument
4076 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\  argument
4083 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\  argument
4085 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\  argument
4089 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\  argument
4091 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\  argument
4095 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\  argument
4097 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\  argument
4101 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\  argument
4103 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\  argument
4107 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\  argument
4109 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\  argument
4113 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\  argument
4115 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\  argument
4119 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\  argument
4121 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\  argument
4125 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\  argument
4127 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\  argument
4131 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\  argument
4133 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\  argument
4137 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\  argument
4139 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\  argument
4143 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\  argument
4145 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\  argument
4149 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\  argument
4151 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\  argument
4158 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\  argument
4160 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\  argument
4164 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\  argument
4166 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\  argument
4170 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\  argument
4172 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\  argument
4176 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\  argument
4178 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\  argument
4182 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\  argument
4184 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\  argument
4188 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\  argument
4190 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\  argument
4194 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\  argument
4196 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\  argument
4200 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\  argument
4202 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\  argument
4209 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\  argument
4211 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\  argument
4215 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\  argument
4217 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\  argument
4221 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\  argument
4223 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\  argument
4227 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\  argument
4229 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\  argument
4233 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\  argument
4235 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\  argument
4239 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\  argument
4241 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\  argument
4245 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\  argument
4247 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\  argument
4251 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\  argument
4253 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\  argument
4257 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\  argument
4259 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\  argument
4263 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\  argument
4265 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\  argument
4269 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\  argument
4271 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\  argument
4275 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\  argument
4277 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\  argument
4284 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\  argument
4286 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\  argument
4290 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\  argument
4292 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\  argument
4296 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\  argument
4298 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\  argument
4302 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\  argument
4304 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\  argument
4308 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\  argument
4310 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\  argument
4314 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\  argument
4316 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\  argument
4320 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\  argument
4322 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\  argument
4329 #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\  argument
4331 #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\  argument
4338 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\  argument
4340 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\  argument
4347 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\  argument
4349 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\  argument
4356 #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\  argument
4358 #define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\  argument
4362 #define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\  argument
4364 #define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\  argument
4368 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\  argument
4370 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\  argument
4374 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\  argument
4376 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\  argument
4386 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\  argument
4388 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\  argument
4395 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\  argument
4397 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\  argument
4407 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\  argument
4409 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\  argument
4419 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\  argument
4421 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\  argument
4425 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\  argument
4427 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\  argument
4431 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\  argument
4433 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\  argument
4437 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\  argument
4439 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\  argument
4443 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\  argument
4445 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\  argument
4449 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\  argument
4451 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\  argument
4455 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\  argument
4457 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\  argument
4461 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\  argument
4463 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\  argument
4467 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\  argument
4469 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\  argument
4476 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\  argument
4478 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\  argument
4488 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\  argument
4490 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\  argument
4497 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\  argument
4499 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\  argument
4509 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\  argument
4511 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\  argument
4518 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\  argument
4520 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\  argument
4527 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\  argument
4529 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\  argument
4533 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\  argument
4535 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\  argument
4542 #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\  argument
4544 #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\  argument
4548 #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\  argument
4550 #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\  argument
4554 #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\  argument
4556 #define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\  argument
4560 #define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\  argument
4562 #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\  argument
4572 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\  argument
4574 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\  argument
4578 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\  argument
4580 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\  argument
4584 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\  argument
4586 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\  argument
4590 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\  argument
4592 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\  argument
4596 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\  argument
4598 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\  argument
4602 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\  argument
4604 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\  argument
4608 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\  argument
4610 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\  argument
4614 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\  argument
4616 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\  argument
4620 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\  argument
4622 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\  argument
4629 #define QRES_RES_CFG_WM_HIGH_SET(x)\  argument
4631 #define QRES_RES_CFG_WM_HIGH_GET(x)\  argument
4638 #define QRES_RES_STAT_MAXUSE_SET(x)\  argument
4640 #define QRES_RES_STAT_MAXUSE_GET(x)\  argument
4647 #define QRES_RES_STAT_CUR_INUSE_SET(x)\  argument
4649 #define QRES_RES_STAT_CUR_INUSE_GET(x)\  argument
4656 #define QS_XTR_GRP_CFG_MODE_SET(x)\  argument
4658 #define QS_XTR_GRP_CFG_MODE_GET(x)\  argument
4662 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\  argument
4664 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\  argument
4668 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\  argument
4670 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\  argument
4680 #define QS_XTR_FLUSH_FLUSH_SET(x)\  argument
4682 #define QS_XTR_FLUSH_FLUSH_GET(x)\  argument
4689 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\  argument
4691 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\  argument
4698 #define QS_INJ_GRP_CFG_MODE_SET(x)\  argument
4700 #define QS_INJ_GRP_CFG_MODE_GET(x)\  argument
4704 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\  argument
4706 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\  argument
4716 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\  argument
4718 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\  argument
4722 #define QS_INJ_CTRL_ABORT_SET(x)\  argument
4724 #define QS_INJ_CTRL_ABORT_GET(x)\  argument
4728 #define QS_INJ_CTRL_EOF_SET(x)\  argument
4730 #define QS_INJ_CTRL_EOF_GET(x)\  argument
4734 #define QS_INJ_CTRL_SOF_SET(x)\  argument
4736 #define QS_INJ_CTRL_SOF_GET(x)\  argument
4740 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\  argument
4742 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\  argument
4749 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\  argument
4751 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\  argument
4755 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\  argument
4757 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\  argument
4761 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\  argument
4763 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\  argument
4770 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\  argument
4772 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\  argument
4776 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\  argument
4778 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\  argument
4782 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\  argument
4784 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\  argument
4788 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\  argument
4790 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\  argument
4797 #define QSYS_ATOP_ATOP_SET(x)\  argument
4799 #define QSYS_ATOP_ATOP_GET(x)\  argument
4806 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\  argument
4808 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\  argument
4812 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\  argument
4814 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\  argument
4821 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\  argument
4823 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\  argument
4830 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\  argument
4832 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\  argument
4839 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\  argument
4841 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\  argument
4845 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\  argument
4847 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\  argument
4851 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\  argument
4853 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\  argument
4860 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\  argument
4862 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\  argument
4866 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
4868 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
4875 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\  argument
4877 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\  argument
4884 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\  argument
4886 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\  argument
4890 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\  argument
4892 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\  argument
4896 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\  argument
4898 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\  argument
4905 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\  argument
4907 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\  argument
4911 #define REW_TAG_CTRL_TAG_CFG_SET(x)\  argument
4913 #define REW_TAG_CTRL_TAG_CFG_GET(x)\  argument
4917 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\  argument
4919 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\  argument
4923 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\  argument
4925 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\  argument
4929 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\  argument
4931 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\  argument
4935 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\  argument
4937 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\  argument
4944 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\  argument
4946 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\  argument
4950 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\  argument
4952 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\  argument
4956 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\  argument
4958 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\  argument
4962 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\  argument
4964 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\  argument
4968 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\  argument
4970 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\  argument
4974 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\  argument
4976 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\  argument
4983 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\  argument
4985 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\  argument
4992 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\  argument
4994 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\  argument
5007 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\  argument
5009 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\  argument
5016 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\  argument
5018 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\  argument
5022 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\  argument
5024 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\  argument
5031 #define REW_RAM_INIT_RAM_INIT_SET(x)\  argument
5033 #define REW_RAM_INIT_RAM_INIT_GET(x)\  argument
5037 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
5039 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
5046 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\  argument
5048 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\  argument
5052 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
5054 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
5061 #define VOP_RAM_INIT_RAM_INIT_SET(x)\  argument
5063 #define VOP_RAM_INIT_RAM_INIT_GET(x)\  argument
5067 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\  argument
5069 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\  argument
5076 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\  argument
5078 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\  argument
5082 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\  argument
5084 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\  argument
5088 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\  argument
5090 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\  argument
5094 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\  argument
5096 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\  argument
5103 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\  argument
5105 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\  argument
5112 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\  argument
5114 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\  argument
5121 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\  argument
5123 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\  argument
5130 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\  argument
5132 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\  argument