37 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\  argument
38 	FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
39 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\  argument
40 	FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x)
46 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\  argument
47 	FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
48 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\  argument
49 	FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x)
52 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\  argument
53 	FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x)
54 #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\  argument
55 	FIELD_GET(AFI_PORT_CFG_FRM_OUT_MAX, x)
61 #define ANA_ADVLEARN_VLAN_CHK_SET(x)\  argument
62 	FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x)
63 #define ANA_ADVLEARN_VLAN_CHK_GET(x)\  argument
64 	FIELD_GET(ANA_ADVLEARN_VLAN_CHK, x)
73 #define ANA_ANAINTR_INTR_SET(x)\  argument
74 	FIELD_PREP(ANA_ANAINTR_INTR, x)
75 #define ANA_ANAINTR_INTR_GET(x)\  argument
76 	FIELD_GET(ANA_ANAINTR_INTR, x)
79 #define ANA_ANAINTR_INTR_ENA_SET(x)\  argument
80 	FIELD_PREP(ANA_ANAINTR_INTR_ENA, x)
81 #define ANA_ANAINTR_INTR_ENA_GET(x)\  argument
82 	FIELD_GET(ANA_ANAINTR_INTR_ENA, x)
88 #define ANA_AUTOAGE_AGE_PERIOD_SET(x)\  argument
89 	FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x)
90 #define ANA_AUTOAGE_AGE_PERIOD_GET(x)\  argument
91 	FIELD_GET(ANA_AUTOAGE_AGE_PERIOD, x)
97 #define ANA_MIRRORPORTS_MIRRORPORTS_SET(x)\  argument
98 	FIELD_PREP(ANA_MIRRORPORTS_MIRRORPORTS, x)
99 #define ANA_MIRRORPORTS_MIRRORPORTS_GET(x)\  argument
100 	FIELD_GET(ANA_MIRRORPORTS_MIRRORPORTS, x)
106 #define ANA_EMIRRORPORTS_EMIRRORPORTS_SET(x)\  argument
107 	FIELD_PREP(ANA_EMIRRORPORTS_EMIRRORPORTS, x)
108 #define ANA_EMIRRORPORTS_EMIRRORPORTS_GET(x)\  argument
109 	FIELD_GET(ANA_EMIRRORPORTS_EMIRRORPORTS, x)
115 #define ANA_FLOODING_FLD_UNICAST_SET(x)\  argument
116 	FIELD_PREP(ANA_FLOODING_FLD_UNICAST, x)
117 #define ANA_FLOODING_FLD_UNICAST_GET(x)\  argument
118 	FIELD_GET(ANA_FLOODING_FLD_UNICAST, x)
121 #define ANA_FLOODING_FLD_BROADCAST_SET(x)\  argument
122 	FIELD_PREP(ANA_FLOODING_FLD_BROADCAST, x)
123 #define ANA_FLOODING_FLD_BROADCAST_GET(x)\  argument
124 	FIELD_GET(ANA_FLOODING_FLD_BROADCAST, x)
127 #define ANA_FLOODING_FLD_MULTICAST_SET(x)\  argument
128 	FIELD_PREP(ANA_FLOODING_FLD_MULTICAST, x)
129 #define ANA_FLOODING_FLD_MULTICAST_GET(x)\  argument
130 	FIELD_GET(ANA_FLOODING_FLD_MULTICAST, x)
136 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\  argument
137 	FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x)
138 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\  argument
139 	FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x)
142 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\  argument
143 	FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_DATA, x)
144 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\  argument
145 	FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_DATA, x)
148 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\  argument
149 	FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x)
150 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\  argument
151 	FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x)
154 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\  argument
155 	FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_DATA, x)
156 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\  argument
157 	FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_DATA, x)
163 #define ANA_PGID_PGID_SET(x)\  argument
164 	FIELD_PREP(ANA_PGID_PGID, x)
165 #define ANA_PGID_PGID_GET(x)\  argument
166 	FIELD_GET(ANA_PGID_PGID, x)
172 #define ANA_PGID_CFG_OBEY_VLAN_SET(x)\  argument
173 	FIELD_PREP(ANA_PGID_CFG_OBEY_VLAN, x)
174 #define ANA_PGID_CFG_OBEY_VLAN_GET(x)\  argument
175 	FIELD_GET(ANA_PGID_CFG_OBEY_VLAN, x)
187 #define ANA_MACACCESS_CHANGE2SW_SET(x)\  argument
188 	FIELD_PREP(ANA_MACACCESS_CHANGE2SW, x)
189 #define ANA_MACACCESS_CHANGE2SW_GET(x)\  argument
190 	FIELD_GET(ANA_MACACCESS_CHANGE2SW, x)
193 #define ANA_MACACCESS_MAC_CPU_COPY_SET(x)\  argument
194 	FIELD_PREP(ANA_MACACCESS_MAC_CPU_COPY, x)
195 #define ANA_MACACCESS_MAC_CPU_COPY_GET(x)\  argument
196 	FIELD_GET(ANA_MACACCESS_MAC_CPU_COPY, x)
199 #define ANA_MACACCESS_VALID_SET(x)\  argument
200 	FIELD_PREP(ANA_MACACCESS_VALID, x)
201 #define ANA_MACACCESS_VALID_GET(x)\  argument
202 	FIELD_GET(ANA_MACACCESS_VALID, x)
205 #define ANA_MACACCESS_ENTRYTYPE_SET(x)\  argument
206 	FIELD_PREP(ANA_MACACCESS_ENTRYTYPE, x)
207 #define ANA_MACACCESS_ENTRYTYPE_GET(x)\  argument
208 	FIELD_GET(ANA_MACACCESS_ENTRYTYPE, x)
211 #define ANA_MACACCESS_DEST_IDX_SET(x)\  argument
212 	FIELD_PREP(ANA_MACACCESS_DEST_IDX, x)
213 #define ANA_MACACCESS_DEST_IDX_GET(x)\  argument
214 	FIELD_GET(ANA_MACACCESS_DEST_IDX, x)
217 #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\  argument
218 	FIELD_PREP(ANA_MACACCESS_MAC_TABLE_CMD, x)
219 #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\  argument
220 	FIELD_GET(ANA_MACACCESS_MAC_TABLE_CMD, x)
226 #define ANA_MACTINDX_BUCKET_SET(x)\  argument
227 	FIELD_PREP(ANA_MACTINDX_BUCKET, x)
228 #define ANA_MACTINDX_BUCKET_GET(x)\  argument
229 	FIELD_GET(ANA_MACTINDX_BUCKET, x)
232 #define ANA_MACTINDX_M_INDEX_SET(x)\  argument
233 	FIELD_PREP(ANA_MACTINDX_M_INDEX, x)
234 #define ANA_MACTINDX_M_INDEX_GET(x)\  argument
235 	FIELD_GET(ANA_MACTINDX_M_INDEX, x)
241 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x)\  argument
242 	FIELD_PREP(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x)
243 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x)\  argument
244 	FIELD_GET(ANA_VLAN_PORT_MASK_VLAN_PORT_MASK, x)
250 #define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x)\  argument
251 	FIELD_PREP(ANA_VLANACCESS_VLAN_TBL_CMD, x)
252 #define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x)\  argument
253 	FIELD_GET(ANA_VLANACCESS_VLAN_TBL_CMD, x)
259 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x)\  argument
260 	FIELD_PREP(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x)
261 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x)\  argument
262 	FIELD_GET(ANA_VLANTIDX_VLAN_PGID_CPU_DIS, x)
265 #define ANA_VLANTIDX_V_INDEX_SET(x)\  argument
266 	FIELD_PREP(ANA_VLANTIDX_V_INDEX, x)
267 #define ANA_VLANTIDX_V_INDEX_GET(x)\  argument
268 	FIELD_GET(ANA_VLANTIDX_V_INDEX, x)
274 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x)\  argument
275 	FIELD_PREP(ANA_VLAN_CFG_VLAN_AWARE_ENA, x)
276 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x)\  argument
277 	FIELD_GET(ANA_VLAN_CFG_VLAN_AWARE_ENA, x)
280 #define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x)\  argument
281 	FIELD_PREP(ANA_VLAN_CFG_VLAN_POP_CNT, x)
282 #define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\  argument
283 	FIELD_GET(ANA_VLAN_CFG_VLAN_POP_CNT, x)
286 #define ANA_VLAN_CFG_VLAN_VID_SET(x)\  argument
287 	FIELD_PREP(ANA_VLAN_CFG_VLAN_VID, x)
288 #define ANA_VLAN_CFG_VLAN_VID_GET(x)\  argument
289 	FIELD_GET(ANA_VLAN_CFG_VLAN_VID, x)
295 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x)\  argument
296 	FIELD_PREP(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x)
297 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x)\  argument
298 	FIELD_GET(ANA_DROP_CFG_DROP_UNTAGGED_ENA, x)
301 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x)\  argument
302 	FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x)
303 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x)\  argument
304 	FIELD_GET(ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA, x)
307 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x)\  argument
308 	FIELD_PREP(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x)
309 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x)\  argument
310 	FIELD_GET(ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, x)
313 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x)\  argument
314 	FIELD_PREP(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x)
315 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\  argument
316 	FIELD_GET(ANA_DROP_CFG_DROP_MC_SMAC_ENA, x)
322 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_SET(x)\  argument
323 	FIELD_PREP(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x)
324 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_GET(x)\  argument
325 	FIELD_GET(ANA_CPU_FWD_CFG_MLD_REDIR_ENA, x)
328 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(x)\  argument
329 	FIELD_PREP(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x)
330 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_GET(x)\  argument
331 	FIELD_GET(ANA_CPU_FWD_CFG_IGMP_REDIR_ENA, x)
334 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_SET(x)\  argument
335 	FIELD_PREP(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x)
336 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_GET(x)\  argument
337 	FIELD_GET(ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA, x)
340 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\  argument
341 	FIELD_PREP(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x)
342 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\  argument
343 	FIELD_GET(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x)
352 #define ANA_PORT_CFG_SRC_MIRROR_ENA_SET(x)\  argument
353 	FIELD_PREP(ANA_PORT_CFG_SRC_MIRROR_ENA, x)
354 #define ANA_PORT_CFG_SRC_MIRROR_ENA_GET(x)\  argument
355 	FIELD_GET(ANA_PORT_CFG_SRC_MIRROR_ENA, x)
358 #define ANA_PORT_CFG_LEARNAUTO_SET(x)\  argument
359 	FIELD_PREP(ANA_PORT_CFG_LEARNAUTO, x)
360 #define ANA_PORT_CFG_LEARNAUTO_GET(x)\  argument
361 	FIELD_GET(ANA_PORT_CFG_LEARNAUTO, x)
364 #define ANA_PORT_CFG_LEARN_ENA_SET(x)\  argument
365 	FIELD_PREP(ANA_PORT_CFG_LEARN_ENA, x)
366 #define ANA_PORT_CFG_LEARN_ENA_GET(x)\  argument
367 	FIELD_GET(ANA_PORT_CFG_LEARN_ENA, x)
370 #define ANA_PORT_CFG_RECV_ENA_SET(x)\  argument
371 	FIELD_PREP(ANA_PORT_CFG_RECV_ENA, x)
372 #define ANA_PORT_CFG_RECV_ENA_GET(x)\  argument
373 	FIELD_GET(ANA_PORT_CFG_RECV_ENA, x)
376 #define ANA_PORT_CFG_PORTID_VAL_SET(x)\  argument
377 	FIELD_PREP(ANA_PORT_CFG_PORTID_VAL, x)
378 #define ANA_PORT_CFG_PORTID_VAL_GET(x)\  argument
379 	FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x)
385 #define ANA_POL_CFG_PORT_POL_ENA_SET(x)\  argument
386 	FIELD_PREP(ANA_POL_CFG_PORT_POL_ENA, x)
387 #define ANA_POL_CFG_PORT_POL_ENA_GET(x)\  argument
388 	FIELD_GET(ANA_POL_CFG_PORT_POL_ENA, x)
391 #define ANA_POL_CFG_POL_ORDER_SET(x)\  argument
392 	FIELD_PREP(ANA_POL_CFG_POL_ORDER, x)
393 #define ANA_POL_CFG_POL_ORDER_GET(x)\  argument
394 	FIELD_GET(ANA_POL_CFG_POL_ORDER, x)
400 #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\  argument
401 	FIELD_PREP(ANA_PFC_CFG_FC_LINK_SPEED, x)
402 #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\  argument
403 	FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x)
409 #define ANA_AGGR_CFG_AC_RND_ENA_SET(x)\  argument
410 	FIELD_PREP(ANA_AGGR_CFG_AC_RND_ENA, x)
411 #define ANA_AGGR_CFG_AC_RND_ENA_GET(x)\  argument
412 	FIELD_GET(ANA_AGGR_CFG_AC_RND_ENA, x)
415 #define ANA_AGGR_CFG_AC_DMAC_ENA_SET(x)\  argument
416 	FIELD_PREP(ANA_AGGR_CFG_AC_DMAC_ENA, x)
417 #define ANA_AGGR_CFG_AC_DMAC_ENA_GET(x)\  argument
418 	FIELD_GET(ANA_AGGR_CFG_AC_DMAC_ENA, x)
421 #define ANA_AGGR_CFG_AC_SMAC_ENA_SET(x)\  argument
422 	FIELD_PREP(ANA_AGGR_CFG_AC_SMAC_ENA, x)
423 #define ANA_AGGR_CFG_AC_SMAC_ENA_GET(x)\  argument
424 	FIELD_GET(ANA_AGGR_CFG_AC_SMAC_ENA, x)
427 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_SET(x)\  argument
428 	FIELD_PREP(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x)
429 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_GET(x)\  argument
430 	FIELD_GET(ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA, x)
433 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_SET(x)\  argument
434 	FIELD_PREP(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x)
435 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_GET(x)\  argument
436 	FIELD_GET(ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA, x)
439 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_SET(x)\  argument
440 	FIELD_PREP(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x)
441 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_GET(x)\  argument
442 	FIELD_GET(ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA, x)
445 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_SET(x)\  argument
446 	FIELD_PREP(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x)
447 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_GET(x)\  argument
448 	FIELD_GET(ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, x)
454 #define ANA_POL_PIR_CFG_PIR_RATE_SET(x)\  argument
455 	FIELD_PREP(ANA_POL_PIR_CFG_PIR_RATE, x)
456 #define ANA_POL_PIR_CFG_PIR_RATE_GET(x)\  argument
457 	FIELD_GET(ANA_POL_PIR_CFG_PIR_RATE, x)
460 #define ANA_POL_PIR_CFG_PIR_BURST_SET(x)\  argument
461 	FIELD_PREP(ANA_POL_PIR_CFG_PIR_BURST, x)
462 #define ANA_POL_PIR_CFG_PIR_BURST_GET(x)\  argument
463 	FIELD_GET(ANA_POL_PIR_CFG_PIR_BURST, x)
469 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_SET(x)\  argument
470 	FIELD_PREP(ANA_POL_MODE_DROP_ON_YELLOW_ENA, x)
471 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_GET(x)\  argument
472 	FIELD_GET(ANA_POL_MODE_DROP_ON_YELLOW_ENA, x)
475 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_SET(x)\  argument
476 	FIELD_PREP(ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA, x)
477 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_GET(x)\  argument
478 	FIELD_GET(ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA, x)
481 #define ANA_POL_MODE_IPG_SIZE_SET(x)\  argument
482 	FIELD_PREP(ANA_POL_MODE_IPG_SIZE, x)
483 #define ANA_POL_MODE_IPG_SIZE_GET(x)\  argument
484 	FIELD_GET(ANA_POL_MODE_IPG_SIZE, x)
487 #define ANA_POL_MODE_FRM_MODE_SET(x)\  argument
488 	FIELD_PREP(ANA_POL_MODE_FRM_MODE, x)
489 #define ANA_POL_MODE_FRM_MODE_GET(x)\  argument
490 	FIELD_GET(ANA_POL_MODE_FRM_MODE, x)
493 #define ANA_POL_MODE_OVERSHOOT_ENA_SET(x)\  argument
494 	FIELD_PREP(ANA_POL_MODE_OVERSHOOT_ENA, x)
495 #define ANA_POL_MODE_OVERSHOOT_ENA_GET(x)\  argument
496 	FIELD_GET(ANA_POL_MODE_OVERSHOOT_ENA, x)
502 #define ANA_POL_PIR_STATE_PIR_LVL_SET(x)\  argument
503 	FIELD_PREP(ANA_POL_PIR_STATE_PIR_LVL, x)
504 #define ANA_POL_PIR_STATE_PIR_LVL_GET(x)\  argument
505 	FIELD_GET(ANA_POL_PIR_STATE_PIR_LVL, x)
511 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\  argument
512 	FIELD_PREP(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x)
513 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\  argument
514 	FIELD_GET(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x)
520 #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\  argument
521 	FIELD_PREP(DEV_CLOCK_CFG_MAC_TX_RST, x)
522 #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\  argument
523 	FIELD_GET(DEV_CLOCK_CFG_MAC_TX_RST, x)
526 #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\  argument
527 	FIELD_PREP(DEV_CLOCK_CFG_MAC_RX_RST, x)
528 #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\  argument
529 	FIELD_GET(DEV_CLOCK_CFG_MAC_RX_RST, x)
532 #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\  argument
533 	FIELD_PREP(DEV_CLOCK_CFG_PCS_TX_RST, x)
534 #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\  argument
535 	FIELD_GET(DEV_CLOCK_CFG_PCS_TX_RST, x)
538 #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\  argument
539 	FIELD_PREP(DEV_CLOCK_CFG_PCS_RX_RST, x)
540 #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\  argument
541 	FIELD_GET(DEV_CLOCK_CFG_PCS_RX_RST, x)
544 #define DEV_CLOCK_CFG_PORT_RST_SET(x)\  argument
545 	FIELD_PREP(DEV_CLOCK_CFG_PORT_RST, x)
546 #define DEV_CLOCK_CFG_PORT_RST_GET(x)\  argument
547 	FIELD_GET(DEV_CLOCK_CFG_PORT_RST, x)
550 #define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\  argument
551 	FIELD_PREP(DEV_CLOCK_CFG_LINK_SPEED, x)
552 #define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\  argument
553 	FIELD_GET(DEV_CLOCK_CFG_LINK_SPEED, x)
559 #define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
560 	FIELD_PREP(DEV_MAC_ENA_CFG_RX_ENA, x)
561 #define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
562 	FIELD_GET(DEV_MAC_ENA_CFG_RX_ENA, x)
565 #define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
566 	FIELD_PREP(DEV_MAC_ENA_CFG_TX_ENA, x)
567 #define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
568 	FIELD_GET(DEV_MAC_ENA_CFG_TX_ENA, x)
574 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\  argument
575 	FIELD_PREP(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x)
576 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\  argument
577 	FIELD_GET(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x)
583 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
584 	FIELD_PREP(DEV_MAC_MAXLEN_CFG_MAX_LEN, x)
585 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
586 	FIELD_GET(DEV_MAC_MAXLEN_CFG_MAX_LEN, x)
592 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_SET(x)\  argument
593 	FIELD_PREP(DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA, x)
594 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_GET(x)\  argument
595 	FIELD_GET(DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA, x)
598 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\  argument
599 	FIELD_PREP(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
600 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\  argument
601 	FIELD_GET(DEV_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
607 #define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\  argument
608 	FIELD_PREP(DEV_MAC_IFG_CFG_TX_IFG, x)
609 #define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\  argument
610 	FIELD_GET(DEV_MAC_IFG_CFG_TX_IFG, x)
613 #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\  argument
614 	FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG2, x)
615 #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\  argument
616 	FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG2, x)
619 #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\  argument
620 	FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG1, x)
621 #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\  argument
622 	FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG1, x)
628 #define DEV_MAC_HDX_CFG_SEED_SET(x)\  argument
629 	FIELD_PREP(DEV_MAC_HDX_CFG_SEED, x)
630 #define DEV_MAC_HDX_CFG_SEED_GET(x)\  argument
631 	FIELD_GET(DEV_MAC_HDX_CFG_SEED, x)
634 #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\  argument
635 	FIELD_PREP(DEV_MAC_HDX_CFG_SEED_LOAD, x)
636 #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\  argument
637 	FIELD_GET(DEV_MAC_HDX_CFG_SEED_LOAD, x)
649 #define DEV_PCS1G_CFG_PCS_ENA_SET(x)\  argument
650 	FIELD_PREP(DEV_PCS1G_CFG_PCS_ENA, x)
651 #define DEV_PCS1G_CFG_PCS_ENA_GET(x)\  argument
652 	FIELD_GET(DEV_PCS1G_CFG_PCS_ENA, x)
658 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\  argument
659 	FIELD_PREP(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
660 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\  argument
661 	FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
664 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\  argument
665 	FIELD_PREP(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
666 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\  argument
667 	FIELD_GET(DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
673 #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\  argument
674 	FIELD_PREP(DEV_PCS1G_SD_CFG_SD_ENA, x)
675 #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\  argument
676 	FIELD_GET(DEV_PCS1G_SD_CFG_SD_ENA, x)
682 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\  argument
683 	FIELD_PREP(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x)
684 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\  argument
685 	FIELD_GET(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x)
688 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\  argument
689 	FIELD_PREP(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
690 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\  argument
691 	FIELD_GET(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
694 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\  argument
695 	FIELD_PREP(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x)
696 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\  argument
697 	FIELD_GET(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x)
700 #define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\  argument
701 	FIELD_PREP(DEV_PCS1G_ANEG_CFG_ENA, x)
702 #define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\  argument
703 	FIELD_GET(DEV_PCS1G_ANEG_CFG_ENA, x)
709 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\  argument
710 	FIELD_PREP(DEV_PCS1G_ANEG_STATUS_LP_ADV, x)
711 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\  argument
712 	FIELD_GET(DEV_PCS1G_ANEG_STATUS_LP_ADV, x)
715 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\  argument
716 	FIELD_PREP(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
717 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\  argument
718 	FIELD_GET(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
724 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\  argument
725 	FIELD_PREP(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x)
726 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\  argument
727 	FIELD_GET(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x)
730 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\  argument
731 	FIELD_PREP(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x)
732 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\  argument
733 	FIELD_GET(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x)
739 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\  argument
740 	FIELD_PREP(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x)
741 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\  argument
742 	FIELD_GET(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x)
748 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\  argument
749 	FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
750 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\  argument
751 	FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
757 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\  argument
758 	FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x)
759 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\  argument
760 	FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x)
766 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\  argument
767 	FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x)
768 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\  argument
769 	FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x)
775 #define FDMA_CH_DB_DISCARD_DB_DISCARD_SET(x)\  argument
776 	FIELD_PREP(FDMA_CH_DB_DISCARD_DB_DISCARD, x)
777 #define FDMA_CH_DB_DISCARD_DB_DISCARD_GET(x)\  argument
778 	FIELD_GET(FDMA_CH_DB_DISCARD_DB_DISCARD, x)
793 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\  argument
794 	FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
795 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\  argument
796 	FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
799 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\  argument
800 	FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x)
801 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\  argument
802 	FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x)
805 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\  argument
806 	FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
807 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\  argument
808 	FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
811 #define FDMA_CH_CFG_CH_MEM_SET(x)\  argument
812 	FIELD_PREP(FDMA_CH_CFG_CH_MEM, x)
813 #define FDMA_CH_CFG_CH_MEM_GET(x)\  argument
814 	FIELD_GET(FDMA_CH_CFG_CH_MEM, x)
820 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\  argument
821 	FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x)
822 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\  argument
823 	FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x)
826 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\  argument
827 	FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x)
828 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\  argument
829 	FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x)
838 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\  argument
839 	FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
840 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\  argument
841 	FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
853 #define PTP_PIN_INTR_INTR_PTP_SET(x)\  argument
854 	FIELD_PREP(PTP_PIN_INTR_INTR_PTP, x)
855 #define PTP_PIN_INTR_INTR_PTP_GET(x)\  argument
856 	FIELD_GET(PTP_PIN_INTR_INTR_PTP, x)
862 #define PTP_PIN_INTR_ENA_INTR_ENA_SET(x)\  argument
863 	FIELD_PREP(PTP_PIN_INTR_ENA_INTR_ENA, x)
864 #define PTP_PIN_INTR_ENA_INTR_ENA_GET(x)\  argument
865 	FIELD_GET(PTP_PIN_INTR_ENA_INTR_ENA, x)
871 #define PTP_DOM_CFG_ENA_SET(x)\  argument
872 	FIELD_PREP(PTP_DOM_CFG_ENA, x)
873 #define PTP_DOM_CFG_ENA_GET(x)\  argument
874 	FIELD_GET(PTP_DOM_CFG_ENA, x)
877 #define PTP_DOM_CFG_CLKCFG_DIS_SET(x)\  argument
878 	FIELD_PREP(PTP_DOM_CFG_CLKCFG_DIS, x)
879 #define PTP_DOM_CFG_CLKCFG_DIS_GET(x)\  argument
880 	FIELD_GET(PTP_DOM_CFG_CLKCFG_DIS, x)
889 #define PTP_PIN_CFG_PIN_ACTION_SET(x)\  argument
890 	FIELD_PREP(PTP_PIN_CFG_PIN_ACTION, x)
891 #define PTP_PIN_CFG_PIN_ACTION_GET(x)\  argument
892 	FIELD_GET(PTP_PIN_CFG_PIN_ACTION, x)
895 #define PTP_PIN_CFG_PIN_SYNC_SET(x)\  argument
896 	FIELD_PREP(PTP_PIN_CFG_PIN_SYNC, x)
897 #define PTP_PIN_CFG_PIN_SYNC_GET(x)\  argument
898 	FIELD_GET(PTP_PIN_CFG_PIN_SYNC, x)
901 #define PTP_PIN_CFG_PIN_SELECT_SET(x)\  argument
902 	FIELD_PREP(PTP_PIN_CFG_PIN_SELECT, x)
903 #define PTP_PIN_CFG_PIN_SELECT_GET(x)\  argument
904 	FIELD_GET(PTP_PIN_CFG_PIN_SELECT, x)
907 #define PTP_PIN_CFG_PIN_DOM_SET(x)\  argument
908 	FIELD_PREP(PTP_PIN_CFG_PIN_DOM, x)
909 #define PTP_PIN_CFG_PIN_DOM_GET(x)\  argument
910 	FIELD_GET(PTP_PIN_CFG_PIN_DOM, x)
916 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_SET(x)\  argument
917 	FIELD_PREP(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x)
918 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_GET(x)\  argument
919 	FIELD_GET(PTP_TOD_SEC_MSB_TOD_SEC_MSB, x)
928 #define PTP_TOD_NSEC_TOD_NSEC_SET(x)\  argument
929 	FIELD_PREP(PTP_TOD_NSEC_TOD_NSEC, x)
930 #define PTP_TOD_NSEC_TOD_NSEC_GET(x)\  argument
931 	FIELD_GET(PTP_TOD_NSEC_TOD_NSEC, x)
937 #define PTP_WF_HIGH_PERIOD_PIN_WFH(x)            ((x) & GENMASK(29, 0))  argument
939 #define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x)          ((x) & GENMASK(29, 0))  argument
945 #define PTP_WF_LOW_PERIOD_PIN_WFL(x)             ((x) & GENMASK(29, 0))  argument
947 #define PTP_WF_LOW_PERIOD_PIN_WFL_X(x)           ((x) & GENMASK(29, 0))  argument
953 #define PTP_TWOSTEP_CTRL_NXT_SET(x)\  argument
954 	FIELD_PREP(PTP_TWOSTEP_CTRL_NXT, x)
955 #define PTP_TWOSTEP_CTRL_NXT_GET(x)\  argument
956 	FIELD_GET(PTP_TWOSTEP_CTRL_NXT, x)
959 #define PTP_TWOSTEP_CTRL_VLD_SET(x)\  argument
960 	FIELD_PREP(PTP_TWOSTEP_CTRL_VLD, x)
961 #define PTP_TWOSTEP_CTRL_VLD_GET(x)\  argument
962 	FIELD_GET(PTP_TWOSTEP_CTRL_VLD, x)
965 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\  argument
966 	FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x)
967 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\  argument
968 	FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x)
971 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\  argument
972 	FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x)
973 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\  argument
974 	FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x)
977 #define PTP_TWOSTEP_CTRL_OVFL_SET(x)\  argument
978 	FIELD_PREP(PTP_TWOSTEP_CTRL_OVFL, x)
979 #define PTP_TWOSTEP_CTRL_OVFL_GET(x)\  argument
980 	FIELD_GET(PTP_TWOSTEP_CTRL_OVFL, x)
986 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\  argument
987 	FIELD_PREP(PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
988 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\  argument
989 	FIELD_GET(PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
995 #define QS_XTR_GRP_CFG_MODE_SET(x)\  argument
996 	FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)
997 #define QS_XTR_GRP_CFG_MODE_GET(x)\  argument
998 	FIELD_GET(QS_XTR_GRP_CFG_MODE, x)
1001 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\  argument
1002 	FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)
1003 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\  argument
1004 	FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)
1019 #define QS_INJ_GRP_CFG_MODE_SET(x)\  argument
1020 	FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)
1021 #define QS_INJ_GRP_CFG_MODE_GET(x)\  argument
1022 	FIELD_GET(QS_INJ_GRP_CFG_MODE, x)
1025 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\  argument
1026 	FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)
1027 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\  argument
1028 	FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)
1037 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\  argument
1038 	FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x)
1039 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\  argument
1040 	FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x)
1043 #define QS_INJ_CTRL_EOF_SET(x)\  argument
1044 	FIELD_PREP(QS_INJ_CTRL_EOF, x)
1045 #define QS_INJ_CTRL_EOF_GET(x)\  argument
1046 	FIELD_GET(QS_INJ_CTRL_EOF, x)
1049 #define QS_INJ_CTRL_SOF_SET(x)\  argument
1050 	FIELD_PREP(QS_INJ_CTRL_SOF, x)
1051 #define QS_INJ_CTRL_SOF_GET(x)\  argument
1052 	FIELD_GET(QS_INJ_CTRL_SOF, x)
1055 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\  argument
1056 	FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x)
1057 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\  argument
1058 	FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x)
1064 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\  argument
1065 	FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x)
1066 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\  argument
1067 	FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x)
1070 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\  argument
1071 	FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x)
1072 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\  argument
1073 	FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x)
1079 #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\  argument
1080 	FIELD_PREP(QSYS_PORT_MODE_DEQUEUE_DIS, x)
1081 #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\  argument
1082 	FIELD_GET(QSYS_PORT_MODE_DEQUEUE_DIS, x)
1088 #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\  argument
1089 	FIELD_PREP(QSYS_SW_PORT_MODE_PORT_ENA, x)
1090 #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\  argument
1091 	FIELD_GET(QSYS_SW_PORT_MODE_PORT_ENA, x)
1094 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\  argument
1095 	FIELD_PREP(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x)
1096 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\  argument
1097 	FIELD_GET(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x)
1100 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\  argument
1101 	FIELD_PREP(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x)
1102 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\  argument
1103 	FIELD_GET(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x)
1106 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\  argument
1107 	FIELD_PREP(QSYS_SW_PORT_MODE_TX_PFC_ENA, x)
1108 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\  argument
1109 	FIELD_GET(QSYS_SW_PORT_MODE_TX_PFC_ENA, x)
1112 #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\  argument
1113 	FIELD_PREP(QSYS_SW_PORT_MODE_AGING_MODE, x)
1114 #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\  argument
1115 	FIELD_GET(QSYS_SW_PORT_MODE_AGING_MODE, x)
1121 #define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\  argument
1122 	FIELD_PREP(QSYS_SW_STATUS_EQ_AVAIL, x)
1123 #define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\  argument
1124 	FIELD_GET(QSYS_SW_STATUS_EQ_AVAIL, x)
1136 #define QSYS_CIR_CFG_CIR_RATE_SET(x)\  argument
1137 	FIELD_PREP(QSYS_CIR_CFG_CIR_RATE, x)
1138 #define QSYS_CIR_CFG_CIR_RATE_GET(x)\  argument
1139 	FIELD_GET(QSYS_CIR_CFG_CIR_RATE, x)
1142 #define QSYS_CIR_CFG_CIR_BURST_SET(x)\  argument
1143 	FIELD_PREP(QSYS_CIR_CFG_CIR_BURST, x)
1144 #define QSYS_CIR_CFG_CIR_BURST_GET(x)\  argument
1145 	FIELD_GET(QSYS_CIR_CFG_CIR_BURST, x)
1151 #define QSYS_SE_CFG_SE_DWRR_CNT_SET(x)\  argument
1152 	FIELD_PREP(QSYS_SE_CFG_SE_DWRR_CNT, x)
1153 #define QSYS_SE_CFG_SE_DWRR_CNT_GET(x)\  argument
1154 	FIELD_GET(QSYS_SE_CFG_SE_DWRR_CNT, x)
1157 #define QSYS_SE_CFG_SE_RR_ENA_SET(x)\  argument
1158 	FIELD_PREP(QSYS_SE_CFG_SE_RR_ENA, x)
1159 #define QSYS_SE_CFG_SE_RR_ENA_GET(x)\  argument
1160 	FIELD_GET(QSYS_SE_CFG_SE_RR_ENA, x)
1163 #define QSYS_SE_CFG_SE_AVB_ENA_SET(x)\  argument
1164 	FIELD_PREP(QSYS_SE_CFG_SE_AVB_ENA, x)
1165 #define QSYS_SE_CFG_SE_AVB_ENA_GET(x)\  argument
1166 	FIELD_GET(QSYS_SE_CFG_SE_AVB_ENA, x)
1169 #define QSYS_SE_CFG_SE_FRM_MODE_SET(x)\  argument
1170 	FIELD_PREP(QSYS_SE_CFG_SE_FRM_MODE, x)
1171 #define QSYS_SE_CFG_SE_FRM_MODE_GET(x)\  argument
1172 	FIELD_GET(QSYS_SE_CFG_SE_FRM_MODE, x)
1177 #define QSYS_SE_DWRR_CFG_DWRR_COST_SET(x)\  argument
1178 	FIELD_PREP(QSYS_SE_DWRR_CFG_DWRR_COST, x)
1179 #define QSYS_SE_DWRR_CFG_DWRR_COST_GET(x)\  argument
1180 	FIELD_GET(QSYS_SE_DWRR_CFG_DWRR_COST, x)
1186 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_SET(x)\  argument
1187 	FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x)
1188 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_GET(x)\  argument
1189 	FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM_MAX, x)
1192 #define QSYS_TAS_CFG_CTRL_LIST_NUM_SET(x)\  argument
1193 	FIELD_PREP(QSYS_TAS_CFG_CTRL_LIST_NUM, x)
1194 #define QSYS_TAS_CFG_CTRL_LIST_NUM_GET(x)\  argument
1195 	FIELD_GET(QSYS_TAS_CFG_CTRL_LIST_NUM, x)
1198 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_SET(x)\  argument
1199 	FIELD_PREP(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x)
1200 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_GET(x)\  argument
1201 	FIELD_GET(QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q, x)
1204 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_SET(x)\  argument
1205 	FIELD_PREP(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x)
1206 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_GET(x)\  argument
1207 	FIELD_GET(QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM, x)
1213 #define QSYS_TAS_GS_CTRL_HSCH_POS_SET(x)\  argument
1214 	FIELD_PREP(QSYS_TAS_GS_CTRL_HSCH_POS, x)
1215 #define QSYS_TAS_GS_CTRL_HSCH_POS_GET(x)\  argument
1216 	FIELD_GET(QSYS_TAS_GS_CTRL_HSCH_POS, x)
1222 #define QSYS_TAS_STM_CFG_REVISIT_DLY_SET(x)\  argument
1223 	FIELD_PREP(QSYS_TAS_STM_CFG_REVISIT_DLY, x)
1224 #define QSYS_TAS_STM_CFG_REVISIT_DLY_GET(x)\  argument
1225 	FIELD_GET(QSYS_TAS_STM_CFG_REVISIT_DLY, x)
1231 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_SET(x)\  argument
1232 	FIELD_PREP(QSYS_TAS_PROFILE_CFG_PORT_NUM, x)
1233 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_GET(x)\  argument
1234 	FIELD_GET(QSYS_TAS_PROFILE_CFG_PORT_NUM, x)
1237 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_SET(x)\  argument
1238 	FIELD_PREP(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x)
1239 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_GET(x)\  argument
1240 	FIELD_GET(QSYS_TAS_PROFILE_CFG_LINK_SPEED, x)
1246 #define QSYS_TAS_BT_NSEC_NSEC_SET(x)\  argument
1247 	FIELD_PREP(QSYS_TAS_BT_NSEC_NSEC, x)
1248 #define QSYS_TAS_BT_NSEC_NSEC_GET(x)\  argument
1249 	FIELD_GET(QSYS_TAS_BT_NSEC_NSEC, x)
1258 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_SET(x)\  argument
1259 	FIELD_PREP(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x)
1260 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_GET(x)\  argument
1261 	FIELD_GET(QSYS_TAS_BT_SEC_MSB_SEC_MSB, x)
1270 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_SET(x)\  argument
1271 	FIELD_PREP(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x)
1272 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_GET(x)\  argument
1273 	FIELD_GET(QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX, x)
1279 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_SET(x)\  argument
1280 	FIELD_PREP(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x)
1281 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_GET(x)\  argument
1282 	FIELD_GET(QSYS_TAS_LIST_CFG_LIST_BASE_ADDR, x)
1288 #define QSYS_TAS_LST_LIST_STATE_SET(x)\  argument
1289 	FIELD_PREP(QSYS_TAS_LST_LIST_STATE, x)
1290 #define QSYS_TAS_LST_LIST_STATE_GET(x)\  argument
1291 	FIELD_GET(QSYS_TAS_LST_LIST_STATE, x)
1297 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_SET(x)\  argument
1298 	FIELD_PREP(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x)
1299 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_GET(x)\  argument
1300 	FIELD_GET(QSYS_TAS_GCL_CT_CFG_HSCH_POS, x)
1303 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_SET(x)\  argument
1304 	FIELD_PREP(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x)
1305 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_GET(x)\  argument
1306 	FIELD_GET(QSYS_TAS_GCL_CT_CFG_GATE_STATE, x)
1309 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_SET(x)\  argument
1310 	FIELD_PREP(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x)
1311 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_GET(x)\  argument
1312 	FIELD_GET(QSYS_TAS_GCL_CT_CFG_OP_TYPE, x)
1318 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_SET(x)\  argument
1319 	FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x)
1320 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_GET(x)\  argument
1321 	FIELD_GET(QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE, x)
1324 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_SET(x)\  argument
1325 	FIELD_PREP(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x)
1326 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_GET(x)\  argument
1327 	FIELD_GET(QSYS_TAS_GCL_CT_CFG2_NEXT_GCL, x)
1336 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_SET(x)\  argument
1337 	FIELD_PREP(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x)
1338 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_GET(x)\  argument
1339 	FIELD_GET(QSYS_TAS_GATE_STATE_TAS_GATE_STATE, x)
1345 #define REW_PORT_VLAN_CFG_PORT_TPID_SET(x)\  argument
1346 	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_TPID, x)
1347 #define REW_PORT_VLAN_CFG_PORT_TPID_GET(x)\  argument
1348 	FIELD_GET(REW_PORT_VLAN_CFG_PORT_TPID, x)
1351 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\  argument
1352 	FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x)
1353 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\  argument
1354 	FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x)
1360 #define REW_TAG_CFG_TAG_CFG_SET(x)\  argument
1361 	FIELD_PREP(REW_TAG_CFG_TAG_CFG, x)
1362 #define REW_TAG_CFG_TAG_CFG_GET(x)\  argument
1363 	FIELD_GET(REW_TAG_CFG_TAG_CFG, x)
1366 #define REW_TAG_CFG_TAG_TPID_CFG_SET(x)\  argument
1367 	FIELD_PREP(REW_TAG_CFG_TAG_TPID_CFG, x)
1368 #define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\  argument
1369 	FIELD_GET(REW_TAG_CFG_TAG_TPID_CFG, x)
1375 #define REW_PORT_CFG_NO_REWRITE_SET(x)\  argument
1376 	FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x)
1377 #define REW_PORT_CFG_NO_REWRITE_GET(x)\  argument
1378 	FIELD_GET(REW_PORT_CFG_NO_REWRITE, x)
1384 #define SYS_RESET_CFG_CORE_ENA_SET(x)\  argument
1385 	FIELD_PREP(SYS_RESET_CFG_CORE_ENA, x)
1386 #define SYS_RESET_CFG_CORE_ENA_GET(x)\  argument
1387 	FIELD_GET(SYS_RESET_CFG_CORE_ENA, x)
1393 #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\  argument
1394 	FIELD_PREP(SYS_PORT_MODE_INCL_INJ_HDR, x)
1395 #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\  argument
1396 	FIELD_GET(SYS_PORT_MODE_INCL_INJ_HDR, x)
1399 #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\  argument
1400 	FIELD_PREP(SYS_PORT_MODE_INCL_XTR_HDR, x)
1401 #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\  argument
1402 	FIELD_GET(SYS_PORT_MODE_INCL_XTR_HDR, x)
1408 #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\  argument
1409 	FIELD_PREP(SYS_FRONT_PORT_MODE_HDX_MODE, x)
1410 #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\  argument
1411 	FIELD_GET(SYS_FRONT_PORT_MODE_HDX_MODE, x)
1417 #define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\  argument
1418 	FIELD_PREP(SYS_FRM_AGING_AGE_TX_ENA, x)
1419 #define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\  argument
1420 	FIELD_GET(SYS_FRM_AGING_AGE_TX_ENA, x)
1426 #define SYS_STAT_CFG_STAT_VIEW_SET(x)\  argument
1427 	FIELD_PREP(SYS_STAT_CFG_STAT_VIEW, x)
1428 #define SYS_STAT_CFG_STAT_VIEW_GET(x)\  argument
1429 	FIELD_GET(SYS_STAT_CFG_STAT_VIEW, x)
1435 #define SYS_PAUSE_CFG_PAUSE_START_SET(x)\  argument
1436 	FIELD_PREP(SYS_PAUSE_CFG_PAUSE_START, x)
1437 #define SYS_PAUSE_CFG_PAUSE_START_GET(x)\  argument
1438 	FIELD_GET(SYS_PAUSE_CFG_PAUSE_START, x)
1441 #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\  argument
1442 	FIELD_PREP(SYS_PAUSE_CFG_PAUSE_STOP, x)
1443 #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\  argument
1444 	FIELD_GET(SYS_PAUSE_CFG_PAUSE_STOP, x)
1447 #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\  argument
1448 	FIELD_PREP(SYS_PAUSE_CFG_PAUSE_ENA, x)
1449 #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\  argument
1450 	FIELD_GET(SYS_PAUSE_CFG_PAUSE_ENA, x)
1462 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\  argument
1463 	FIELD_PREP(SYS_MAC_FC_CFG_FC_LINK_SPEED, x)
1464 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\  argument
1465 	FIELD_GET(SYS_MAC_FC_CFG_FC_LINK_SPEED, x)
1468 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\  argument
1469 	FIELD_PREP(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x)
1470 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\  argument
1471 	FIELD_GET(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x)
1474 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\  argument
1475 	FIELD_PREP(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x)
1476 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\  argument
1477 	FIELD_GET(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x)
1480 #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\  argument
1481 	FIELD_PREP(SYS_MAC_FC_CFG_TX_FC_ENA, x)
1482 #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\  argument
1483 	FIELD_GET(SYS_MAC_FC_CFG_TX_FC_ENA, x)
1486 #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\  argument
1487 	FIELD_PREP(SYS_MAC_FC_CFG_RX_FC_ENA, x)
1488 #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\  argument
1489 	FIELD_GET(SYS_MAC_FC_CFG_RX_FC_ENA, x)
1492 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\  argument
1493 	FIELD_PREP(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x)
1494 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\  argument
1495 	FIELD_GET(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x)
1504 #define SYS_RAM_INIT_RAM_INIT_SET(x)\  argument
1505 	FIELD_PREP(SYS_RAM_INIT_RAM_INIT, x)
1506 #define SYS_RAM_INIT_RAM_INIT_GET(x)\  argument
1507 	FIELD_GET(SYS_RAM_INIT_RAM_INIT, x)