37 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\  argument
39 #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\  argument
46 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\  argument
48 #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\  argument
52 #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\  argument
54 #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\  argument
61 #define ANA_ADVLEARN_VLAN_CHK_SET(x)\  argument
63 #define ANA_ADVLEARN_VLAN_CHK_GET(x)\  argument
73 #define ANA_ANAINTR_INTR_SET(x)\  argument
75 #define ANA_ANAINTR_INTR_GET(x)\  argument
79 #define ANA_ANAINTR_INTR_ENA_SET(x)\  argument
81 #define ANA_ANAINTR_INTR_ENA_GET(x)\  argument
88 #define ANA_AUTOAGE_AGE_PERIOD_SET(x)\  argument
90 #define ANA_AUTOAGE_AGE_PERIOD_GET(x)\  argument
97 #define ANA_MIRRORPORTS_MIRRORPORTS_SET(x)\  argument
99 #define ANA_MIRRORPORTS_MIRRORPORTS_GET(x)\  argument
106 #define ANA_EMIRRORPORTS_EMIRRORPORTS_SET(x)\  argument
108 #define ANA_EMIRRORPORTS_EMIRRORPORTS_GET(x)\  argument
115 #define ANA_FLOODING_FLD_UNICAST_SET(x)\  argument
117 #define ANA_FLOODING_FLD_UNICAST_GET(x)\  argument
121 #define ANA_FLOODING_FLD_BROADCAST_SET(x)\  argument
123 #define ANA_FLOODING_FLD_BROADCAST_GET(x)\  argument
127 #define ANA_FLOODING_FLD_MULTICAST_SET(x)\  argument
129 #define ANA_FLOODING_FLD_MULTICAST_GET(x)\  argument
136 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\  argument
138 #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\  argument
142 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\  argument
144 #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\  argument
148 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\  argument
150 #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\  argument
154 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\  argument
156 #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\  argument
163 #define ANA_PGID_PGID_SET(x)\  argument
165 #define ANA_PGID_PGID_GET(x)\  argument
172 #define ANA_PGID_CFG_OBEY_VLAN_SET(x)\  argument
174 #define ANA_PGID_CFG_OBEY_VLAN_GET(x)\  argument
187 #define ANA_MACACCESS_CHANGE2SW_SET(x)\  argument
189 #define ANA_MACACCESS_CHANGE2SW_GET(x)\  argument
193 #define ANA_MACACCESS_MAC_CPU_COPY_SET(x)\  argument
195 #define ANA_MACACCESS_MAC_CPU_COPY_GET(x)\  argument
199 #define ANA_MACACCESS_VALID_SET(x)\  argument
201 #define ANA_MACACCESS_VALID_GET(x)\  argument
205 #define ANA_MACACCESS_ENTRYTYPE_SET(x)\  argument
207 #define ANA_MACACCESS_ENTRYTYPE_GET(x)\  argument
211 #define ANA_MACACCESS_DEST_IDX_SET(x)\  argument
213 #define ANA_MACACCESS_DEST_IDX_GET(x)\  argument
217 #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\  argument
219 #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\  argument
226 #define ANA_MACTINDX_BUCKET_SET(x)\  argument
228 #define ANA_MACTINDX_BUCKET_GET(x)\  argument
232 #define ANA_MACTINDX_M_INDEX_SET(x)\  argument
234 #define ANA_MACTINDX_M_INDEX_GET(x)\  argument
241 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_SET(x)\  argument
243 #define ANA_VLAN_PORT_MASK_VLAN_PORT_MASK_GET(x)\  argument
250 #define ANA_VLANACCESS_VLAN_TBL_CMD_SET(x)\  argument
252 #define ANA_VLANACCESS_VLAN_TBL_CMD_GET(x)\  argument
259 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_SET(x)\  argument
261 #define ANA_VLANTIDX_VLAN_PGID_CPU_DIS_GET(x)\  argument
265 #define ANA_VLANTIDX_V_INDEX_SET(x)\  argument
267 #define ANA_VLANTIDX_V_INDEX_GET(x)\  argument
274 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_SET(x)\  argument
276 #define ANA_VLAN_CFG_VLAN_AWARE_ENA_GET(x)\  argument
280 #define ANA_VLAN_CFG_VLAN_POP_CNT_SET(x)\  argument
282 #define ANA_VLAN_CFG_VLAN_POP_CNT_GET(x)\  argument
286 #define ANA_VLAN_CFG_VLAN_VID_SET(x)\  argument
288 #define ANA_VLAN_CFG_VLAN_VID_GET(x)\  argument
295 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_SET(x)\  argument
297 #define ANA_DROP_CFG_DROP_UNTAGGED_ENA_GET(x)\  argument
301 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_SET(x)\  argument
303 #define ANA_DROP_CFG_DROP_PRIO_S_TAGGED_ENA_GET(x)\  argument
307 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_SET(x)\  argument
309 #define ANA_DROP_CFG_DROP_PRIO_C_TAGGED_ENA_GET(x)\  argument
313 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_SET(x)\  argument
315 #define ANA_DROP_CFG_DROP_MC_SMAC_ENA_GET(x)\  argument
322 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_SET(x)\  argument
324 #define ANA_CPU_FWD_CFG_MLD_REDIR_ENA_GET(x)\  argument
328 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_SET(x)\  argument
330 #define ANA_CPU_FWD_CFG_IGMP_REDIR_ENA_GET(x)\  argument
334 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_SET(x)\  argument
336 #define ANA_CPU_FWD_CFG_IPMC_CTRL_COPY_ENA_GET(x)\  argument
340 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\  argument
342 #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\  argument
352 #define ANA_PORT_CFG_SRC_MIRROR_ENA_SET(x)\  argument
354 #define ANA_PORT_CFG_SRC_MIRROR_ENA_GET(x)\  argument
358 #define ANA_PORT_CFG_LEARNAUTO_SET(x)\  argument
360 #define ANA_PORT_CFG_LEARNAUTO_GET(x)\  argument
364 #define ANA_PORT_CFG_LEARN_ENA_SET(x)\  argument
366 #define ANA_PORT_CFG_LEARN_ENA_GET(x)\  argument
370 #define ANA_PORT_CFG_RECV_ENA_SET(x)\  argument
372 #define ANA_PORT_CFG_RECV_ENA_GET(x)\  argument
376 #define ANA_PORT_CFG_PORTID_VAL_SET(x)\  argument
378 #define ANA_PORT_CFG_PORTID_VAL_GET(x)\  argument
385 #define ANA_POL_CFG_PORT_POL_ENA_SET(x)\  argument
387 #define ANA_POL_CFG_PORT_POL_ENA_GET(x)\  argument
391 #define ANA_POL_CFG_POL_ORDER_SET(x)\  argument
393 #define ANA_POL_CFG_POL_ORDER_GET(x)\  argument
400 #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\  argument
402 #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\  argument
409 #define ANA_AGGR_CFG_AC_RND_ENA_SET(x)\  argument
411 #define ANA_AGGR_CFG_AC_RND_ENA_GET(x)\  argument
415 #define ANA_AGGR_CFG_AC_DMAC_ENA_SET(x)\  argument
417 #define ANA_AGGR_CFG_AC_DMAC_ENA_GET(x)\  argument
421 #define ANA_AGGR_CFG_AC_SMAC_ENA_SET(x)\  argument
423 #define ANA_AGGR_CFG_AC_SMAC_ENA_GET(x)\  argument
427 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_SET(x)\  argument
429 #define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA_GET(x)\  argument
433 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_SET(x)\  argument
435 #define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA_GET(x)\  argument
439 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_SET(x)\  argument
441 #define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA_GET(x)\  argument
445 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_SET(x)\  argument
447 #define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA_GET(x)\  argument
454 #define ANA_POL_PIR_CFG_PIR_RATE_SET(x)\  argument
456 #define ANA_POL_PIR_CFG_PIR_RATE_GET(x)\  argument
460 #define ANA_POL_PIR_CFG_PIR_BURST_SET(x)\  argument
462 #define ANA_POL_PIR_CFG_PIR_BURST_GET(x)\  argument
469 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_SET(x)\  argument
471 #define ANA_POL_MODE_DROP_ON_YELLOW_ENA_GET(x)\  argument
475 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_SET(x)\  argument
477 #define ANA_POL_MODE_MARK_ALL_FRMS_RED_ENA_GET(x)\  argument
481 #define ANA_POL_MODE_IPG_SIZE_SET(x)\  argument
483 #define ANA_POL_MODE_IPG_SIZE_GET(x)\  argument
487 #define ANA_POL_MODE_FRM_MODE_SET(x)\  argument
489 #define ANA_POL_MODE_FRM_MODE_GET(x)\  argument
493 #define ANA_POL_MODE_OVERSHOOT_ENA_SET(x)\  argument
495 #define ANA_POL_MODE_OVERSHOOT_ENA_GET(x)\  argument
502 #define ANA_POL_PIR_STATE_PIR_LVL_SET(x)\  argument
504 #define ANA_POL_PIR_STATE_PIR_LVL_GET(x)\  argument
511 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\  argument
513 #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\  argument
520 #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\  argument
522 #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\  argument
526 #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\  argument
528 #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\  argument
532 #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\  argument
534 #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\  argument
538 #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\  argument
540 #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\  argument
544 #define DEV_CLOCK_CFG_PORT_RST_SET(x)\  argument
546 #define DEV_CLOCK_CFG_PORT_RST_GET(x)\  argument
550 #define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\  argument
552 #define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\  argument
559 #define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\  argument
561 #define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\  argument
565 #define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\  argument
567 #define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\  argument
574 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\  argument
576 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\  argument
583 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\  argument
585 #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\  argument
592 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_SET(x)\  argument
594 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA_GET(x)\  argument
598 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\  argument
600 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\  argument
607 #define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\  argument
609 #define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\  argument
613 #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\  argument
615 #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\  argument
619 #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\  argument
621 #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\  argument
628 #define DEV_MAC_HDX_CFG_SEED_SET(x)\  argument
630 #define DEV_MAC_HDX_CFG_SEED_GET(x)\  argument
634 #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\  argument
636 #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\  argument
649 #define DEV_PCS1G_CFG_PCS_ENA_SET(x)\  argument
651 #define DEV_PCS1G_CFG_PCS_ENA_GET(x)\  argument
658 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\  argument
660 #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\  argument
664 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\  argument
666 #define DEV_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\  argument
673 #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\  argument
675 #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\  argument
682 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\  argument
684 #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\  argument
688 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\  argument
690 #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\  argument
694 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\  argument
696 #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\  argument
700 #define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\  argument
702 #define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\  argument
709 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\  argument
711 #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\  argument
715 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\  argument
717 #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\  argument
724 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\  argument
726 #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\  argument
730 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\  argument
732 #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\  argument
739 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\  argument
741 #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\  argument
748 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\  argument
750 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\  argument
757 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\  argument
759 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\  argument
766 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\  argument
768 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\  argument
775 #define FDMA_CH_DB_DISCARD_DB_DISCARD_SET(x)\  argument
777 #define FDMA_CH_DB_DISCARD_DB_DISCARD_GET(x)\  argument
793 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\  argument
795 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\  argument
799 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\  argument
801 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\  argument
805 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\  argument
807 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\  argument
811 #define FDMA_CH_CFG_CH_MEM_SET(x)\  argument
813 #define FDMA_CH_CFG_CH_MEM_GET(x)\  argument
820 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\  argument
822 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\  argument
826 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\  argument
828 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\  argument
838 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\  argument
840 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\  argument
853 #define PTP_PIN_INTR_INTR_PTP_SET(x)\  argument
855 #define PTP_PIN_INTR_INTR_PTP_GET(x)\  argument
862 #define PTP_PIN_INTR_ENA_INTR_ENA_SET(x)\  argument
864 #define PTP_PIN_INTR_ENA_INTR_ENA_GET(x)\  argument
871 #define PTP_DOM_CFG_ENA_SET(x)\  argument
873 #define PTP_DOM_CFG_ENA_GET(x)\  argument
877 #define PTP_DOM_CFG_CLKCFG_DIS_SET(x)\  argument
879 #define PTP_DOM_CFG_CLKCFG_DIS_GET(x)\  argument
889 #define PTP_PIN_CFG_PIN_ACTION_SET(x)\  argument
891 #define PTP_PIN_CFG_PIN_ACTION_GET(x)\  argument
895 #define PTP_PIN_CFG_PIN_SYNC_SET(x)\  argument
897 #define PTP_PIN_CFG_PIN_SYNC_GET(x)\  argument
901 #define PTP_PIN_CFG_PIN_SELECT_SET(x)\  argument
903 #define PTP_PIN_CFG_PIN_SELECT_GET(x)\  argument
907 #define PTP_PIN_CFG_PIN_DOM_SET(x)\  argument
909 #define PTP_PIN_CFG_PIN_DOM_GET(x)\  argument
916 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_SET(x)\  argument
918 #define PTP_TOD_SEC_MSB_TOD_SEC_MSB_GET(x)\  argument
928 #define PTP_TOD_NSEC_TOD_NSEC_SET(x)\  argument
930 #define PTP_TOD_NSEC_TOD_NSEC_GET(x)\  argument
937 #define PTP_WF_HIGH_PERIOD_PIN_WFH(x)            ((x) & GENMASK(29, 0))  argument
939 #define PTP_WF_HIGH_PERIOD_PIN_WFH_X(x)          ((x) & GENMASK(29, 0))  argument
945 #define PTP_WF_LOW_PERIOD_PIN_WFL(x)             ((x) & GENMASK(29, 0))  argument
947 #define PTP_WF_LOW_PERIOD_PIN_WFL_X(x)           ((x) & GENMASK(29, 0))  argument
953 #define PTP_TWOSTEP_CTRL_NXT_SET(x)\  argument
955 #define PTP_TWOSTEP_CTRL_NXT_GET(x)\  argument
959 #define PTP_TWOSTEP_CTRL_VLD_SET(x)\  argument
961 #define PTP_TWOSTEP_CTRL_VLD_GET(x)\  argument
965 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\  argument
967 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\  argument
971 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\  argument
973 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\  argument
977 #define PTP_TWOSTEP_CTRL_OVFL_SET(x)\  argument
979 #define PTP_TWOSTEP_CTRL_OVFL_GET(x)\  argument
986 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\  argument
988 #define PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\  argument
995 #define QS_XTR_GRP_CFG_MODE_SET(x)\  argument
997 #define QS_XTR_GRP_CFG_MODE_GET(x)\  argument
1001 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\  argument
1003 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\  argument
1019 #define QS_INJ_GRP_CFG_MODE_SET(x)\  argument
1021 #define QS_INJ_GRP_CFG_MODE_GET(x)\  argument
1025 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\  argument
1027 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\  argument
1037 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\  argument
1039 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\  argument
1043 #define QS_INJ_CTRL_EOF_SET(x)\  argument
1045 #define QS_INJ_CTRL_EOF_GET(x)\  argument
1049 #define QS_INJ_CTRL_SOF_SET(x)\  argument
1051 #define QS_INJ_CTRL_SOF_GET(x)\  argument
1055 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\  argument
1057 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\  argument
1064 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\  argument
1066 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\  argument
1070 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\  argument
1072 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\  argument
1079 #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\  argument
1081 #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\  argument
1088 #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\  argument
1090 #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\  argument
1094 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\  argument
1096 #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\  argument
1100 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\  argument
1102 #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\  argument
1106 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\  argument
1108 #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\  argument
1112 #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\  argument
1114 #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\  argument
1121 #define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\  argument
1123 #define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\  argument
1136 #define QSYS_CIR_CFG_CIR_RATE_SET(x)\  argument
1138 #define QSYS_CIR_CFG_CIR_RATE_GET(x)\  argument
1142 #define QSYS_CIR_CFG_CIR_BURST_SET(x)\  argument
1144 #define QSYS_CIR_CFG_CIR_BURST_GET(x)\  argument
1151 #define QSYS_SE_CFG_SE_DWRR_CNT_SET(x)\  argument
1153 #define QSYS_SE_CFG_SE_DWRR_CNT_GET(x)\  argument
1157 #define QSYS_SE_CFG_SE_RR_ENA_SET(x)\  argument
1159 #define QSYS_SE_CFG_SE_RR_ENA_GET(x)\  argument
1163 #define QSYS_SE_CFG_SE_AVB_ENA_SET(x)\  argument
1165 #define QSYS_SE_CFG_SE_AVB_ENA_GET(x)\  argument
1169 #define QSYS_SE_CFG_SE_FRM_MODE_SET(x)\  argument
1171 #define QSYS_SE_CFG_SE_FRM_MODE_GET(x)\  argument
1177 #define QSYS_SE_DWRR_CFG_DWRR_COST_SET(x)\  argument
1179 #define QSYS_SE_DWRR_CFG_DWRR_COST_GET(x)\  argument
1186 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_SET(x)\  argument
1188 #define QSYS_TAS_CFG_CTRL_LIST_NUM_MAX_GET(x)\  argument
1192 #define QSYS_TAS_CFG_CTRL_LIST_NUM_SET(x)\  argument
1194 #define QSYS_TAS_CFG_CTRL_LIST_NUM_GET(x)\  argument
1198 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_SET(x)\  argument
1200 #define QSYS_TAS_CFG_CTRL_ALWAYS_GB_SCH_Q_GET(x)\  argument
1204 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_SET(x)\  argument
1206 #define QSYS_TAS_CFG_CTRL_GCL_ENTRY_NUM_GET(x)\  argument
1213 #define QSYS_TAS_GS_CTRL_HSCH_POS_SET(x)\  argument
1215 #define QSYS_TAS_GS_CTRL_HSCH_POS_GET(x)\  argument
1222 #define QSYS_TAS_STM_CFG_REVISIT_DLY_SET(x)\  argument
1224 #define QSYS_TAS_STM_CFG_REVISIT_DLY_GET(x)\  argument
1231 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_SET(x)\  argument
1233 #define QSYS_TAS_PROFILE_CFG_PORT_NUM_GET(x)\  argument
1237 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_SET(x)\  argument
1239 #define QSYS_TAS_PROFILE_CFG_LINK_SPEED_GET(x)\  argument
1246 #define QSYS_TAS_BT_NSEC_NSEC_SET(x)\  argument
1248 #define QSYS_TAS_BT_NSEC_NSEC_GET(x)\  argument
1258 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_SET(x)\  argument
1260 #define QSYS_TAS_BT_SEC_MSB_SEC_MSB_GET(x)\  argument
1270 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_SET(x)\  argument
1272 #define QSYS_TAS_STARTUP_CFG_OBSOLETE_IDX_GET(x)\  argument
1279 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_SET(x)\  argument
1281 #define QSYS_TAS_LIST_CFG_LIST_BASE_ADDR_GET(x)\  argument
1288 #define QSYS_TAS_LST_LIST_STATE_SET(x)\  argument
1290 #define QSYS_TAS_LST_LIST_STATE_GET(x)\  argument
1297 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_SET(x)\  argument
1299 #define QSYS_TAS_GCL_CT_CFG_HSCH_POS_GET(x)\  argument
1303 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_SET(x)\  argument
1305 #define QSYS_TAS_GCL_CT_CFG_GATE_STATE_GET(x)\  argument
1309 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_SET(x)\  argument
1311 #define QSYS_TAS_GCL_CT_CFG_OP_TYPE_GET(x)\  argument
1318 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_SET(x)\  argument
1320 #define QSYS_TAS_GCL_CT_CFG2_PORT_PROFILE_GET(x)\  argument
1324 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_SET(x)\  argument
1326 #define QSYS_TAS_GCL_CT_CFG2_NEXT_GCL_GET(x)\  argument
1336 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_SET(x)\  argument
1338 #define QSYS_TAS_GATE_STATE_TAS_GATE_STATE_GET(x)\  argument
1345 #define REW_PORT_VLAN_CFG_PORT_TPID_SET(x)\  argument
1347 #define REW_PORT_VLAN_CFG_PORT_TPID_GET(x)\  argument
1351 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\  argument
1353 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\  argument
1360 #define REW_TAG_CFG_TAG_CFG_SET(x)\  argument
1362 #define REW_TAG_CFG_TAG_CFG_GET(x)\  argument
1366 #define REW_TAG_CFG_TAG_TPID_CFG_SET(x)\  argument
1368 #define REW_TAG_CFG_TAG_TPID_CFG_GET(x)\  argument
1375 #define REW_PORT_CFG_NO_REWRITE_SET(x)\  argument
1377 #define REW_PORT_CFG_NO_REWRITE_GET(x)\  argument
1384 #define SYS_RESET_CFG_CORE_ENA_SET(x)\  argument
1386 #define SYS_RESET_CFG_CORE_ENA_GET(x)\  argument
1393 #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\  argument
1395 #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\  argument
1399 #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\  argument
1401 #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\  argument
1408 #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\  argument
1410 #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\  argument
1417 #define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\  argument
1419 #define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\  argument
1426 #define SYS_STAT_CFG_STAT_VIEW_SET(x)\  argument
1428 #define SYS_STAT_CFG_STAT_VIEW_GET(x)\  argument
1435 #define SYS_PAUSE_CFG_PAUSE_START_SET(x)\  argument
1437 #define SYS_PAUSE_CFG_PAUSE_START_GET(x)\  argument
1441 #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\  argument
1443 #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\  argument
1447 #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\  argument
1449 #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\  argument
1462 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\  argument
1464 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\  argument
1468 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\  argument
1470 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\  argument
1474 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\  argument
1476 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\  argument
1480 #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\  argument
1482 #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\  argument
1486 #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\  argument
1488 #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\  argument
1492 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\  argument
1494 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\  argument
1504 #define SYS_RAM_INIT_RAM_INIT_SET(x)\  argument
1506 #define SYS_RAM_INIT_RAM_INIT_GET(x)\  argument