Lines Matching +full:2 +full:- +full:channel
1 /* SPDX-License-Identifier: GPL-2.0+ */
41 #define STRAP_READ_RGMII_TXC_DELAY_EN_ BIT(2)
66 #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2)
110 #define SYS_LOCK_REG_UART_SS_LOCK_ BIT(2)
149 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) argument
150 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) argument
151 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) argument
154 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) argument
155 #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) argument
156 #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) argument
158 #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2))
174 #define MAC_CR_CFG_H_ BIT(2)
202 #define MAC_MII_ACC_MDC_CYCLE_12_5MHZ_ (2)
230 #define MAC_WUCSR_WAKE_EN_ BIT(2)
261 /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */
265 /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */
288 #define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2)
292 #define RFE_HASH_KEY(index) (0x558 + (index << 2))
294 #define RFE_INDX(index) (0x580 + (index << 2))
329 #define VR_MII_DIG_CTRL1_EN_2_5G_MODE_ BIT(2)
337 #define VR_MII_AN_CTRL_SGMII_MODE_ (2)
340 #define VR_MII_AN_CTRL_PCS_MODE_MASK_ GENMASK(2, 1)
344 #define VR_MII_AN_INTR_STS_SPEED_MASK_ GENMASK(3, 2)
346 #define VR_MII_AN_INTR_STS_100_MBPS_ BIT(2)
353 #define VR_MII_DIG_STS_PSEQ_STATE_MASK_ GENMASK(4, 2)
354 #define VR_MII_DIG_STS_PSEQ_STATE_POS_ (2)
367 #define VR_MII_CTRL1_RX_RATE_0_MASK_ GENMASK(3, 2)
368 #define VR_MII_CTRL1_RX_RATE_0_SHIFT_ (2)
372 #define VR_MII_MPLL_BAUD_CLK_DIV_4 (2)
375 #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) argument
377 #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) argument
398 #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ argument
399 (((u32)(vector)) << ((channel) << 2))
402 #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ argument
403 (((u32)(vector)) << ((channel) << 2))
430 #define PTP_CMD_CTL_PTP_ENABLE_ BIT(2)
434 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ argument
435 (0x7 << (1 + ((channel) << 2)))
438 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2)
443 #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ argument
444 (((value) & 0x7) << (1 + ((channel) << 2)))
445 #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) argument
448 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ argument
449 (0xf << (4 + ((channel) << 2)))
452 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1US_ (2)
466 #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ argument
467 (((value) & 0xf) << (4 + ((channel) << 2)))
468 #define HS_PTP_GENERAL_CONFIG_EVENT_POL_X_(channel) (BIT(1 + ((channel) * 2))) argument
469 #define HS_PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) * 2)) argument
474 #define PTP_INT_IO_FE_SET_(channel) BIT(24 + (channel)) argument
477 #define PTP_INT_IO_RE_SET_(channel) BIT(16 + (channel)) argument
486 #define PTP_INT_EN_FE_EN_SET_(channel) BIT(24 + (channel)) argument
487 #define PTP_INT_EN_RE_EN_SET_(channel) BIT(16 + (channel)) argument
488 #define PTP_INT_EN_TIMER_SET_(channel) BIT(channel) argument
490 #define PTP_INT_EN_FE_EN_CLR_(channel) BIT(24 + (channel)) argument
491 #define PTP_INT_EN_RE_EN_CLR_(channel) BIT(16 + (channel)) argument
505 #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4)) argument
506 #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4)) argument
507 #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4)) argument
508 #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4)) argument
554 #define PTP_IO_CAP_CONFIG_LOCK_FE_(channel) BIT(24 + (channel)) argument
555 #define PTP_IO_CAP_CONFIG_LOCK_RE_(channel) BIT(16 + (channel)) argument
556 #define PTP_IO_CAP_CONFIG_FE_CAP_EN_(channel) BIT(8 + (channel)) argument
557 #define PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel) BIT(0 + (channel)) argument
563 #define PTP_IO_EVENT_OUTPUT_CFG_SEL_(channel) BIT(16 + (channel)) argument
564 #define PTP_IO_EVENT_OUTPUT_CFG_EN_(channel) BIT(0 + (channel)) argument
566 #define PTP_IO_PIN_CFG_OBUF_TYPE_(channel) BIT(0 + (channel)) argument
632 #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) argument
633 #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) argument
634 #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) argument
635 #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) argument
636 #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) argument
637 #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) argument
642 #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) argument
643 #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) argument
645 #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) argument
658 #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) argument
666 #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) argument
668 #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) argument
670 #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) argument
672 #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) argument
674 #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) argument
676 #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) argument
680 #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) argument
686 #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) argument
700 #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) argument
704 #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) argument
706 #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) argument
708 #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) argument
710 #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) argument
712 #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) argument
714 #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) argument
719 #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) argument
870 #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2)
925 #define GPIO_TX_COMPLETION (2)
1047 #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) argument
1072 (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0))
1105 #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2)
1131 #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2))
1132 #error NET_IP_ALIGN must be 0 or 2