286 static int mlxsw_pci_sdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_sdq_init()  argument
302 	mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, q->num);  in mlxsw_pci_sdq_init()
303 	mlxsw_cmd_mbox_sw2hw_dq_sdq_lp_set(mbox, lp);  in mlxsw_pci_sdq_init()
304 	mlxsw_cmd_mbox_sw2hw_dq_sdq_tclass_set(mbox, tclass);  in mlxsw_pci_sdq_init()
305 	mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */  in mlxsw_pci_sdq_init()
309 		mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);  in mlxsw_pci_sdq_init()
312 	err = mlxsw_cmd_sw2hw_sdq(mlxsw_pci->core, mbox, q->num);  in mlxsw_pci_sdq_init()
392 static int mlxsw_pci_rdq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_rdq_init()  argument
406 	mlxsw_cmd_mbox_sw2hw_dq_cq_set(mbox, sdq_count + q->num);  in mlxsw_pci_rdq_init()
407 	mlxsw_cmd_mbox_sw2hw_dq_log2_dq_sz_set(mbox, 3); /* 8 pages */  in mlxsw_pci_rdq_init()
411 		mlxsw_cmd_mbox_sw2hw_dq_pa_set(mbox, i, mapaddr);  in mlxsw_pci_rdq_init()
414 	err = mlxsw_cmd_sw2hw_rdq(mlxsw_pci->core, mbox, q->num);  in mlxsw_pci_rdq_init()
467 static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_cq_init()  argument
482 		mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,  in mlxsw_pci_cq_init()
485 		mlxsw_cmd_mbox_sw2hw_cq_cqe_ver_set(mbox,  in mlxsw_pci_cq_init()
488 	mlxsw_cmd_mbox_sw2hw_cq_c_eqn_set(mbox, MLXSW_PCI_EQ_COMP_NUM);  in mlxsw_pci_cq_init()
489 	mlxsw_cmd_mbox_sw2hw_cq_st_set(mbox, 0);  in mlxsw_pci_cq_init()
490 	mlxsw_cmd_mbox_sw2hw_cq_log_cq_size_set(mbox, ilog2(q->count));  in mlxsw_pci_cq_init()
494 		mlxsw_cmd_mbox_sw2hw_cq_pa_set(mbox, i, mapaddr);  in mlxsw_pci_cq_init()
496 	err = mlxsw_cmd_sw2hw_cq(mlxsw_pci->core, mbox, q->num);  in mlxsw_pci_cq_init()
758 static int mlxsw_pci_eq_init(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_eq_init()  argument
772 	mlxsw_cmd_mbox_sw2hw_eq_int_msix_set(mbox, 1); /* MSI-X used */  in mlxsw_pci_eq_init()
773 	mlxsw_cmd_mbox_sw2hw_eq_st_set(mbox, 1); /* armed */  in mlxsw_pci_eq_init()
774 	mlxsw_cmd_mbox_sw2hw_eq_log_eq_size_set(mbox, ilog2(q->count));  in mlxsw_pci_eq_init()
778 		mlxsw_cmd_mbox_sw2hw_eq_pa_set(mbox, i, mapaddr);  in mlxsw_pci_eq_init()
780 	err = mlxsw_cmd_sw2hw_eq(mlxsw_pci->core, mbox, q->num);  in mlxsw_pci_eq_init()
875 	int (*init)(struct mlxsw_pci *mlxsw_pci, char *mbox,
921 static int mlxsw_pci_queue_init(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_queue_init()  argument
968 	mlxsw_cmd_mbox_zero(mbox);  in mlxsw_pci_queue_init()
969 	err = q_ops->init(mlxsw_pci, mbox, q);  in mlxsw_pci_queue_init()
994 static int mlxsw_pci_queue_group_init(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_queue_group_init()  argument
1008 		err = mlxsw_pci_queue_init(mlxsw_pci, mbox, q_ops,  in mlxsw_pci_queue_group_init()
1036 static int mlxsw_pci_aqs_init(struct mlxsw_pci *mlxsw_pci, char *mbox)  in mlxsw_pci_aqs_init()  argument
1050 	mlxsw_cmd_mbox_zero(mbox);  in mlxsw_pci_aqs_init()
1051 	err = mlxsw_cmd_query_aq_cap(mlxsw_pci->core, mbox);  in mlxsw_pci_aqs_init()
1055 	num_sdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_sdqs_get(mbox);  in mlxsw_pci_aqs_init()
1056 	sdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_sdq_sz_get(mbox);  in mlxsw_pci_aqs_init()
1057 	num_rdqs = mlxsw_cmd_mbox_query_aq_cap_max_num_rdqs_get(mbox);  in mlxsw_pci_aqs_init()
1058 	rdq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_rdq_sz_get(mbox);  in mlxsw_pci_aqs_init()
1059 	num_cqs = mlxsw_cmd_mbox_query_aq_cap_max_num_cqs_get(mbox);  in mlxsw_pci_aqs_init()
1060 	cq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cq_sz_get(mbox);  in mlxsw_pci_aqs_init()
1061 	cqv2_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_cqv2_sz_get(mbox);  in mlxsw_pci_aqs_init()
1062 	num_eqs = mlxsw_cmd_mbox_query_aq_cap_max_num_eqs_get(mbox);  in mlxsw_pci_aqs_init()
1063 	eq_log2sz = mlxsw_cmd_mbox_query_aq_cap_log_max_eq_sz_get(mbox);  in mlxsw_pci_aqs_init()
1084 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_eq_ops,  in mlxsw_pci_aqs_init()
1091 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_cq_ops,  in mlxsw_pci_aqs_init()
1098 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_sdq_ops,  in mlxsw_pci_aqs_init()
1105 	err = mlxsw_pci_queue_group_init(mlxsw_pci, mbox, &mlxsw_pci_rdq_ops,  in mlxsw_pci_aqs_init()
1136 				     char *mbox, int index,  in mlxsw_pci_config_profile_swid_config()  argument
1143 			mbox, index, swid->type);  in mlxsw_pci_config_profile_swid_config()
1148 			mbox, index, swid->properties);  in mlxsw_pci_config_profile_swid_config()
1151 	mlxsw_cmd_mbox_config_profile_swid_config_mask_set(mbox, index, mask);  in mlxsw_pci_config_profile_swid_config()
1175 static int mlxsw_pci_config_profile(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_config_profile()  argument
1182 	mlxsw_cmd_mbox_zero(mbox);  in mlxsw_pci_config_profile()
1186 			mbox, 1);  in mlxsw_pci_config_profile()
1188 			mbox, profile->max_vepa_channels);  in mlxsw_pci_config_profile()
1191 		mlxsw_cmd_mbox_config_profile_set_max_lag_set(mbox, 1);  in mlxsw_pci_config_profile()
1192 		mlxsw_cmd_mbox_config_profile_max_lag_set(mbox,  in mlxsw_pci_config_profile()
1197 			mbox, 1);  in mlxsw_pci_config_profile()
1199 			mbox, profile->max_mid);  in mlxsw_pci_config_profile()
1203 			mbox, 1);  in mlxsw_pci_config_profile()
1205 			mbox, profile->max_pgt);  in mlxsw_pci_config_profile()
1209 			mbox, 1);  in mlxsw_pci_config_profile()
1211 			mbox, profile->max_system_port);  in mlxsw_pci_config_profile()
1215 			mbox, 1);  in mlxsw_pci_config_profile()
1217 			mbox, profile->max_vlan_groups);  in mlxsw_pci_config_profile()
1221 			mbox, 1);  in mlxsw_pci_config_profile()
1223 			mbox, profile->max_regions);  in mlxsw_pci_config_profile()
1227 			mbox, 1);  in mlxsw_pci_config_profile()
1229 			mbox, profile->max_flood_tables);  in mlxsw_pci_config_profile()
1231 			mbox, profile->max_vid_flood_tables);  in mlxsw_pci_config_profile()
1233 			mbox, profile->max_fid_offset_flood_tables);  in mlxsw_pci_config_profile()
1235 			mbox, profile->fid_offset_flood_table_size);  in mlxsw_pci_config_profile()
1237 			mbox, profile->max_fid_flood_tables);  in mlxsw_pci_config_profile()
1239 			mbox, profile->fid_flood_table_size);  in mlxsw_pci_config_profile()
1243 			mbox, 1);  in mlxsw_pci_config_profile()
1245 			mbox, profile->flood_mode);  in mlxsw_pci_config_profile()
1249 			mbox, 1);  in mlxsw_pci_config_profile()
1251 			mbox, profile->max_ib_mc);  in mlxsw_pci_config_profile()
1255 			mbox, 1);  in mlxsw_pci_config_profile()
1257 			mbox, profile->max_pkey);  in mlxsw_pci_config_profile()
1261 			mbox, 1);  in mlxsw_pci_config_profile()
1263 			mbox, profile->ar_sec);  in mlxsw_pci_config_profile()
1267 			mbox, 1);  in mlxsw_pci_config_profile()
1269 			mbox, profile->adaptive_routing_group_cap);  in mlxsw_pci_config_profile()
1272 		mlxsw_cmd_mbox_config_profile_set_ubridge_set(mbox, 1);  in mlxsw_pci_config_profile()
1273 		mlxsw_cmd_mbox_config_profile_ubridge_set(mbox,  in mlxsw_pci_config_profile()
1281 		mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set(mbox, 1);  in mlxsw_pci_config_profile()
1282 		mlxsw_cmd_mbox_config_profile_kvd_linear_size_set(mbox,  in mlxsw_pci_config_profile()
1284 		mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set(mbox,  in mlxsw_pci_config_profile()
1286 		mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set(mbox,  in mlxsw_pci_config_profile()
1289 								mbox, 1);  in mlxsw_pci_config_profile()
1290 		mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set(mbox,  in mlxsw_pci_config_profile()
1295 		mlxsw_pci_config_profile_swid_config(mlxsw_pci, mbox, i,  in mlxsw_pci_config_profile()
1299 		mlxsw_cmd_mbox_config_profile_set_cqe_version_set(mbox, 1);  in mlxsw_pci_config_profile()
1300 		mlxsw_cmd_mbox_config_profile_cqe_version_set(mbox, 1);  in mlxsw_pci_config_profile()
1304 		mlxsw_cmd_mbox_config_profile_set_cqe_time_stamp_type_set(mbox,  in mlxsw_pci_config_profile()
1306 		mlxsw_cmd_mbox_config_profile_cqe_time_stamp_type_set(mbox,  in mlxsw_pci_config_profile()
1310 	return mlxsw_cmd_config_profile_set(mlxsw_pci->core, mbox);  in mlxsw_pci_config_profile()
1313 static int mlxsw_pci_boardinfo(struct mlxsw_pci *mlxsw_pci, char *mbox)  in mlxsw_pci_boardinfo()  argument
1318 	mlxsw_cmd_mbox_zero(mbox);  in mlxsw_pci_boardinfo()
1319 	err = mlxsw_cmd_boardinfo(mlxsw_pci->core, mbox);  in mlxsw_pci_boardinfo()
1322 	mlxsw_cmd_mbox_boardinfo_vsd_memcpy_from(mbox, bus_info->vsd);  in mlxsw_pci_boardinfo()
1323 	mlxsw_cmd_mbox_boardinfo_psid_memcpy_from(mbox, bus_info->psid);  in mlxsw_pci_boardinfo()
1327 static int mlxsw_pci_fw_area_init(struct mlxsw_pci *mlxsw_pci, char *mbox,  in mlxsw_pci_fw_area_init()  argument
1341 	mlxsw_cmd_mbox_zero(mbox);  in mlxsw_pci_fw_area_init()
1353 		mlxsw_cmd_mbox_map_fa_pa_set(mbox, nent, mem_item->mapaddr);  in mlxsw_pci_fw_area_init()
1354 		mlxsw_cmd_mbox_map_fa_log2size_set(mbox, nent, 0); /* 1 page */  in mlxsw_pci_fw_area_init()
1356 			err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);  in mlxsw_pci_fw_area_init()
1360 			mlxsw_cmd_mbox_zero(mbox);  in mlxsw_pci_fw_area_init()
1365 		err = mlxsw_cmd_map_fa(mlxsw_pci->core, mbox, nent);  in mlxsw_pci_fw_area_init()
1414 				struct mlxsw_pci_mem_item *mbox)  in mlxsw_pci_mbox_alloc()  argument
1419 	mbox->size = MLXSW_CMD_MBOX_SIZE;  in mlxsw_pci_mbox_alloc()
1420 	mbox->buf = dma_alloc_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE,  in mlxsw_pci_mbox_alloc()
1421 				       &mbox->mapaddr, GFP_KERNEL);  in mlxsw_pci_mbox_alloc()
1422 	if (!mbox->buf) {  in mlxsw_pci_mbox_alloc()
1431 				struct mlxsw_pci_mem_item *mbox)  in mlxsw_pci_mbox_free()  argument
1435 	dma_free_coherent(&pdev->dev, MLXSW_CMD_MBOX_SIZE, mbox->buf,  in mlxsw_pci_mbox_free()
1436 			  mbox->mapaddr);  in mlxsw_pci_mbox_free()
1513 	char *mbox;  in mlxsw_pci_init()  local
1519 	mbox = mlxsw_cmd_mbox_alloc();  in mlxsw_pci_init()
1520 	if (!mbox)  in mlxsw_pci_init()
1533 	err = mlxsw_cmd_query_fw(mlxsw_core, mbox);  in mlxsw_pci_init()
1538 		mlxsw_cmd_mbox_query_fw_fw_rev_major_get(mbox);  in mlxsw_pci_init()
1540 		mlxsw_cmd_mbox_query_fw_fw_rev_minor_get(mbox);  in mlxsw_pci_init()
1542 		mlxsw_cmd_mbox_query_fw_fw_rev_subminor_get(mbox);  in mlxsw_pci_init()
1544 	if (mlxsw_cmd_mbox_query_fw_cmd_interface_rev_get(mbox) != 1) {  in mlxsw_pci_init()
1549 	if (mlxsw_cmd_mbox_query_fw_doorbell_page_bar_get(mbox) != 0) {  in mlxsw_pci_init()
1556 		mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);  in mlxsw_pci_init()
1558 	if (mlxsw_cmd_mbox_query_fw_fr_rn_clk_bar_get(mbox) != 0) {  in mlxsw_pci_init()
1565 		mlxsw_cmd_mbox_query_fw_free_running_clock_offset_get(mbox);  in mlxsw_pci_init()
1567 	if (mlxsw_cmd_mbox_query_fw_utc_sec_bar_get(mbox) != 0) {  in mlxsw_pci_init()
1574 		mlxsw_cmd_mbox_query_fw_utc_sec_offset_get(mbox);  in mlxsw_pci_init()
1576 	if (mlxsw_cmd_mbox_query_fw_utc_nsec_bar_get(mbox) != 0) {  in mlxsw_pci_init()
1583 		mlxsw_cmd_mbox_query_fw_utc_nsec_offset_get(mbox);  in mlxsw_pci_init()
1585 	num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);  in mlxsw_pci_init()
1586 	err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);  in mlxsw_pci_init()
1590 	err = mlxsw_pci_boardinfo(mlxsw_pci, mbox);  in mlxsw_pci_init()
1594 	err = mlxsw_core_resources_query(mlxsw_core, mbox, res);  in mlxsw_pci_init()
1613 	err = mlxsw_pci_config_profile(mlxsw_pci, mbox, profile, res);  in mlxsw_pci_init()
1621 	err = mlxsw_core_resources_query(mlxsw_core, mbox, res);  in mlxsw_pci_init()
1625 	err = mlxsw_pci_aqs_init(mlxsw_pci, mbox);  in mlxsw_pci_init()
1659 	mlxsw_cmd_mbox_free(mbox);  in mlxsw_pci_init()
1841 		 * copy registers into mbox buffer.  in mlxsw_pci_cmd_exec()