Lines Matching full:bit
9 #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15)
10 #define MTK_WDMA_DESC_CTRL_BURST BIT(16)
12 #define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30)
13 #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31)
23 #define MTK_WED_RESET_TX_BM BIT(0)
24 #define MTK_WED_RESET_TX_FREE_AGENT BIT(4)
25 #define MTK_WED_RESET_WPDMA_TX_DRV BIT(8)
26 #define MTK_WED_RESET_WPDMA_RX_DRV BIT(9)
27 #define MTK_WED_RESET_WPDMA_INT_AGENT BIT(11)
28 #define MTK_WED_RESET_WED_TX_DMA BIT(12)
29 #define MTK_WED_RESET_WDMA_RX_DRV BIT(17)
30 #define MTK_WED_RESET_WDMA_INT_AGENT BIT(19)
31 #define MTK_WED_RESET_WED BIT(31)
34 #define MTK_WED_CTRL_WPDMA_INT_AGENT_EN BIT(0)
35 #define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY BIT(1)
36 #define MTK_WED_CTRL_WDMA_INT_AGENT_EN BIT(2)
37 #define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY BIT(3)
38 #define MTK_WED_CTRL_WED_TX_BM_EN BIT(8)
39 #define MTK_WED_CTRL_WED_TX_BM_BUSY BIT(9)
40 #define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN BIT(10)
41 #define MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY BIT(11)
42 #define MTK_WED_CTRL_RESERVE_EN BIT(12)
43 #define MTK_WED_CTRL_RESERVE_BUSY BIT(13)
44 #define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24)
45 #define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25)
46 #define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28)
49 #define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR BIT(0)
50 #define MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD BIT(1)
51 #define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4)
52 #define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8)
53 #define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9)
54 #define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(12)
55 #define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(13)
56 #define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16)
57 #define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR BIT(17)
58 #define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT BIT(18)
59 #define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN BIT(19)
60 #define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT BIT(20)
61 #define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR BIT(21)
62 #define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR BIT(22)
63 #define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR BIT(23)
64 #define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24)
81 #define MTK_WED_TX_BM_CTRL_PAUSE BIT(28)
95 #define MTK_WED_TX_BM_INTF_TKID_VALID BIT(28)
96 #define MTK_WED_TX_BM_INTF_TKID_READ BIT(29)
107 #define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28)
117 #define MTK_WED_TXDP_DW9_OVERWR BIT(9)
124 #define MTK_WED_GLO_CFG_TX_DMA_EN BIT(0)
125 #define MTK_WED_GLO_CFG_TX_DMA_BUSY BIT(1)
126 #define MTK_WED_GLO_CFG_RX_DMA_EN BIT(2)
127 #define MTK_WED_GLO_CFG_RX_DMA_BUSY BIT(3)
129 #define MTK_WED_GLO_CFG_TX_WB_DDONE BIT(6)
130 #define MTK_WED_GLO_CFG_BIG_ENDIAN BIT(7)
131 #define MTK_WED_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8)
132 #define MTK_WED_GLO_CFG_TX_BT_SIZE_LO BIT(9)
134 #define MTK_WED_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
137 #define MTK_WED_GLO_CFG_SW_RESET BIT(24)
138 #define MTK_WED_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)
139 #define MTK_WED_GLO_CFG_OMIT_RX_INFO BIT(27)
140 #define MTK_WED_GLO_CFG_OMIT_TX_INFO BIT(28)
141 #define MTK_WED_GLO_CFG_BYTE_SWAP BIT(29)
142 #define MTK_WED_GLO_CFG_RX_2B_OFFSET BIT(31)
156 #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE BIT(1)
160 #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN BIT(0)
161 #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY BIT(1)
162 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN BIT(2)
163 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY BIT(3)
165 #define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE BIT(6)
166 #define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
167 #define MTK_WED_WPDMA_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8)
168 #define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_LO BIT(9)
170 #define MTK_WED_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
173 #define MTK_WED_WPDMA_GLO_CFG_SW_RESET BIT(24)
174 #define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)
175 #define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27)
176 #define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28)
177 #define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP BIT(29)
178 #define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
181 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC BIT(4)
182 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC BIT(5)
183 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC BIT(6)
184 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC BIT(7)
186 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT BIT(19)
187 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UEVENT_PKT_FMT_CHK BIT(20)
188 #define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR BIT(21)
189 #define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP BIT(24)
190 #define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV BIT(28)
197 #define MTK_WED_WPDMA_CTRL_SDL1_FIXED BIT(31)
200 #define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV BIT(21)
201 #define MTK_WED_WPDMA_INT_CTRL_SIG_SRC BIT(22)
207 #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN BIT(0)
208 #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR BIT(1)
210 #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN BIT(8)
211 #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR BIT(9)
217 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN BIT(0)
218 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR BIT(1)
227 #define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16)
230 #define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20)
248 #define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN BIT(0)
249 #define MTK_WED_WDMA_GLO_CFG_RX_DRV_EN BIT(2)
250 #define MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY BIT(3)
252 #define MTK_WED_WDMA_GLO_CFG_TX_WB_DDONE BIT(6)
253 #define MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE BIT(13)
254 #define MTK_WED_WDMA_GLO_CFG_WCOMPLETE_SEL BIT(16)
255 #define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_RXDMA_BYPASS BIT(17)
256 #define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_BYPASS BIT(18)
257 #define MTK_WED_WDMA_GLO_CFG_FSM_RETURN_IDLE BIT(19)
258 #define MTK_WED_WDMA_GLO_CFG_WAIT_COHERENT BIT(20)
259 #define MTK_WED_WDMA_GLO_CFG_AXI_W_AFTER_AW BIT(21)
260 #define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY_SINGLE_W BIT(22)
261 #define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY BIT(23)
262 #define MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP BIT(24)
263 #define MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE BIT(25)
264 #define MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE BIT(26)
265 #define MTK_WED_WDMA_GLO_CFG_RXDRV_CLKGATE_BYPASS BIT(30)
302 #define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0)
303 #define MTK_WDMA_GLO_CFG_RX_DMA_EN BIT(2)
304 #define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES BIT(26)
305 #define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27)
306 #define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES BIT(28)
317 #define MTK_WDMA_INT_MASK_TX_DELAY BIT(28)
318 #define MTK_WDMA_INT_MASK_TX_COHERENT BIT(29)
319 #define MTK_WDMA_INT_MASK_RX_DELAY BIT(30)
320 #define MTK_WDMA_INT_MASK_RX_COHERENT BIT(31)
326 #define MTK_PCIE_MIRROR_MAP_EN BIT(0)
327 #define MTK_PCIE_MIRROR_MAP_WED_ID BIT(1)