Lines Matching +full:0 +full:x238

7 #define MTK_PPE_GLO_CFG				0x200
8 #define MTK_PPE_GLO_CFG_EN			BIT(0)
23 #define MTK_PPE_FLOW_CFG			0x204
42 #define MTK_PPE_IP_PROTO_CHK			0x208
43 #define MTK_PPE_IP_PROTO_CHK_IPV4		GENMASK(15, 0)
46 #define MTK_PPE_TB_CFG				0x21c
47 #define MTK_PPE_TB_CFG_ENTRY_NUM		GENMASK(2, 0)
80 #define MTK_PPE_TB_BASE				0x220
82 #define MTK_PPE_TB_USED				0x224
83 #define MTK_PPE_TB_USED_NUM			GENMASK(13, 0)
85 #define MTK_PPE_BIND_RATE			0x228
86 #define MTK_PPE_BIND_RATE_BIND			GENMASK(15, 0)
89 #define MTK_PPE_BIND_LIMIT0			0x22c
90 #define MTK_PPE_BIND_LIMIT0_QUARTER		GENMASK(13, 0)
93 #define MTK_PPE_BIND_LIMIT1			0x230
94 #define MTK_PPE_BIND_LIMIT1_FULL		GENMASK(13, 0)
97 #define MTK_PPE_KEEPALIVE			0x234
98 #define MTK_PPE_KEEPALIVE_TIME			GENMASK(15, 0)
102 #define MTK_PPE_UNBIND_AGE			0x238
104 #define MTK_PPE_UNBIND_AGE_DELTA		GENMASK(7, 0)
106 #define MTK_PPE_BIND_AGE0			0x23c
108 #define MTK_PPE_BIND_AGE0_DELTA_UDP		GENMASK(14, 0)
110 #define MTK_PPE_BIND_AGE1			0x240
112 #define MTK_PPE_BIND_AGE1_DELTA_TCP		GENMASK(14, 0)
114 #define MTK_PPE_HASH_SEED			0x244
116 #define MTK_PPE_DEFAULT_CPU_PORT		0x248
117 #define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n)	(GENMASK(2, 0) << ((_n) * 4))
119 #define MTK_PPE_DEFAULT_CPU_PORT1		0x24c
121 #define MTK_PPE_MTU_DROP			0x308
123 #define MTK_PPE_VLAN_MTU0			0x30c
124 #define MTK_PPE_VLAN_MTU0_NONE			GENMASK(13, 0)
127 #define MTK_PPE_VLAN_MTU1			0x310
128 #define MTK_PPE_VLAN_MTU1_2TAG			GENMASK(13, 0)
131 #define MTK_PPE_VPM_TPID			0x318
133 #define MTK_PPE_CACHE_CTL			0x320
134 #define MTK_PPE_CACHE_CTL_EN			BIT(0)
140 #define MTK_PPE_MIB_CFG				0x334
141 #define MTK_PPE_MIB_CFG_EN			BIT(0)
144 #define MTK_PPE_MIB_TB_BASE			0x338
146 #define MTK_PPE_MIB_CACHE_CTL			0x350
147 #define MTK_PPE_MIB_CACHE_CTL_EN		BIT(0)
150 #define MTK_PPE_SBW_CTRL			0x374