Lines Matching full:gmac
74 P_CLK_REF_LNK1_GM_DIS = 1<<7, /* Disable Clock Ref. Link1 GMAC */
75 P_CLK_COR_LNK1_GM_DIS = 1<<6, /* Disable Clock Core Link1 GMAC */
829 /* Receive GMAC FIFO (YUKON and Yukon-2) */
831 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
832 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
833 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
834 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
835 RX_GMF_FL_THR = 0x0c50,/* 16 bit Rx GMAC FIFO Flush Threshold */
836 RX_GMF_FL_CTRL = 0x0c52,/* 16 bit Rx GMAC FIFO Flush Control */
841 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
843 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
845 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
847 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
974 /* Transmit GMAC FIFO (YUKON only) */
976 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
977 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
978 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
980 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
981 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
982 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
984 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
985 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
986 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
1098 /* GMAC and GPHY Control Registers (YUKON only) */
1100 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
1102 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
1103 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
1130 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
1131 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
1135 * Marvel-PHY Registers, indirect addressed over GMAC
1629 /* GMAC registers */
1723 /* GMAC Bit Definitions */
1862 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1899 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1900 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1907 /* RX_GMF_FL_CTRL 16 bit Rx GMAC FIFO Flush Control (Yukon-Supreme) */
1921 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1926 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
2013 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
2030 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
2031 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
2062 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
2063 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
2075 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
2077 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
2078 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */