278 static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data)  in wrl()  function
289 		wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT);  in abort_dma()
557 	wrl(pep, HTPR, pep->htpr_dma);  in init_hash_table()
572 	wrl(pep, PORT_CONFIG, val);  in pxa168_eth_set_rx_mode()
618 	wrl(pep, MAC_ADDR_HIGH, mac_h);  in pxa168_eth_set_mac_address()
619 	wrl(pep, MAC_ADDR_LOW, mac_l);  in pxa168_eth_set_mac_address()
637 	wrl(pep, ETH_C_TX_DESC_1,  in eth_port_start()
642 	wrl(pep, ETH_C_RX_DESC_0,  in eth_port_start()
645 	wrl(pep, ETH_F_RX_DESC_0,  in eth_port_start()
649 	wrl(pep, INT_CAUSE, 0);  in eth_port_start()
652 	wrl(pep, INT_MASK, ALL_INTS);  in eth_port_start()
656 	wrl(pep, PORT_CONFIG, val);  in eth_port_start()
661 	wrl(pep, SDMA_CMD, val);  in eth_port_start()
670 	wrl(pep, INT_MASK, 0);  in eth_port_reset()
673 	wrl(pep, INT_CAUSE, 0);  in eth_port_reset()
687 	wrl(pep, PORT_CONFIG, val);  in eth_port_reset()
850 	wrl(pep, INT_CAUSE, ~icr);  in pxa168_eth_collect_events()
868 	wrl(pep, INT_MASK, 0);  in pxa168_eth_int_handler()
917 	wrl(pep, PORT_CONFIG_EXT,  in set_port_config_ext()
952 	wrl(pep, PORT_CONFIG, cfg);  in pxa168_eth_adjust_link()
953 	wrl(pep, PORT_CONFIG_EXT, cfgext);  in pxa168_eth_adjust_link()
994 	wrl(pep, INT_MASK, 0);  in pxa168_init_hw()
995 	wrl(pep, INT_CAUSE, 0);  in pxa168_init_hw()
997 	wrl(pep, INT_W_CLEAR, 0);  in pxa168_init_hw()
1007 	wrl(pep, SDMA_CONFIG, SDCR_BSZ8 |	/* Burst size = 32 bytes */  in pxa168_init_hw()
1013 	wrl(pep, PORT_CONFIG, PCR_HS);		/* Hash size is 1/2kb */  in pxa168_init_hw()
1173 	wrl(pep, INT_MASK, 0);  in pxa168_eth_stop()
1174 	wrl(pep, INT_CAUSE, 0);  in pxa168_eth_stop()
1176 	wrl(pep, INT_W_CLEAR, 0);  in pxa168_eth_stop()
1244 		wrl(pep, INT_MASK, ALL_INTS);  in pxa168_rx_poll()
1273 	wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD);  in pxa168_eth_start_xmit()
1310 	wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R);  in pxa168_smi_read()
1334 	wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) |  in pxa168_smi_write()