Lines Matching +full:0 +full:xff000
16 #define PCI_DEVID_OTX2_CPT_PF 0xA0FD
17 #define PCI_DEVID_OTX2_CPT10K_PF 0xA0F2
24 u64 free_sts = 0, busy_sts = 0; \
28 for (e = (e_min), i = 0; e < (e_max); e++, i++) { \
30 if (reg & 0x1) \
33 if (reg & 0x2) \
47 reg0 = rvu_read64(rvu, blkaddr, CPT_AF_FLTX_INT(0)); in rvu_cpt_af_flt_intr_handler()
52 "Received CPTAF FLT irq : 0x%llx, 0x%llx, 0x%llx", in rvu_cpt_af_flt_intr_handler()
56 "Received CPTAF FLT irq : 0x%llx, 0x%llx", in rvu_cpt_af_flt_intr_handler()
60 rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT(0), reg0); in rvu_cpt_af_flt_intr_handler()
76 dev_err_ratelimited(rvu->dev, "Received CPTAF RVU irq : 0x%llx", reg); in rvu_cpt_af_rvu_intr_handler()
90 dev_err_ratelimited(rvu->dev, "Received CPTAF RAS irq : 0x%llx", reg); in rvu_cpt_af_ras_intr_handler()
103 ret = request_irq(pci_irq_vector(rvu->pdev, irq_offs), handler, 0, in rvu_cpt_do_register_interrupt()
112 return 0; in rvu_cpt_do_register_interrupt()
122 for (i = 0; i < CPT_10K_AF_INT_VEC_RVU; i++) in cpt_10k_unregister_interrupts()
123 rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(i), 0x1); in cpt_10k_unregister_interrupts()
124 rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1C, 0x1); in cpt_10k_unregister_interrupts()
125 rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1C, 0x1); in cpt_10k_unregister_interrupts()
127 for (i = 0; i < CPT_10K_AF_INT_VEC_CNT; i++) in cpt_10k_unregister_interrupts()
142 offs = rvu_read64(rvu, blkaddr, CPT_PRIV_AF_INT_CFG) & 0x7FF; in cpt_unregister_interrupts()
153 for (i = 0; i < CPT_AF_INT_VEC_RVU; i++) in cpt_unregister_interrupts()
154 rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(i), 0x1); in cpt_unregister_interrupts()
155 rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1C, 0x1); in cpt_unregister_interrupts()
156 rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1C, 0x1); in cpt_unregister_interrupts()
158 for (i = 0; i < CPT_AF_INT_VEC_CNT; i++) in cpt_unregister_interrupts()
184 rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1S(i), 0x1); in cpt_10k_register_interrupts()
192 rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1S, 0x1); in cpt_10k_register_interrupts()
199 rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1S, 0x1); in cpt_10k_register_interrupts()
201 return 0; in cpt_10k_register_interrupts()
211 int i, offs, ret = 0; in cpt_register_interrupts()
215 return 0; in cpt_register_interrupts()
218 offs = rvu_read64(rvu, blkaddr, CPT_PRIV_AF_INT_CFG) & 0x7FF; in cpt_register_interrupts()
222 return 0; in cpt_register_interrupts()
235 rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1S(i), 0x1); in cpt_register_interrupts()
243 rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1S, 0x1); in cpt_register_interrupts()
250 rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1S, 0x1); in cpt_register_interrupts()
252 return 0; in cpt_register_interrupts()
275 for (i = 0; i < rvu->hw->total_pfs; i++) { in get_cpt_pf_num()
276 pdev = pci_get_domain_bus_and_slot(domain_nr, i + 1, 0); in get_cpt_pf_num()
337 if (blkaddr < 0) in rvu_mbox_handler_cpt_lf_alloc()
340 if (req->eng_grpmsk == 0x0) in rvu_mbox_handler_cpt_lf_alloc()
367 for (slot = 0; slot < num_lfs; slot++) { in rvu_mbox_handler_cpt_lf_alloc()
369 if (cptlf < 0) in rvu_mbox_handler_cpt_lf_alloc()
389 return 0; in rvu_mbox_handler_cpt_lf_alloc()
402 return 0; in cpt_lf_free()
404 for (slot = 0; slot < num_lfs; slot++) { in cpt_lf_free()
406 if (cptlf < 0) in cpt_lf_free()
420 return 0; in cpt_lf_free()
457 nix_sel = (blkaddr == BLKADDR_CPT1) ? 1 : 0; in cpt_inline_ipsec_cfg_inbound()
476 rvu_write64(rvu, blkaddr, CPT_AF_ECO, 0x1); in cpt_inline_ipsec_cfg_inbound()
485 rvu_write64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(0), val); in cpt_inline_ipsec_cfg_inbound()
489 return 0; in cpt_inline_ipsec_cfg_inbound()
527 nix_sel = (nix_blkaddr == BLKADDR_NIX0) ? 0 : 1; in cpt_inline_ipsec_cfg_outbound()
534 return 0; in cpt_inline_ipsec_cfg_outbound()
548 if (blkaddr < 0) in rvu_mbox_handler_cpt_inline_ipsec_cfg()
554 if (cptlf < 0) in rvu_mbox_handler_cpt_inline_ipsec_cfg()
581 if (blkaddr < 0) in is_valid_offset()
585 if ((offset & 0xFF000) == CPT_AF_LFX_CTL(0) || in is_valid_offset()
586 (offset & 0xFF000) == CPT_AF_LFX_CTL2(0)) { in is_valid_offset()
590 lf = (offset & 0xFFF) >> 3; in is_valid_offset()
601 if (lf < 0) in is_valid_offset()
617 switch (offset & 0xFF000) { in is_valid_offset()
618 case CPT_AF_EXEX_STS(0): in is_valid_offset()
619 case CPT_AF_EXEX_CTL(0): in is_valid_offset()
620 case CPT_AF_EXEX_CTL2(0): in is_valid_offset()
621 case CPT_AF_EXEX_UCODE_BASE(0): in is_valid_offset()
640 if (blkaddr < 0) in rvu_mbox_handler_cpt_rd_wr_register()
660 return 0; in rvu_mbox_handler_cpt_rd_wr_register()
694 rsp->x2p_link_cfg0 = rvu_read64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(0)); in get_ctx_pc()
701 u32 e_min = 0, e_max = 0; in get_eng_sts()
705 max_ses = reg & 0xffff; in get_eng_sts()
706 max_ies = (reg >> 16) & 0xffff; in get_eng_sts()
707 max_aes = (reg >> 32) & 0xffff; in get_eng_sts()
714 e_min = 0; in get_eng_sts()
729 if (blkaddr < 0) in rvu_mbox_handler_cpt_sts()
754 return 0; in rvu_mbox_handler_cpt_sts()
760 #define RXC_ACTIVE_LIMIT GENMASK_ULL(11, 0)
785 if (blkaddr < 0) in rvu_mbox_handler_cpt_rxc_time_cfg()
795 return 0; in rvu_mbox_handler_cpt_rxc_time_cfg()
833 if (timeout == 0) in cpt_rxc_teardown()
846 if (timeout == 0) in cpt_rxc_teardown()
850 #define INPROG_INFLIGHT(reg) ((reg) & 0x1FF)
852 #define INPROG_GRB(reg) (((reg) >> 32) & 0xFF)
853 #define INPROG_GWB(reg) (((reg) >> 40) & 0xFF)
857 int i = 0, hard_lp_ctr = 100000; in cpt_lf_disable_iqueue()
862 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_CTL), 0x0); in cpt_lf_disable_iqueue()
876 i = 0; in cpt_lf_disable_iqueue()
885 nq_ptr = (grp_ptr >> 32) & 0x7FFF; in cpt_lf_disable_iqueue()
886 dq_ptr = grp_ptr & 0x7FFF; in cpt_lf_disable_iqueue()
890 if (hard_lp_ctr == 0) in cpt_lf_disable_iqueue()
893 i = 0; in cpt_lf_disable_iqueue()
899 if ((INPROG_INFLIGHT(inprog) == 0) && in cpt_lf_disable_iqueue()
901 ((INPROG_GRB(inprog) == 0) || in cpt_lf_disable_iqueue()
905 i = 0; in cpt_lf_disable_iqueue()
910 if (hard_lp_ctr == 0) in cpt_lf_disable_iqueue()
932 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, 0); in rvu_cpt_lf_teardown()
934 return 0; in rvu_cpt_lf_teardown()
963 *res = 0xFFFF; in cpt_inline_inb_lf_cmd_send()
979 inst[0] = 0; in cpt_inline_inb_lf_cmd_send()
982 inst[2] = 0; in cpt_inline_inb_lf_cmd_send()
985 inst[4] = 0; in cpt_inline_inb_lf_cmd_send()
986 inst[5] = 0; in cpt_inline_inb_lf_cmd_send()
987 inst[6] = 0; in cpt_inline_inb_lf_cmd_send()
994 cpt_idx = (blkaddr == BLKADDR_CPT0) ? 0 : 1; in cpt_inline_inb_lf_cmd_send()
1006 if (*res == 0xFFFF) in cpt_inline_inb_lf_cmd_send()
1012 if (timeout == 0) in cpt_inline_inb_lf_cmd_send()
1020 return 0; in cpt_inline_inb_lf_cmd_send()
1024 #define CTX_CAM_CPTR GENMASK_ULL(45, 0)
1030 int slot = 0, num_lfs; in rvu_cpt_ctx_flush()
1035 if (nix_blkaddr < 0) in rvu_cpt_ctx_flush()
1039 return 0; in rvu_cpt_ctx_flush()
1054 max_ctx_entries = (reg >> 48) & 0xFFF; in rvu_cpt_ctx_flush()
1060 if (num_lfs == 0) { in rvu_cpt_ctx_flush()
1069 for (i = 0; i < max_ctx_entries; i++) { in rvu_cpt_ctx_flush()
1080 rvu_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, 0); in rvu_cpt_ctx_flush()
1085 return 0; in rvu_cpt_ctx_flush()