41 	val = (0x8100ull & 0xFFFF) | BIT_ULL(20) | BIT_ULL(22);  in cnf10kb_mcs_parser_cfg()
43 	reg = MCSX_PEX_RX_SLAVE_CUSTOM_TAGX(0);  in cnf10kb_mcs_parser_cfg()
46 	reg = MCSX_PEX_TX_SLAVE_CUSTOM_TAGX(0);  in cnf10kb_mcs_parser_cfg()
50 	val = (0x88a8ull & 0xFFFF) | BIT_ULL(20) | BIT_ULL(23);  in cnf10kb_mcs_parser_cfg()
60 	/* Enable custom tage 0 and 1 and sectag */  in cnf10kb_mcs_parser_cfg()
61 	val = BIT_ULL(0) | BIT_ULL(1) | BIT_ULL(12);  in cnf10kb_mcs_parser_cfg()
74 	val = (map->secy & 0x3F) | (map->ctrl_pkt & 0x1) << 6;  in cnf10kb_mcs_flowid_secy_map()
80 		val |= (map->sc & 0x3F) << 7;  in cnf10kb_mcs_flowid_secy_map()
91 	val = (map->sa_index0 & 0x7F) | (map->sa_index1 & 0x7F) << 7;  in cnf10kb_mcs_tx_sa_mem_map_write()
116 	val = (map->sa_index & 0x7F) | (map->sa_in_use << 7);  in cnf10kb_mcs_rx_sa_mem_map_write()
134 		while (!(mcs_reg_read(mcs, MCSX_MIL_IP_GBL_STATUS) & BIT_ULL(0))) {  in mcs_set_force_clk_en()
145 	return 0;  in mcs_set_force_clk_en()
150  * one of two SAs mapped to SC gets expired. If tx_sa_active=0 implies
180 			event.sa_id = val & 0x7F;  in cnf10kb_mcs_tx_pn_thresh_reached_handler()
182 			event.sa_id = (val >> 7) & 0x7F;  in cnf10kb_mcs_tx_pn_thresh_reached_handler()
191 	struct mcs_intr_event event = { 0 };  in cnf10kb_mcs_tx_pn_wrapped_handler()
206 			event.sa_id = (val >> 7) & 0x7F;  in cnf10kb_mcs_tx_pn_wrapped_handler()
209 			event.sa_id = val & 0x7F;  in cnf10kb_mcs_tx_pn_wrapped_handler()