Lines Matching full:pe
22 static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe) in mvpp2_prs_hw_write() argument
26 if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1) in mvpp2_prs_hw_write()
30 pe->tcam[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK; in mvpp2_prs_hw_write()
33 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
35 mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram[i]); in mvpp2_prs_hw_write()
38 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_hw_write()
40 mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam[i]); in mvpp2_prs_hw_write()
46 int mvpp2_prs_init_from_hw(struct mvpp2 *priv, struct mvpp2_prs_entry *pe, in mvpp2_prs_init_from_hw() argument
54 memset(pe, 0, sizeof(*pe)); in mvpp2_prs_init_from_hw()
55 pe->index = tid; in mvpp2_prs_init_from_hw()
58 mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index); in mvpp2_prs_init_from_hw()
60 pe->tcam[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv, in mvpp2_prs_init_from_hw()
62 if (pe->tcam[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK) in mvpp2_prs_init_from_hw()
66 pe->tcam[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i)); in mvpp2_prs_init_from_hw()
69 mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index); in mvpp2_prs_init_from_hw()
71 pe->sram[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i)); in mvpp2_prs_init_from_hw()
101 static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu) in mvpp2_prs_tcam_lu_set() argument
103 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU(MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
104 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] &= ~MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
105 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU(lu & MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
106 pe->tcam[MVPP2_PRS_TCAM_LU_WORD] |= MVPP2_PRS_TCAM_LU_EN(MVPP2_PRS_LU_MASK); in mvpp2_prs_tcam_lu_set()
110 static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_set() argument
114 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(BIT(port)); in mvpp2_prs_tcam_port_set()
116 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(BIT(port)); in mvpp2_prs_tcam_port_set()
120 static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_port_map_set() argument
123 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT(MVPP2_PRS_PORT_MASK); in mvpp2_prs_tcam_port_map_set()
124 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] &= ~MVPP2_PRS_TCAM_PORT_EN(MVPP2_PRS_PORT_MASK); in mvpp2_prs_tcam_port_map_set()
125 pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] |= MVPP2_PRS_TCAM_PORT_EN(~ports & MVPP2_PRS_PORT_MASK); in mvpp2_prs_tcam_port_map_set()
129 unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_port_map_get() argument
131 return (~pe->tcam[MVPP2_PRS_TCAM_PORT_WORD] >> 24) & MVPP2_PRS_PORT_MASK; in mvpp2_prs_tcam_port_map_get()
135 static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_set() argument
141 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(0xff << pos); in mvpp2_prs_tcam_data_byte_set()
142 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] &= ~(MVPP2_PRS_TCAM_EN(0xff) << pos); in mvpp2_prs_tcam_data_byte_set()
143 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= byte << pos; in mvpp2_prs_tcam_data_byte_set()
144 pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] |= MVPP2_PRS_TCAM_EN(enable << pos); in mvpp2_prs_tcam_data_byte_set()
148 void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_data_byte_get() argument
154 *byte = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> pos) & 0xff; in mvpp2_prs_tcam_data_byte_get()
155 *enable = (pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] >> (pos + 16)) & 0xff; in mvpp2_prs_tcam_data_byte_get()
159 static bool mvpp2_prs_tcam_data_cmp(struct mvpp2_prs_entry *pe, int offs, in mvpp2_prs_tcam_data_cmp() argument
164 tcam_data = pe->tcam[MVPP2_PRS_BYTE_TO_WORD(offs)] & 0xffff; in mvpp2_prs_tcam_data_cmp()
169 static void mvpp2_prs_tcam_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_tcam_ai_update() argument
179 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= BIT(i); in mvpp2_prs_tcam_ai_update()
181 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] &= ~BIT(i); in mvpp2_prs_tcam_ai_update()
184 pe->tcam[MVPP2_PRS_TCAM_AI_WORD] |= MVPP2_PRS_TCAM_AI_EN(enable); in mvpp2_prs_tcam_ai_update()
188 static int mvpp2_prs_tcam_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_tcam_ai_get() argument
190 return pe->tcam[MVPP2_PRS_TCAM_AI_WORD] & MVPP2_PRS_AI_MASK; in mvpp2_prs_tcam_ai_get()
194 static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset, in mvpp2_prs_match_etype() argument
197 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff); in mvpp2_prs_match_etype()
198 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff); in mvpp2_prs_match_etype()
202 static void mvpp2_prs_match_vid(struct mvpp2_prs_entry *pe, int offset, in mvpp2_prs_match_vid() argument
205 mvpp2_prs_tcam_data_byte_set(pe, offset + 0, (vid & 0xf00) >> 8, 0xf); in mvpp2_prs_match_vid()
206 mvpp2_prs_tcam_data_byte_set(pe, offset + 1, vid & 0xff, 0xff); in mvpp2_prs_match_vid()
210 static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_set() argument
213 pe->sram[MVPP2_BIT_TO_WORD(bit_num)] |= (val << (MVPP2_BIT_IN_WORD(bit_num))); in mvpp2_prs_sram_bits_set()
217 static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num, in mvpp2_prs_sram_bits_clear() argument
220 pe->sram[MVPP2_BIT_TO_WORD(bit_num)] &= ~(val << (MVPP2_BIT_IN_WORD(bit_num))); in mvpp2_prs_sram_bits_clear()
224 static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ri_update() argument
234 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_OFFS + i, in mvpp2_prs_sram_ri_update()
237 mvpp2_prs_sram_bits_clear(pe, in mvpp2_prs_sram_ri_update()
241 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ri_update()
246 static int mvpp2_prs_sram_ri_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ri_get() argument
248 return pe->sram[MVPP2_PRS_SRAM_RI_WORD]; in mvpp2_prs_sram_ri_get()
252 static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_ai_update() argument
262 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_OFFS + i, in mvpp2_prs_sram_ai_update()
265 mvpp2_prs_sram_bits_clear(pe, in mvpp2_prs_sram_ai_update()
269 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1); in mvpp2_prs_sram_ai_update()
274 static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe) in mvpp2_prs_sram_ai_get() argument
281 bits = (pe->sram[ai_off] >> ai_shift) | in mvpp2_prs_sram_ai_get()
282 (pe->sram[ai_off + 1] << (32 - ai_shift)); in mvpp2_prs_sram_ai_get()
290 static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_next_lu_set() argument
295 mvpp2_prs_sram_bits_clear(pe, sram_next_off, in mvpp2_prs_sram_next_lu_set()
297 mvpp2_prs_sram_bits_set(pe, sram_next_off, lu); in mvpp2_prs_sram_next_lu_set()
303 static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift, in mvpp2_prs_sram_shift_set() argument
308 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
311 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1); in mvpp2_prs_sram_shift_set()
315 pe->sram[MVPP2_BIT_TO_WORD(MVPP2_PRS_SRAM_SHIFT_OFFS)] |= in mvpp2_prs_sram_shift_set()
319 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, in mvpp2_prs_sram_shift_set()
321 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op); in mvpp2_prs_sram_shift_set()
324 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_shift_set()
330 static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe, in mvpp2_prs_sram_offset_set() argument
336 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
339 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1); in mvpp2_prs_sram_offset_set()
343 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS, in mvpp2_prs_sram_offset_set()
345 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, in mvpp2_prs_sram_offset_set()
349 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, in mvpp2_prs_sram_offset_set()
351 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type); in mvpp2_prs_sram_offset_set()
354 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, in mvpp2_prs_sram_offset_set()
356 mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, in mvpp2_prs_sram_offset_set()
360 mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1); in mvpp2_prs_sram_offset_set()
366 struct mvpp2_prs_entry pe; in mvpp2_prs_flow_find() local
377 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_flow_find()
378 bits = mvpp2_prs_sram_ai_get(&pe); in mvpp2_prs_flow_find()
409 struct mvpp2_prs_entry pe; in mvpp2_prs_drop_fc() local
412 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_drop_fc()
415 pe.index = MVPP2_PE_FC_DROP; in mvpp2_prs_drop_fc()
416 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_drop_fc()
421 mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff); in mvpp2_prs_drop_fc()
423 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_drop_fc()
426 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_drop_fc()
427 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_drop_fc()
430 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_drop_fc()
433 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_drop_fc()
434 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_drop_fc()
440 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_drop_all_set() local
444 mvpp2_prs_init_from_hw(priv, &pe, MVPP2_PE_DROP_ALL); in mvpp2_prs_mac_drop_all_set()
447 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mac_drop_all_set()
448 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
449 pe.index = MVPP2_PE_DROP_ALL; in mvpp2_prs_mac_drop_all_set()
452 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_drop_all_set()
455 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_drop_all_set()
456 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_drop_all_set()
459 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_drop_all_set()
462 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_drop_all_set()
466 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_drop_all_set()
468 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_drop_all_set()
475 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_promisc_set() local
492 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_mac_promisc_set()
494 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mac_promisc_set()
495 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
496 pe.index = tid; in mvpp2_prs_mac_promisc_set()
499 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_promisc_set()
502 mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK); in mvpp2_prs_mac_promisc_set()
505 mvpp2_prs_tcam_data_byte_set(&pe, 0, cast_match, in mvpp2_prs_mac_promisc_set()
509 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_promisc_set()
513 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_promisc_set()
516 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_promisc_set()
520 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_mac_promisc_set()
522 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_promisc_set()
529 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_tag_set() local
542 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_dsa_tag_set()
545 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_dsa_tag_set()
546 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
547 pe.index = tid; in mvpp2_prs_dsa_tag_set()
550 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_set()
554 mvpp2_prs_tcam_data_byte_set(&pe, 0, in mvpp2_prs_dsa_tag_set()
560 mvpp2_prs_sram_ai_update(&pe, 1, in mvpp2_prs_dsa_tag_set()
563 mvpp2_prs_sram_ai_update(&pe, 0, in mvpp2_prs_dsa_tag_set()
567 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE, in mvpp2_prs_dsa_tag_set()
570 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_dsa_tag_set()
573 mvpp2_prs_sram_shift_set(&pe, shift, in mvpp2_prs_dsa_tag_set()
577 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_dsa_tag_set()
579 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_dsa_tag_set()
583 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_dsa_tag_set()
587 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_set()
589 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_tag_set()
596 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_tag_ethertype_set() local
613 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_dsa_tag_ethertype_set()
616 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_dsa_tag_ethertype_set()
617 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
618 pe.index = tid; in mvpp2_prs_dsa_tag_ethertype_set()
621 mvpp2_prs_match_etype(&pe, 0, ETH_P_EDSA); in mvpp2_prs_dsa_tag_ethertype_set()
622 mvpp2_prs_match_etype(&pe, 2, 0); in mvpp2_prs_dsa_tag_ethertype_set()
624 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DSA_MASK, in mvpp2_prs_dsa_tag_ethertype_set()
627 mvpp2_prs_sram_shift_set(&pe, 2 + MVPP2_ETH_TYPE_LEN + shift, in mvpp2_prs_dsa_tag_ethertype_set()
631 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_tag_ethertype_set()
635 mvpp2_prs_tcam_data_byte_set(&pe, in mvpp2_prs_dsa_tag_ethertype_set()
640 mvpp2_prs_sram_ai_update(&pe, 0, in mvpp2_prs_dsa_tag_ethertype_set()
643 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_tag_ethertype_set()
646 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_dsa_tag_ethertype_set()
648 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_dsa_tag_ethertype_set()
651 mvpp2_prs_tcam_port_map_set(&pe, port_mask); in mvpp2_prs_dsa_tag_ethertype_set()
655 mvpp2_prs_tcam_port_set(&pe, port, add); in mvpp2_prs_dsa_tag_ethertype_set()
657 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_tag_ethertype_set()
663 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_find() local
676 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_vlan_find()
677 match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid); in mvpp2_prs_vlan_find()
682 ri_bits = mvpp2_prs_sram_ri_get(&pe); in mvpp2_prs_vlan_find()
686 ai_bits = mvpp2_prs_tcam_ai_get(&pe); in mvpp2_prs_vlan_find()
705 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_add() local
709 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_add()
729 mvpp2_prs_init_from_hw(priv, &pe, tid_aux); in mvpp2_prs_vlan_add()
730 ri_bits = mvpp2_prs_sram_ri_get(&pe); in mvpp2_prs_vlan_add()
739 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_add()
740 pe.index = tid; in mvpp2_prs_vlan_add()
741 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
743 mvpp2_prs_match_etype(&pe, 0, tpid); in mvpp2_prs_vlan_add()
746 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vlan_add()
749 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_add()
752 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_SINGLE, in mvpp2_prs_vlan_add()
756 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_TRIPLE, in mvpp2_prs_vlan_add()
759 mvpp2_prs_tcam_ai_update(&pe, ai, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_add()
761 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_add()
763 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_vlan_add()
766 mvpp2_prs_tcam_port_map_set(&pe, port_map); in mvpp2_prs_vlan_add()
768 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_add()
790 struct mvpp2_prs_entry pe; in mvpp2_prs_double_vlan_find() local
803 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_double_vlan_find()
805 match = mvpp2_prs_tcam_data_cmp(&pe, 0, tpid1) && in mvpp2_prs_double_vlan_find()
806 mvpp2_prs_tcam_data_cmp(&pe, 4, tpid2); in mvpp2_prs_double_vlan_find()
811 ri_mask = mvpp2_prs_sram_ri_get(&pe) & MVPP2_PRS_RI_VLAN_MASK; in mvpp2_prs_double_vlan_find()
825 struct mvpp2_prs_entry pe; in mvpp2_prs_double_vlan_add() local
827 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_double_vlan_add()
852 mvpp2_prs_init_from_hw(priv, &pe, tid_aux); in mvpp2_prs_double_vlan_add()
853 ri_bits = mvpp2_prs_sram_ri_get(&pe); in mvpp2_prs_double_vlan_add()
863 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_double_vlan_add()
864 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
865 pe.index = tid; in mvpp2_prs_double_vlan_add()
869 mvpp2_prs_match_etype(&pe, 0, tpid1); in mvpp2_prs_double_vlan_add()
870 mvpp2_prs_match_etype(&pe, 4, tpid2); in mvpp2_prs_double_vlan_add()
872 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
874 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN, in mvpp2_prs_double_vlan_add()
876 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, in mvpp2_prs_double_vlan_add()
878 mvpp2_prs_sram_ai_update(&pe, ai | MVPP2_PRS_DBL_VLAN_AI_BIT, in mvpp2_prs_double_vlan_add()
881 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_double_vlan_add()
883 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_double_vlan_add()
887 mvpp2_prs_tcam_port_map_set(&pe, port_map); in mvpp2_prs_double_vlan_add()
888 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_double_vlan_add()
897 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_proto() local
910 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_proto()
911 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
912 pe.index = tid; in mvpp2_prs_ip4_proto()
915 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip4_proto()
916 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip4_proto()
919 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, -4, in mvpp2_prs_ip4_proto()
921 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_proto()
922 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask | MVPP2_PRS_RI_IP_FRAG_MASK); in mvpp2_prs_ip4_proto()
924 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, in mvpp2_prs_ip4_proto()
926 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, in mvpp2_prs_ip4_proto()
929 mvpp2_prs_tcam_data_byte_set(&pe, 5, proto, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip4_proto()
930 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_proto()
933 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_proto()
936 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
937 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_proto()
945 pe.index = tid; in mvpp2_prs_ip4_proto()
947 pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_ip4_proto()
948 pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_ip4_proto()
949 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); in mvpp2_prs_ip4_proto()
951 mvpp2_prs_sram_ri_update(&pe, ri | MVPP2_PRS_RI_IP_FRAG_TRUE, in mvpp2_prs_ip4_proto()
954 mvpp2_prs_tcam_data_byte_set(&pe, 2, 0x00, 0x0); in mvpp2_prs_ip4_proto()
955 mvpp2_prs_tcam_data_byte_set(&pe, 3, 0x00, 0x0); in mvpp2_prs_ip4_proto()
958 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_proto()
959 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_proto()
967 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_cast() local
975 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_cast()
976 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
977 pe.index = tid; in mvpp2_prs_ip4_cast()
981 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV4_MC, in mvpp2_prs_ip4_cast()
983 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, in mvpp2_prs_ip4_cast()
988 mvpp2_prs_tcam_data_byte_set(&pe, 0, mask, mask); in mvpp2_prs_ip4_cast()
989 mvpp2_prs_tcam_data_byte_set(&pe, 1, mask, mask); in mvpp2_prs_ip4_cast()
990 mvpp2_prs_tcam_data_byte_set(&pe, 2, mask, mask); in mvpp2_prs_ip4_cast()
991 mvpp2_prs_tcam_data_byte_set(&pe, 3, mask, mask); in mvpp2_prs_ip4_cast()
992 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_BCAST, in mvpp2_prs_ip4_cast()
1000 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
1002 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_cast()
1006 mvpp2_prs_sram_shift_set(&pe, -12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip4_cast()
1008 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_cast()
1011 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_cast()
1014 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_cast()
1015 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_cast()
1024 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_proto() local
1036 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_proto()
1037 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
1038 pe.index = tid; in mvpp2_prs_ip6_proto()
1041 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_proto()
1042 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_proto()
1043 mvpp2_prs_sram_ri_update(&pe, ri, ri_mask); in mvpp2_prs_ip6_proto()
1044 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip6_proto()
1048 mvpp2_prs_tcam_data_byte_set(&pe, 0, proto, MVPP2_PRS_TCAM_PROTO_MASK); in mvpp2_prs_ip6_proto()
1049 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_proto()
1052 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_proto()
1055 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_proto()
1056 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_proto()
1064 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_cast() local
1075 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_cast()
1076 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
1077 pe.index = tid; in mvpp2_prs_ip6_cast()
1080 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
1081 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_MCAST, in mvpp2_prs_ip6_cast()
1083 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_cast()
1086 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip6_cast()
1088 mvpp2_prs_tcam_data_byte_set(&pe, 0, MVPP2_PRS_IPV6_MC, in mvpp2_prs_ip6_cast()
1090 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); in mvpp2_prs_ip6_cast()
1092 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_cast()
1095 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_cast()
1096 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_cast()
1131 struct mvpp2_prs_entry pe; in mvpp2_prs_def_flow_init() local
1135 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_def_flow_init()
1136 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
1137 pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port; in mvpp2_prs_def_flow_init()
1140 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_def_flow_init()
1143 mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow_init()
1144 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow_init()
1147 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow_init()
1148 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_def_flow_init()
1155 struct mvpp2_prs_entry pe; in mvpp2_prs_mh_init() local
1157 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mh_init()
1159 pe.index = MVPP2_PE_MH_DEFAULT; in mvpp2_prs_mh_init()
1160 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1161 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, in mvpp2_prs_mh_init()
1163 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mh_init()
1166 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mh_init()
1169 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1170 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mh_init()
1173 pe.index = MVPP2_PE_MH_SKIP_PRS; in mvpp2_prs_mh_init()
1174 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1175 mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE, in mvpp2_prs_mh_init()
1177 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mh_init()
1178 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mh_init()
1181 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mh_init()
1184 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH); in mvpp2_prs_mh_init()
1185 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mh_init()
1193 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_init() local
1195 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mac_init()
1198 pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS; in mvpp2_prs_mac_init()
1199 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
1201 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_mac_init()
1203 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_mac_init()
1204 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_mac_init()
1207 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_mac_init()
1210 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_init()
1211 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_init()
1223 struct mvpp2_prs_entry pe; in mvpp2_prs_dsa_init() local
1256 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_dsa_init()
1257 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_dsa_init()
1258 pe.index = MVPP2_PE_DSA_DEFAULT; in mvpp2_prs_dsa_init()
1259 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_dsa_init()
1262 mvpp2_prs_sram_shift_set(&pe, 0, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_dsa_init()
1263 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_dsa_init()
1266 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_dsa_init()
1269 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_dsa_init()
1271 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_dsa_init()
1277 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_init() local
1279 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_init()
1282 pe.index = MVPP2_PE_VID_FLTR_DEFAULT; in mvpp2_prs_vid_init()
1283 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1285 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_EDSA_VID_AI_BIT); in mvpp2_prs_vid_init()
1288 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_LEN, in mvpp2_prs_vid_init()
1292 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_init()
1294 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_init()
1297 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vid_init()
1300 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1301 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_init()
1304 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_init()
1307 pe.index = MVPP2_PE_VID_EDSA_FLTR_DEFAULT; in mvpp2_prs_vid_init()
1308 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1310 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_EDSA_VID_AI_BIT, in mvpp2_prs_vid_init()
1314 mvpp2_prs_sram_shift_set(&pe, MVPP2_VLAN_TAG_EDSA_LEN, in mvpp2_prs_vid_init()
1318 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_init()
1320 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_init()
1323 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vid_init()
1326 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_init()
1327 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_init()
1333 struct mvpp2_prs_entry pe; in mvpp2_prs_etype_init() local
1342 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1343 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1344 pe.index = tid; in mvpp2_prs_etype_init()
1346 mvpp2_prs_match_etype(&pe, 0, ETH_P_PPP_SES); in mvpp2_prs_etype_init()
1348 mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE, in mvpp2_prs_etype_init()
1350 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_etype_init()
1351 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
1355 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1356 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1357 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1358 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK, in mvpp2_prs_etype_init()
1360 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1368 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1369 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1370 pe.index = tid; in mvpp2_prs_etype_init()
1372 mvpp2_prs_match_etype(&pe, 0, ETH_P_ARP); in mvpp2_prs_etype_init()
1375 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
1376 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
1377 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
1380 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1385 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1386 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1387 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1388 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP, in mvpp2_prs_etype_init()
1390 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1398 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1399 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1400 pe.index = tid; in mvpp2_prs_etype_init()
1402 mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE); in mvpp2_prs_etype_init()
1405 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
1406 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
1407 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1412 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1417 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1418 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1419 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1420 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC | in mvpp2_prs_etype_init()
1424 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1433 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1434 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1435 pe.index = tid; in mvpp2_prs_etype_init()
1437 mvpp2_prs_match_etype(&pe, 0, ETH_P_IP); in mvpp2_prs_etype_init()
1438 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_etype_init()
1443 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_etype_init()
1444 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
1447 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + in mvpp2_prs_etype_init()
1451 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_etype_init()
1456 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1457 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1458 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1459 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_etype_init()
1461 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1470 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_etype_init()
1471 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1472 pe.index = tid; in mvpp2_prs_etype_init()
1474 mvpp2_prs_match_etype(&pe, 0, ETH_P_IPV6); in mvpp2_prs_etype_init()
1477 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + in mvpp2_prs_etype_init()
1480 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_etype_init()
1481 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
1484 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1488 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1489 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1490 priv->prs_shadow[pe.index].finish = false; in mvpp2_prs_etype_init()
1491 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_etype_init()
1493 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1496 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_etype_init()
1497 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1498 pe.index = MVPP2_PE_ETH_TYPE_UN; in mvpp2_prs_etype_init()
1501 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_etype_init()
1504 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_etype_init()
1505 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_etype_init()
1506 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
1509 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_etype_init()
1514 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2); in mvpp2_prs_etype_init()
1515 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF; in mvpp2_prs_etype_init()
1516 priv->prs_shadow[pe.index].finish = true; in mvpp2_prs_etype_init()
1517 mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_etype_init()
1519 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_etype_init()
1533 struct mvpp2_prs_entry pe; in mvpp2_prs_vlan_init() local
1567 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_init()
1568 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1569 pe.index = MVPP2_PE_VLAN_DBL; in mvpp2_prs_vlan_init()
1571 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vlan_init()
1574 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vlan_init()
1575 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_DOUBLE, in mvpp2_prs_vlan_init()
1578 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_DBL_VLAN_AI_BIT, in mvpp2_prs_vlan_init()
1581 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vlan_init()
1584 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1585 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_init()
1588 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vlan_init()
1589 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1590 pe.index = MVPP2_PE_VLAN_NONE; in mvpp2_prs_vlan_init()
1592 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vlan_init()
1593 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_VLAN_NONE, in mvpp2_prs_vlan_init()
1597 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_vlan_init()
1600 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VLAN); in mvpp2_prs_vlan_init()
1601 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vlan_init()
1609 struct mvpp2_prs_entry pe; in mvpp2_prs_pppoe_init() local
1618 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_pppoe_init()
1619 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1620 pe.index = tid; in mvpp2_prs_pppoe_init()
1622 mvpp2_prs_match_etype(&pe, 0, PPP_IP); in mvpp2_prs_pppoe_init()
1624 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_pppoe_init()
1625 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT, in mvpp2_prs_pppoe_init()
1628 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + in mvpp2_prs_pppoe_init()
1632 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
1637 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1638 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1646 pe.index = tid; in mvpp2_prs_pppoe_init()
1648 mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN, in mvpp2_prs_pppoe_init()
1655 pe.sram[MVPP2_PRS_SRAM_RI_WORD] = 0x0; in mvpp2_prs_pppoe_init()
1656 pe.sram[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0; in mvpp2_prs_pppoe_init()
1657 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4, in mvpp2_prs_pppoe_init()
1661 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1662 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1670 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_pppoe_init()
1671 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1672 pe.index = tid; in mvpp2_prs_pppoe_init()
1674 mvpp2_prs_match_etype(&pe, 0, PPP_IPV6); in mvpp2_prs_pppoe_init()
1676 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_pppoe_init()
1677 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6, in mvpp2_prs_pppoe_init()
1680 mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 + in mvpp2_prs_pppoe_init()
1684 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
1689 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1690 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1698 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_pppoe_init()
1699 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1700 pe.index = tid; in mvpp2_prs_pppoe_init()
1702 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN, in mvpp2_prs_pppoe_init()
1706 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_pppoe_init()
1707 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_pppoe_init()
1709 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, in mvpp2_prs_pppoe_init()
1714 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_PPPOE); in mvpp2_prs_pppoe_init()
1715 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_pppoe_init()
1723 struct mvpp2_prs_entry pe; in mvpp2_prs_ip4_init() local
1756 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_init()
1757 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1758 pe.index = MVPP2_PE_IP4_PROTO_UN; in mvpp2_prs_ip4_init()
1761 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip4_init()
1762 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip4_init()
1765 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3, -4, in mvpp2_prs_ip4_init()
1767 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_init()
1768 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip4_init()
1771 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_init()
1774 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_init()
1777 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1778 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_init()
1781 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip4_init()
1782 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1783 pe.index = MVPP2_PE_IP4_ADDR_UN; in mvpp2_prs_ip4_init()
1786 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1788 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV4_DIP_AI_BIT, in mvpp2_prs_ip4_init()
1792 mvpp2_prs_sram_shift_set(&pe, -12, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip4_init()
1794 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, in mvpp2_prs_ip4_init()
1796 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV4_DIP_AI_BIT); in mvpp2_prs_ip4_init()
1799 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip4_init()
1802 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip4_init()
1803 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip4_init()
1811 struct mvpp2_prs_entry pe; in mvpp2_prs_ip6_init() local
1854 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_init()
1855 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1856 pe.index = tid; in mvpp2_prs_ip6_init()
1859 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
1860 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
1861 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN | in mvpp2_prs_ip6_init()
1866 mvpp2_prs_tcam_data_byte_set(&pe, 1, 0x00, MVPP2_PRS_IPV6_HOP_MASK); in mvpp2_prs_ip6_init()
1867 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1871 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1872 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1875 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_ip6_init()
1876 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1877 pe.index = MVPP2_PE_IP6_PROTO_UN; in mvpp2_prs_ip6_init()
1880 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
1881 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
1882 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip6_init()
1885 mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L4, in mvpp2_prs_ip6_init()
1889 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1892 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
1895 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1896 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1899 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
1900 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1901 pe.index = MVPP2_PE_IP6_EXT_PROTO_UN; in mvpp2_prs_ip6_init()
1904 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_ip6_init()
1905 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1); in mvpp2_prs_ip6_init()
1906 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L4_OTHER, in mvpp2_prs_ip6_init()
1909 mvpp2_prs_tcam_ai_update(&pe, MVPP2_PRS_IPV6_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1912 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
1915 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP4); in mvpp2_prs_ip6_init()
1916 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1919 memset(&pe, 0, sizeof(struct mvpp2_prs_entry)); in mvpp2_prs_ip6_init()
1920 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1921 pe.index = MVPP2_PE_IP6_ADDR_UN; in mvpp2_prs_ip6_init()
1924 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1925 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UCAST, in mvpp2_prs_ip6_init()
1927 mvpp2_prs_sram_ai_update(&pe, MVPP2_PRS_IPV6_NO_EXT_AI_BIT, in mvpp2_prs_ip6_init()
1930 mvpp2_prs_sram_shift_set(&pe, -18, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_ip6_init()
1932 mvpp2_prs_tcam_ai_update(&pe, 0, MVPP2_PRS_IPV6_NO_EXT_AI_BIT); in mvpp2_prs_ip6_init()
1934 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_ip6_init()
1937 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_IP6); in mvpp2_prs_ip6_init()
1938 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_ip6_init()
1947 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_range_find() local
1958 mvpp2_prs_init_from_hw(port->priv, &pe, tid); in mvpp2_prs_vid_range_find()
1960 mvpp2_prs_tcam_data_byte_get(&pe, 2, &byte[0], &enable[0]); in mvpp2_prs_vid_range_find()
1961 mvpp2_prs_tcam_data_byte_get(&pe, 3, &byte[1], &enable[1]); in mvpp2_prs_vid_range_find()
1982 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_entry_add() local
1985 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_entry_add()
2008 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_entry_add()
2009 pe.index = tid; in mvpp2_prs_vid_entry_add()
2012 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_vid_entry_add()
2014 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_vid_entry_add()
2018 mvpp2_prs_tcam_port_set(&pe, port->id, true); in mvpp2_prs_vid_entry_add()
2021 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_entry_add()
2024 mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_vid_entry_add()
2027 mvpp2_prs_match_vid(&pe, MVPP2_PRS_VID_TCAM_BYTE, vid); in mvpp2_prs_vid_entry_add()
2030 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_entry_add()
2033 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_entry_add()
2034 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_entry_add()
2089 struct mvpp2_prs_entry pe; in mvpp2_prs_vid_enable_filtering() local
2094 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_vid_enable_filtering()
2096 pe.index = tid; in mvpp2_prs_vid_enable_filtering()
2104 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_enable_filtering()
2107 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_vid_enable_filtering()
2110 mvpp2_prs_tcam_port_set(&pe, port->id, true); in mvpp2_prs_vid_enable_filtering()
2113 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_L2); in mvpp2_prs_vid_enable_filtering()
2116 mvpp2_prs_sram_shift_set(&pe, shift, MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD); in mvpp2_prs_vid_enable_filtering()
2119 mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK, in mvpp2_prs_vid_enable_filtering()
2123 mvpp2_prs_sram_ai_update(&pe, 0, MVPP2_PRS_SRAM_AI_MASK); in mvpp2_prs_vid_enable_filtering()
2126 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_VID); in mvpp2_prs_vid_enable_filtering()
2127 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_vid_enable_filtering()
2198 static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe, in mvpp2_prs_mac_range_equals() argument
2205 mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask); in mvpp2_prs_mac_range_equals()
2221 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_da_range_find() local
2234 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_mac_da_range_find()
2235 entry_pmap = mvpp2_prs_tcam_port_map_get(&pe); in mvpp2_prs_mac_da_range_find()
2237 if (mvpp2_prs_mac_range_equals(&pe, da, mask) && in mvpp2_prs_mac_da_range_find()
2251 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_da_accept() local
2254 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_mac_da_accept()
2273 pe.index = tid; in mvpp2_prs_mac_da_accept()
2276 mvpp2_prs_tcam_port_map_set(&pe, 0); in mvpp2_prs_mac_da_accept()
2278 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_mac_da_accept()
2281 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
2284 mvpp2_prs_tcam_port_set(&pe, port->id, add); in mvpp2_prs_mac_da_accept()
2287 pmap = mvpp2_prs_tcam_port_map_get(&pe); in mvpp2_prs_mac_da_accept()
2292 mvpp2_prs_hw_inv(priv, pe.index); in mvpp2_prs_mac_da_accept()
2293 priv->prs_shadow[pe.index].valid = false; in mvpp2_prs_mac_da_accept()
2298 mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA); in mvpp2_prs_mac_da_accept()
2303 mvpp2_prs_tcam_data_byte_set(&pe, len, da[len], 0xff); in mvpp2_prs_mac_da_accept()
2317 mvpp2_prs_sram_ri_update(&pe, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
2319 mvpp2_prs_shadow_ri_set(priv, pe.index, ri, MVPP2_PRS_RI_L2_CAST_MASK | in mvpp2_prs_mac_da_accept()
2323 mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN, in mvpp2_prs_mac_da_accept()
2327 priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_MAC_DEF; in mvpp2_prs_mac_da_accept()
2328 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC); in mvpp2_prs_mac_da_accept()
2329 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_mac_da_accept()
2358 struct mvpp2_prs_entry pe; in mvpp2_prs_mac_del_all() local
2371 mvpp2_prs_init_from_hw(priv, &pe, tid); in mvpp2_prs_mac_del_all()
2373 pmap = mvpp2_prs_tcam_port_map_get(&pe); in mvpp2_prs_mac_del_all()
2381 mvpp2_prs_tcam_data_byte_get(&pe, index, &da[index], in mvpp2_prs_mac_del_all()
2448 struct mvpp2_prs_entry pe; in mvpp2_prs_add_flow() local
2452 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_add_flow()
2460 pe.index = tid; in mvpp2_prs_add_flow()
2465 mvpp2_prs_sram_ai_update(&pe, flow, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_add_flow()
2466 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_add_flow()
2469 mvpp2_prs_tcam_data_byte_set(&pe, i, ri_byte[i], in mvpp2_prs_add_flow()
2473 mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_add_flow()
2474 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_add_flow()
2475 mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK); in mvpp2_prs_add_flow()
2476 mvpp2_prs_hw_write(priv, &pe); in mvpp2_prs_add_flow()
2484 struct mvpp2_prs_entry pe; in mvpp2_prs_def_flow() local
2487 memset(&pe, 0, sizeof(pe)); in mvpp2_prs_def_flow()
2500 pe.index = tid; in mvpp2_prs_def_flow()
2503 mvpp2_prs_sram_ai_update(&pe, port->id, MVPP2_PRS_FLOW_ID_MASK); in mvpp2_prs_def_flow()
2504 mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1); in mvpp2_prs_def_flow()
2507 mvpp2_prs_shadow_set(port->priv, pe.index, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2509 mvpp2_prs_init_from_hw(port->priv, &pe, tid); in mvpp2_prs_def_flow()
2512 mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS); in mvpp2_prs_def_flow()
2513 mvpp2_prs_tcam_port_map_set(&pe, (1 << port->id)); in mvpp2_prs_def_flow()
2514 mvpp2_prs_hw_write(port->priv, &pe); in mvpp2_prs_def_flow()