Lines Matching full:port
61 static void mvpp2_acpi_start(struct mvpp2_port *port);
182 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, in mvpp2_txdesc_dma_addr_get() argument
185 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_dma_addr_get()
192 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, in mvpp2_txdesc_dma_addr_set() argument
201 if (port->priv->hw_version == MVPP21) { in mvpp2_txdesc_dma_addr_set()
213 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, in mvpp2_txdesc_size_get() argument
216 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_size_get()
222 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, in mvpp2_txdesc_size_set() argument
226 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_size_set()
232 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, in mvpp2_txdesc_txq_set() argument
236 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_txq_set()
242 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, in mvpp2_txdesc_cmd_set() argument
246 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_cmd_set()
252 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, in mvpp2_txdesc_offset_get() argument
255 if (port->priv->hw_version == MVPP21) in mvpp2_txdesc_offset_get()
261 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, in mvpp2_rxdesc_dma_addr_get() argument
264 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_dma_addr_get()
271 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, in mvpp2_rxdesc_cookie_get() argument
274 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_cookie_get()
281 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, in mvpp2_rxdesc_size_get() argument
284 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_size_get()
290 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, in mvpp2_rxdesc_status_get() argument
293 if (port->priv->hw_version == MVPP21) in mvpp2_rxdesc_status_get()
306 static void mvpp2_txq_inc_put(struct mvpp2_port *port, in mvpp2_txq_inc_put() argument
319 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); in mvpp2_txq_inc_put()
320 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + in mvpp2_txq_inc_put()
321 mvpp2_txdesc_offset_get(port, tx_desc); in mvpp2_txq_inc_put()
347 /* Get number of physical egress port */
348 static inline int mvpp2_egress_port(struct mvpp2_port *port) in mvpp2_egress_port() argument
350 return MVPP2_MAX_TCONT + port->id; in mvpp2_egress_port()
354 static inline int mvpp2_txq_phys(int port, int txq) in mvpp2_txq_phys() argument
356 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; in mvpp2_txq_phys()
621 struct mvpp2_port *port; in mvpp2_bm_init() local
625 port = priv->port_list[i]; in mvpp2_bm_init()
626 if (port->xdp_prog) { in mvpp2_bm_init()
695 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, in mvpp2_rxq_long_pool_set() argument
702 prxq = port->rxqs[lrxq]->id; in mvpp2_rxq_long_pool_set()
704 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_long_pool_set()
709 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_long_pool_set()
712 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_long_pool_set()
716 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, in mvpp2_rxq_short_pool_set() argument
723 prxq = port->rxqs[lrxq]->id; in mvpp2_rxq_short_pool_set()
725 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_short_pool_set()
730 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_short_pool_set()
733 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_short_pool_set()
736 static void *mvpp2_buf_alloc(struct mvpp2_port *port, in mvpp2_buf_alloc() argument
756 dma_addr = dma_map_single(port->dev->dev.parent, data, in mvpp2_buf_alloc()
759 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { in mvpp2_buf_alloc()
771 static void mvpp2_rxq_enable_fc(struct mvpp2_port *port) in mvpp2_rxq_enable_fc() argument
774 int fq = port->first_rxq; in mvpp2_rxq_enable_fc()
777 spin_lock_irqsave(&port->priv->mss_spinlock, flags); in mvpp2_rxq_enable_fc()
782 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_rxq_enable_fc()
785 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_rxq_enable_fc()
788 for (q = 0; q < port->nrxqs; q++) { in mvpp2_rxq_enable_fc()
792 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val); in mvpp2_rxq_enable_fc()
794 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq)); in mvpp2_rxq_enable_fc()
795 /* Set RXQ port ID */ in mvpp2_rxq_enable_fc()
797 val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq)); in mvpp2_rxq_enable_fc()
809 host_id = port->nqvecs; in mvpp2_rxq_enable_fc()
819 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val); in mvpp2_rxq_enable_fc()
823 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_rxq_enable_fc()
826 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_rxq_enable_fc()
828 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); in mvpp2_rxq_enable_fc()
832 static void mvpp2_rxq_disable_fc(struct mvpp2_port *port) in mvpp2_rxq_disable_fc() argument
836 int fq = port->first_rxq; in mvpp2_rxq_disable_fc()
838 spin_lock_irqsave(&port->priv->mss_spinlock, flags); in mvpp2_rxq_disable_fc()
843 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_rxq_disable_fc()
846 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_rxq_disable_fc()
849 for (q = 0; q < port->nrxqs; q++) { in mvpp2_rxq_disable_fc()
853 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val); in mvpp2_rxq_disable_fc()
855 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq)); in mvpp2_rxq_disable_fc()
862 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val); in mvpp2_rxq_disable_fc()
866 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_rxq_disable_fc()
869 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_rxq_disable_fc()
871 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); in mvpp2_rxq_disable_fc()
875 static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port, in mvpp2_bm_pool_update_fc() argument
882 spin_lock_irqsave(&port->priv->mss_spinlock, flags); in mvpp2_bm_pool_update_fc()
887 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_bm_pool_update_fc()
890 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_bm_pool_update_fc()
894 /* Set BM pool start and stop thresholds per port */ in mvpp2_bm_pool_update_fc()
895 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id)); in mvpp2_bm_pool_update_fc()
896 val |= MSS_BUF_POOL_PORT_OFFS(port->id); in mvpp2_bm_pool_update_fc()
901 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val); in mvpp2_bm_pool_update_fc()
903 /* Remove BM pool from the port */ in mvpp2_bm_pool_update_fc()
904 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id)); in mvpp2_bm_pool_update_fc()
905 val &= ~MSS_BUF_POOL_PORT_OFFS(port->id); in mvpp2_bm_pool_update_fc()
908 * flow control if pool empty (not used by any port) in mvpp2_bm_pool_update_fc()
915 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val); in mvpp2_bm_pool_update_fc()
919 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); in mvpp2_bm_pool_update_fc()
922 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); in mvpp2_bm_pool_update_fc()
924 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); in mvpp2_bm_pool_update_fc()
930 struct mvpp2_port *port; in mvpp2_bm_pool_update_priv_fc() local
934 port = priv->port_list[i]; in mvpp2_bm_pool_update_priv_fc()
935 if (port->priv->percpu_pools) { in mvpp2_bm_pool_update_priv_fc()
936 for (i = 0; i < port->nrxqs; i++) in mvpp2_bm_pool_update_priv_fc()
937 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], in mvpp2_bm_pool_update_priv_fc()
938 port->tx_fc & en); in mvpp2_bm_pool_update_priv_fc()
940 mvpp2_bm_pool_update_fc(port, port->pool_long, port->tx_fc & en); in mvpp2_bm_pool_update_priv_fc()
941 mvpp2_bm_pool_update_fc(port, port->pool_short, port->tx_fc & en); in mvpp2_bm_pool_update_priv_fc()
951 * flow control enabled, but still disabled per port. in mvpp2_enable_global_fc()
975 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, in mvpp2_bm_pool_put() argument
979 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_bm_pool_put()
982 if (test_bit(thread, &port->priv->lock_map)) in mvpp2_bm_pool_put()
983 spin_lock_irqsave(&port->bm_lock[thread], flags); in mvpp2_bm_pool_put()
985 if (port->priv->hw_version >= MVPP22) { in mvpp2_bm_pool_put()
997 mvpp2_thread_write_relaxed(port->priv, thread, in mvpp2_bm_pool_put()
1006 mvpp2_thread_write_relaxed(port->priv, thread, in mvpp2_bm_pool_put()
1008 mvpp2_thread_write_relaxed(port->priv, thread, in mvpp2_bm_pool_put()
1011 if (test_bit(thread, &port->priv->lock_map)) in mvpp2_bm_pool_put()
1012 spin_unlock_irqrestore(&port->bm_lock[thread], flags); in mvpp2_bm_pool_put()
1018 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, in mvpp2_bm_bufs_add() argument
1027 if (port->priv->percpu_pools && in mvpp2_bm_bufs_add()
1029 netdev_err(port->dev, in mvpp2_bm_bufs_add()
1039 netdev_err(port->dev, in mvpp2_bm_bufs_add()
1045 if (port->priv->percpu_pools) in mvpp2_bm_bufs_add()
1046 pp = port->priv->page_pool[bm_pool->id]; in mvpp2_bm_bufs_add()
1048 buf = mvpp2_buf_alloc(port, bm_pool, pp, &dma_addr, in mvpp2_bm_bufs_add()
1053 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, in mvpp2_bm_bufs_add()
1060 netdev_dbg(port->dev, in mvpp2_bm_bufs_add()
1064 netdev_dbg(port->dev, in mvpp2_bm_bufs_add()
1074 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) in mvpp2_bm_pool_use() argument
1076 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; in mvpp2_bm_pool_use()
1079 if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) || in mvpp2_bm_pool_use()
1080 (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) { in mvpp2_bm_pool_use()
1081 netdev_err(port->dev, "Invalid pool %d\n", pool); in mvpp2_bm_pool_use()
1096 if (port->priv->percpu_pools) { in mvpp2_bm_pool_use()
1097 if (pool < port->nrxqs) in mvpp2_bm_pool_use()
1105 mvpp2_bm_bufs_free(port->dev->dev.parent, in mvpp2_bm_pool_use()
1106 port->priv, new_pool, pkts_num); in mvpp2_bm_pool_use()
1115 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); in mvpp2_bm_pool_use()
1123 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, in mvpp2_bm_pool_use()
1130 mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type, in mvpp2_bm_pool_use_percpu() argument
1133 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; in mvpp2_bm_pool_use_percpu()
1136 if (pool > port->nrxqs * 2) { in mvpp2_bm_pool_use_percpu()
1137 netdev_err(port->dev, "Invalid pool %d\n", pool); in mvpp2_bm_pool_use_percpu()
1154 mvpp2_bm_bufs_free(port->dev->dev.parent, in mvpp2_bm_pool_use_percpu()
1155 port->priv, new_pool, pkts_num); in mvpp2_bm_pool_use_percpu()
1163 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); in mvpp2_bm_pool_use_percpu()
1171 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, in mvpp2_bm_pool_use_percpu()
1178 static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port) in mvpp2_swf_bm_pool_init_shared() argument
1183 /* If port pkt_size is higher than 1518B: in mvpp2_swf_bm_pool_init_shared()
1187 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { in mvpp2_swf_bm_pool_init_shared()
1195 if (!port->pool_long) { in mvpp2_swf_bm_pool_init_shared()
1196 port->pool_long = in mvpp2_swf_bm_pool_init_shared()
1197 mvpp2_bm_pool_use(port, long_log_pool, in mvpp2_swf_bm_pool_init_shared()
1199 if (!port->pool_long) in mvpp2_swf_bm_pool_init_shared()
1202 port->pool_long->port_map |= BIT(port->id); in mvpp2_swf_bm_pool_init_shared()
1204 for (rxq = 0; rxq < port->nrxqs; rxq++) in mvpp2_swf_bm_pool_init_shared()
1205 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); in mvpp2_swf_bm_pool_init_shared()
1208 if (!port->pool_short) { in mvpp2_swf_bm_pool_init_shared()
1209 port->pool_short = in mvpp2_swf_bm_pool_init_shared()
1210 mvpp2_bm_pool_use(port, short_log_pool, in mvpp2_swf_bm_pool_init_shared()
1212 if (!port->pool_short) in mvpp2_swf_bm_pool_init_shared()
1215 port->pool_short->port_map |= BIT(port->id); in mvpp2_swf_bm_pool_init_shared()
1217 for (rxq = 0; rxq < port->nrxqs; rxq++) in mvpp2_swf_bm_pool_init_shared()
1218 mvpp2_rxq_short_pool_set(port, rxq, in mvpp2_swf_bm_pool_init_shared()
1219 port->pool_short->id); in mvpp2_swf_bm_pool_init_shared()
1226 static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port) in mvpp2_swf_bm_pool_init_percpu() argument
1231 for (i = 0; i < port->nrxqs; i++) { in mvpp2_swf_bm_pool_init_percpu()
1232 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i, in mvpp2_swf_bm_pool_init_percpu()
1237 bm_pool->port_map |= BIT(port->id); in mvpp2_swf_bm_pool_init_percpu()
1238 mvpp2_rxq_short_pool_set(port, i, bm_pool->id); in mvpp2_swf_bm_pool_init_percpu()
1241 for (i = 0; i < port->nrxqs; i++) { in mvpp2_swf_bm_pool_init_percpu()
1242 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs, in mvpp2_swf_bm_pool_init_percpu()
1247 bm_pool->port_map |= BIT(port->id); in mvpp2_swf_bm_pool_init_percpu()
1248 mvpp2_rxq_long_pool_set(port, i, bm_pool->id); in mvpp2_swf_bm_pool_init_percpu()
1251 port->pool_long = NULL; in mvpp2_swf_bm_pool_init_percpu()
1252 port->pool_short = NULL; in mvpp2_swf_bm_pool_init_percpu()
1257 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) in mvpp2_swf_bm_pool_init() argument
1259 if (port->priv->percpu_pools) in mvpp2_swf_bm_pool_init()
1260 return mvpp2_swf_bm_pool_init_percpu(port); in mvpp2_swf_bm_pool_init()
1262 return mvpp2_swf_bm_pool_init_shared(port); in mvpp2_swf_bm_pool_init()
1265 static void mvpp2_set_hw_csum(struct mvpp2_port *port, in mvpp2_set_hw_csum() argument
1270 /* Update L4 checksum when jumbo enable/disable on port. in mvpp2_set_hw_csum()
1271 * Only port 0 supports hardware checksum offload due to in mvpp2_set_hw_csum()
1276 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { in mvpp2_set_hw_csum()
1277 port->dev->features &= ~csums; in mvpp2_set_hw_csum()
1278 port->dev->hw_features &= ~csums; in mvpp2_set_hw_csum()
1280 port->dev->features |= csums; in mvpp2_set_hw_csum()
1281 port->dev->hw_features |= csums; in mvpp2_set_hw_csum()
1287 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_bm_update_mtu() local
1291 if (port->priv->percpu_pools) in mvpp2_bm_update_mtu()
1294 /* If port MTU is higher than 1518B: in mvpp2_bm_update_mtu()
1303 if (new_long_pool != port->pool_long->id) { in mvpp2_bm_update_mtu()
1304 if (port->tx_fc) { in mvpp2_bm_update_mtu()
1306 mvpp2_bm_pool_update_fc(port, in mvpp2_bm_update_mtu()
1307 port->pool_short, in mvpp2_bm_update_mtu()
1310 mvpp2_bm_pool_update_fc(port, port->pool_long, in mvpp2_bm_update_mtu()
1314 /* Remove port from old short & long pool */ in mvpp2_bm_update_mtu()
1315 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, in mvpp2_bm_update_mtu()
1316 port->pool_long->pkt_size); in mvpp2_bm_update_mtu()
1317 port->pool_long->port_map &= ~BIT(port->id); in mvpp2_bm_update_mtu()
1318 port->pool_long = NULL; in mvpp2_bm_update_mtu()
1320 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, in mvpp2_bm_update_mtu()
1321 port->pool_short->pkt_size); in mvpp2_bm_update_mtu()
1322 port->pool_short->port_map &= ~BIT(port->id); in mvpp2_bm_update_mtu()
1323 port->pool_short = NULL; in mvpp2_bm_update_mtu()
1325 port->pkt_size = pkt_size; in mvpp2_bm_update_mtu()
1327 /* Add port to new short & long pool */ in mvpp2_bm_update_mtu()
1328 mvpp2_swf_bm_pool_init(port); in mvpp2_bm_update_mtu()
1330 mvpp2_set_hw_csum(port, new_long_pool); in mvpp2_bm_update_mtu()
1332 if (port->tx_fc) { in mvpp2_bm_update_mtu()
1334 mvpp2_bm_pool_update_fc(port, port->pool_long, in mvpp2_bm_update_mtu()
1337 mvpp2_bm_pool_update_fc(port, port->pool_short, in mvpp2_bm_update_mtu()
1341 /* Update L4 checksum when jumbo enable/disable on port */ in mvpp2_bm_update_mtu()
1342 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { in mvpp2_bm_update_mtu()
1360 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) in mvpp2_interrupts_enable() argument
1364 for (i = 0; i < port->nqvecs; i++) in mvpp2_interrupts_enable()
1365 sw_thread_mask |= port->qvecs[i].sw_thread_mask; in mvpp2_interrupts_enable()
1367 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_interrupts_enable()
1371 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) in mvpp2_interrupts_disable() argument
1375 for (i = 0; i < port->nqvecs; i++) in mvpp2_interrupts_disable()
1376 sw_thread_mask |= port->qvecs[i].sw_thread_mask; in mvpp2_interrupts_disable()
1378 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_interrupts_disable()
1384 struct mvpp2_port *port = qvec->port; in mvpp2_qvec_interrupt_enable() local
1386 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_qvec_interrupt_enable()
1392 struct mvpp2_port *port = qvec->port; in mvpp2_qvec_interrupt_disable() local
1394 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), in mvpp2_qvec_interrupt_disable()
1404 struct mvpp2_port *port = arg; in mvpp2_interrupts_mask() local
1409 if (cpu > port->priv->nthreads) in mvpp2_interrupts_mask()
1412 thread = mvpp2_cpu_to_thread(port->priv, cpu); in mvpp2_interrupts_mask()
1414 mvpp2_thread_write(port->priv, thread, in mvpp2_interrupts_mask()
1415 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); in mvpp2_interrupts_mask()
1416 mvpp2_thread_write(port->priv, thread, in mvpp2_interrupts_mask()
1417 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0); in mvpp2_interrupts_mask()
1426 struct mvpp2_port *port = arg; in mvpp2_interrupts_unmask() local
1431 if (cpu >= port->priv->nthreads) in mvpp2_interrupts_unmask()
1434 thread = mvpp2_cpu_to_thread(port->priv, cpu); in mvpp2_interrupts_unmask()
1437 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); in mvpp2_interrupts_unmask()
1438 if (port->has_tx_irqs) in mvpp2_interrupts_unmask()
1441 mvpp2_thread_write(port->priv, thread, in mvpp2_interrupts_unmask()
1442 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); in mvpp2_interrupts_unmask()
1443 mvpp2_thread_write(port->priv, thread, in mvpp2_interrupts_unmask()
1444 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), in mvpp2_interrupts_unmask()
1449 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) in mvpp2_shared_interrupt_mask_unmask() argument
1454 if (port->priv->hw_version == MVPP21) in mvpp2_shared_interrupt_mask_unmask()
1462 for (i = 0; i < port->nqvecs; i++) { in mvpp2_shared_interrupt_mask_unmask()
1463 struct mvpp2_queue_vector *v = port->qvecs + i; in mvpp2_shared_interrupt_mask_unmask()
1468 mvpp2_thread_write(port->priv, v->sw_thread_id, in mvpp2_shared_interrupt_mask_unmask()
1469 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); in mvpp2_shared_interrupt_mask_unmask()
1470 mvpp2_thread_write(port->priv, v->sw_thread_id, in mvpp2_shared_interrupt_mask_unmask()
1471 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), in mvpp2_shared_interrupt_mask_unmask()
1476 /* Only GOP port 0 has an XLG MAC */
1477 static bool mvpp2_port_supports_xlg(struct mvpp2_port *port) in mvpp2_port_supports_xlg() argument
1479 return port->gop_id == 0; in mvpp2_port_supports_xlg()
1482 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port) in mvpp2_port_supports_rgmii() argument
1484 return !(port->priv->hw_version >= MVPP22 && port->gop_id == 0); in mvpp2_port_supports_rgmii()
1487 /* Port configuration routines */
1506 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) in mvpp22_gop_init_rgmii() argument
1508 struct mvpp2 *priv = port->priv; in mvpp22_gop_init_rgmii()
1516 if (port->gop_id == 2) in mvpp22_gop_init_rgmii()
1518 else if (port->gop_id == 3) in mvpp22_gop_init_rgmii()
1523 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) in mvpp22_gop_init_sgmii() argument
1525 struct mvpp2 *priv = port->priv; in mvpp22_gop_init_sgmii()
1533 if (port->gop_id > 1) { in mvpp22_gop_init_sgmii()
1535 if (port->gop_id == 2) in mvpp22_gop_init_sgmii()
1537 else if (port->gop_id == 3) in mvpp22_gop_init_sgmii()
1543 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) in mvpp22_gop_init_10gkr() argument
1545 struct mvpp2 *priv = port->priv; in mvpp22_gop_init_10gkr()
1546 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); in mvpp22_gop_init_10gkr()
1547 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); in mvpp22_gop_init_10gkr()
1566 static void mvpp22_gop_fca_enable_periodic(struct mvpp2_port *port, bool en) in mvpp22_gop_fca_enable_periodic() argument
1568 struct mvpp2 *priv = port->priv; in mvpp22_gop_fca_enable_periodic()
1569 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); in mvpp22_gop_fca_enable_periodic()
1579 static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer) in mvpp22_gop_fca_set_timer() argument
1581 struct mvpp2 *priv = port->priv; in mvpp22_gop_fca_set_timer()
1582 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); in mvpp22_gop_fca_set_timer()
1593 * partner won't send traffic if port is in XOFF mode.
1595 static void mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port *port) in mvpp22_gop_fca_set_periodic_timer() argument
1599 timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER)) in mvpp22_gop_fca_set_periodic_timer()
1602 mvpp22_gop_fca_enable_periodic(port, false); in mvpp22_gop_fca_set_periodic_timer()
1604 mvpp22_gop_fca_set_timer(port, timer); in mvpp22_gop_fca_set_periodic_timer()
1606 mvpp22_gop_fca_enable_periodic(port, true); in mvpp22_gop_fca_set_periodic_timer()
1609 static int mvpp22_gop_init(struct mvpp2_port *port, phy_interface_t interface) in mvpp22_gop_init() argument
1611 struct mvpp2 *priv = port->priv; in mvpp22_gop_init()
1622 if (!mvpp2_port_supports_rgmii(port)) in mvpp22_gop_init()
1624 mvpp22_gop_init_rgmii(port); in mvpp22_gop_init()
1629 mvpp22_gop_init_sgmii(port); in mvpp22_gop_init()
1633 if (!mvpp2_port_supports_xlg(port)) in mvpp22_gop_init()
1635 mvpp22_gop_init_10gkr(port); in mvpp22_gop_init()
1642 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | in mvpp22_gop_init()
1643 GENCONF_PORT_CTRL1_EN(port->gop_id); in mvpp22_gop_init()
1654 mvpp22_gop_fca_set_periodic_timer(port); in mvpp22_gop_init()
1660 netdev_err(port->dev, "Invalid port configuration\n"); in mvpp22_gop_init()
1664 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) in mvpp22_gop_unmask_irq() argument
1668 if (phy_interface_mode_is_rgmii(port->phy_interface) || in mvpp22_gop_unmask_irq()
1669 phy_interface_mode_is_8023z(port->phy_interface) || in mvpp22_gop_unmask_irq()
1670 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { in mvpp22_gop_unmask_irq()
1671 /* Enable the GMAC link status irq for this port */ in mvpp22_gop_unmask_irq()
1672 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_unmask_irq()
1674 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_unmask_irq()
1677 if (mvpp2_port_supports_xlg(port)) { in mvpp22_gop_unmask_irq()
1678 /* Enable the XLG/GIG irqs for this port */ in mvpp22_gop_unmask_irq()
1679 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_unmask_irq()
1680 if (mvpp2_is_xlg(port->phy_interface)) in mvpp22_gop_unmask_irq()
1684 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_unmask_irq()
1688 static void mvpp22_gop_mask_irq(struct mvpp2_port *port) in mvpp22_gop_mask_irq() argument
1692 if (mvpp2_port_supports_xlg(port)) { in mvpp22_gop_mask_irq()
1693 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_mask_irq()
1696 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); in mvpp22_gop_mask_irq()
1699 if (phy_interface_mode_is_rgmii(port->phy_interface) || in mvpp22_gop_mask_irq()
1700 phy_interface_mode_is_8023z(port->phy_interface) || in mvpp22_gop_mask_irq()
1701 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { in mvpp22_gop_mask_irq()
1702 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_mask_irq()
1704 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); in mvpp22_gop_mask_irq()
1708 static void mvpp22_gop_setup_irq(struct mvpp2_port *port) in mvpp22_gop_setup_irq() argument
1712 mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK, in mvpp22_gop_setup_irq()
1716 if (port->phylink || in mvpp22_gop_setup_irq()
1717 phy_interface_mode_is_rgmii(port->phy_interface) || in mvpp22_gop_setup_irq()
1718 phy_interface_mode_is_8023z(port->phy_interface) || in mvpp22_gop_setup_irq()
1719 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { in mvpp22_gop_setup_irq()
1720 val = readl(port->base + MVPP22_GMAC_INT_MASK); in mvpp22_gop_setup_irq()
1722 writel(val, port->base + MVPP22_GMAC_INT_MASK); in mvpp22_gop_setup_irq()
1725 if (mvpp2_port_supports_xlg(port)) { in mvpp22_gop_setup_irq()
1726 val = readl(port->base + MVPP22_XLG_INT_MASK); in mvpp22_gop_setup_irq()
1728 writel(val, port->base + MVPP22_XLG_INT_MASK); in mvpp22_gop_setup_irq()
1730 mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK, in mvpp22_gop_setup_irq()
1735 mvpp22_gop_unmask_irq(port); in mvpp22_gop_setup_irq()
1748 static int mvpp22_comphy_init(struct mvpp2_port *port, in mvpp22_comphy_init() argument
1753 if (!port->comphy) in mvpp22_comphy_init()
1756 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, interface); in mvpp22_comphy_init()
1760 return phy_power_on(port->comphy); in mvpp22_comphy_init()
1763 static void mvpp2_port_enable(struct mvpp2_port *port) in mvpp2_port_enable() argument
1767 if (mvpp2_port_supports_xlg(port) && in mvpp2_port_enable()
1768 mvpp2_is_xlg(port->phy_interface)) { in mvpp2_port_enable()
1769 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()
1772 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()
1774 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
1777 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_enable()
1781 static void mvpp2_port_disable(struct mvpp2_port *port) in mvpp2_port_disable() argument
1785 if (mvpp2_port_supports_xlg(port) && in mvpp2_port_disable()
1786 mvpp2_is_xlg(port->phy_interface)) { in mvpp2_port_disable()
1787 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()
1789 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()
1792 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
1794 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_port_disable()
1798 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) in mvpp2_port_periodic_xon_disable() argument
1802 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & in mvpp2_port_periodic_xon_disable()
1804 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_periodic_xon_disable()
1807 /* Configure loopback port */
1808 static void mvpp2_port_loopback_set(struct mvpp2_port *port, in mvpp2_port_loopback_set() argument
1813 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
1826 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp2_port_loopback_set()
1845 static u64 mvpp2_read_count(struct mvpp2_port *port, in mvpp2_read_count() argument
1850 val = readl(port->stats_base + counter->offset); in mvpp2_read_count()
1852 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; in mvpp2_read_count()
1950 struct mvpp2_port *port = netdev_priv(netdev); in mvpp2_ethtool_get_strings() local
1968 for (q = 0; q < port->ntxqs; q++) { in mvpp2_ethtool_get_strings()
1976 for (q = 0; q < port->nrxqs; q++) { in mvpp2_ethtool_get_strings()
1993 mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats) in mvpp2_get_xdp_stats() argument
2009 cpu_stats = per_cpu_ptr(port->stats, cpu); in mvpp2_get_xdp_stats()
2031 static void mvpp2_read_stats(struct mvpp2_port *port) in mvpp2_read_stats() argument
2038 pstats = port->ethtool_stats; in mvpp2_read_stats()
2041 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]); in mvpp2_read_stats()
2044 *pstats++ += mvpp2_read(port->priv, in mvpp2_read_stats()
2046 4 * port->id); in mvpp2_read_stats()
2048 for (q = 0; q < port->ntxqs; q++) in mvpp2_read_stats()
2050 *pstats++ += mvpp2_read_index(port->priv, in mvpp2_read_stats()
2051 MVPP22_CTRS_TX_CTR(port->id, q), in mvpp2_read_stats()
2055 * driver's. We need to add the port->first_rxq offset. in mvpp2_read_stats()
2057 for (q = 0; q < port->nrxqs; q++) in mvpp2_read_stats()
2059 *pstats++ += mvpp2_read_index(port->priv, in mvpp2_read_stats()
2060 port->first_rxq + q, in mvpp2_read_stats()
2064 mvpp2_get_xdp_stats(port, &xdp_stats); in mvpp2_read_stats()
2098 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, in mvpp2_gather_hw_statistics() local
2101 mutex_lock(&port->gather_stats_lock); in mvpp2_gather_hw_statistics()
2103 mvpp2_read_stats(port); in mvpp2_gather_hw_statistics()
2108 cancel_delayed_work(&port->stats_work); in mvpp2_gather_hw_statistics()
2109 queue_delayed_work(port->priv->stats_queue, &port->stats_work, in mvpp2_gather_hw_statistics()
2112 mutex_unlock(&port->gather_stats_lock); in mvpp2_gather_hw_statistics()
2118 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_stats() local
2120 /* Update statistics for the given port, then take the lock to avoid in mvpp2_ethtool_get_stats()
2123 mvpp2_gather_hw_statistics(&port->stats_work.work); in mvpp2_ethtool_get_stats()
2125 mutex_lock(&port->gather_stats_lock); in mvpp2_ethtool_get_stats()
2126 memcpy(data, port->ethtool_stats, in mvpp2_ethtool_get_stats()
2127 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs)); in mvpp2_ethtool_get_stats()
2128 mutex_unlock(&port->gather_stats_lock); in mvpp2_ethtool_get_stats()
2133 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_sset_count() local
2136 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs); in mvpp2_ethtool_get_sset_count()
2141 static void mvpp2_mac_reset_assert(struct mvpp2_port *port) in mvpp2_mac_reset_assert() argument
2145 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) | in mvpp2_mac_reset_assert()
2147 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_mac_reset_assert()
2149 if (port->priv->hw_version >= MVPP22 && port->gop_id == 0) { in mvpp2_mac_reset_assert()
2150 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & in mvpp2_mac_reset_assert()
2152 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_mac_reset_assert()
2156 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port) in mvpp22_pcs_reset_assert() argument
2158 struct mvpp2 *priv = port->priv; in mvpp22_pcs_reset_assert()
2162 if (port->priv->hw_version == MVPP21 || port->gop_id != 0) in mvpp22_pcs_reset_assert()
2165 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); in mvpp22_pcs_reset_assert()
2166 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); in mvpp22_pcs_reset_assert()
2177 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port, in mvpp22_pcs_reset_deassert() argument
2180 struct mvpp2 *priv = port->priv; in mvpp22_pcs_reset_deassert()
2184 if (port->priv->hw_version == MVPP21 || port->gop_id != 0) in mvpp22_pcs_reset_deassert()
2187 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); in mvpp22_pcs_reset_deassert()
2188 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); in mvpp22_pcs_reset_deassert()
2209 /* Change maximum receive size of the port */
2210 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) in mvpp2_gmac_max_rx_size_set() argument
2214 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
2216 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << in mvpp2_gmac_max_rx_size_set()
2218 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_max_rx_size_set()
2221 /* Change maximum receive size of the port */
2222 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) in mvpp2_xlg_max_rx_size_set() argument
2226 val = readl(port->base + MVPP22_XLG_CTRL1_REG); in mvpp2_xlg_max_rx_size_set()
2228 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << in mvpp2_xlg_max_rx_size_set()
2230 writel(val, port->base + MVPP22_XLG_CTRL1_REG); in mvpp2_xlg_max_rx_size_set()
2233 /* Set defaults to the MVPP2 port */
2234 static void mvpp2_defaults_set(struct mvpp2_port *port) in mvpp2_defaults_set() argument
2238 if (port->priv->hw_version == MVPP21) { in mvpp2_defaults_set()
2240 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
2244 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); in mvpp2_defaults_set()
2248 tx_port_num = mvpp2_egress_port(port); in mvpp2_defaults_set()
2249 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, in mvpp2_defaults_set()
2251 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); in mvpp2_defaults_set()
2254 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); in mvpp2_defaults_set()
2258 mvpp2_write(port->priv, in mvpp2_defaults_set()
2264 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, in mvpp2_defaults_set()
2265 port->priv->tclk / USEC_PER_SEC); in mvpp2_defaults_set()
2266 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); in mvpp2_defaults_set()
2270 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); in mvpp2_defaults_set()
2272 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_defaults_set()
2275 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), in mvpp2_defaults_set()
2280 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { in mvpp2_defaults_set()
2281 queue = port->rxqs[lrxq]->id; in mvpp2_defaults_set()
2282 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_defaults_set()
2285 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_defaults_set()
2289 mvpp2_interrupts_disable(port); in mvpp2_defaults_set()
2293 static void mvpp2_ingress_enable(struct mvpp2_port *port) in mvpp2_ingress_enable() argument
2298 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { in mvpp2_ingress_enable()
2299 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_enable()
2300 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_enable()
2302 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_enable()
2306 static void mvpp2_ingress_disable(struct mvpp2_port *port) in mvpp2_ingress_disable() argument
2311 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { in mvpp2_ingress_disable()
2312 queue = port->rxqs[lrxq]->id; in mvpp2_ingress_disable()
2313 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); in mvpp2_ingress_disable()
2315 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); in mvpp2_ingress_disable()
2322 static void mvpp2_egress_enable(struct mvpp2_port *port) in mvpp2_egress_enable() argument
2326 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_enable()
2330 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_egress_enable()
2331 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_egress_enable()
2337 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_enable()
2338 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); in mvpp2_egress_enable()
2344 static void mvpp2_egress_disable(struct mvpp2_port *port) in mvpp2_egress_disable() argument
2348 int tx_port_num = mvpp2_egress_port(port); in mvpp2_egress_disable()
2351 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_egress_disable()
2352 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & in mvpp2_egress_disable()
2355 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, in mvpp2_egress_disable()
2362 netdev_warn(port->dev, in mvpp2_egress_disable()
2370 /* Check port TX Command register that all in mvpp2_egress_disable()
2373 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); in mvpp2_egress_disable()
2381 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) in mvpp2_rxq_received() argument
2383 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); in mvpp2_rxq_received()
2392 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, in mvpp2_rxq_status_update() argument
2400 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); in mvpp2_rxq_status_update()
2415 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, in mvpp2_rxq_offset_set() argument
2423 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); in mvpp2_rxq_offset_set()
2430 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); in mvpp2_rxq_offset_set()
2450 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) in mvpp2_aggr_txq_pend_desc_add() argument
2453 mvpp2_thread_write(port->priv, in mvpp2_aggr_txq_pend_desc_add()
2454 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), in mvpp2_aggr_txq_pend_desc_add()
2464 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port, in mvpp2_aggr_desc_num_check() argument
2470 mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_aggr_desc_num_check()
2471 u32 val = mvpp2_read_relaxed(port->priv, in mvpp2_aggr_desc_num_check()
2488 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port, in mvpp2_txq_alloc_reserved_desc() argument
2491 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_txq_alloc_reserved_desc()
2492 struct mvpp2 *priv = port->priv; in mvpp2_txq_alloc_reserved_desc()
2506 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port, in mvpp2_txq_reserved_desc_num_proc() argument
2523 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_txq_reserved_desc_num_proc()
2538 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req); in mvpp2_txq_reserved_desc_num_proc()
2598 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, in mvpp2_txq_sent_desc_proc() argument
2604 val = mvpp2_thread_read_relaxed(port->priv, in mvpp2_txq_sent_desc_proc()
2605 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), in mvpp2_txq_sent_desc_proc()
2617 struct mvpp2_port *port = arg; in mvpp2_txq_sent_counter_clear() local
2621 if (smp_processor_id() >= port->priv->nthreads) in mvpp2_txq_sent_counter_clear()
2624 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_txq_sent_counter_clear()
2625 int id = port->txqs[queue]->id; in mvpp2_txq_sent_counter_clear()
2627 mvpp2_thread_read(port->priv, in mvpp2_txq_sent_counter_clear()
2628 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), in mvpp2_txq_sent_counter_clear()
2634 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) in mvpp2_txp_max_tx_size_set() argument
2639 mtu = port->pkt_size * 8; in mvpp2_txp_max_tx_size_set()
2647 tx_port_num = mvpp2_egress_port(port); in mvpp2_txp_max_tx_size_set()
2648 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txp_max_tx_size_set()
2651 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); in mvpp2_txp_max_tx_size_set()
2654 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); in mvpp2_txp_max_tx_size_set()
2657 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); in mvpp2_txp_max_tx_size_set()
2663 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); in mvpp2_txp_max_tx_size_set()
2666 for (txq = 0; txq < port->ntxqs; txq++) { in mvpp2_txp_max_tx_size_set()
2667 val = mvpp2_read(port->priv, in mvpp2_txp_max_tx_size_set()
2675 mvpp2_write(port->priv, in mvpp2_txp_max_tx_size_set()
2683 static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port, in mvpp2_set_rxq_free_tresh() argument
2688 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_set_rxq_free_tresh()
2690 val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG); in mvpp2_set_rxq_free_tresh()
2693 mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val); in mvpp2_set_rxq_free_tresh()
2699 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, in mvpp2_rx_pkts_coal_set() argument
2702 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_rx_pkts_coal_set()
2707 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rx_pkts_coal_set()
2708 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG, in mvpp2_rx_pkts_coal_set()
2715 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, in mvpp2_tx_pkts_coal_set() argument
2727 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_tx_pkts_coal_set()
2728 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val); in mvpp2_tx_pkts_coal_set()
2751 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, in mvpp2_rx_time_coal_set() argument
2754 unsigned long freq = port->priv->tclk; in mvpp2_rx_time_coal_set()
2765 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); in mvpp2_rx_time_coal_set()
2768 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) in mvpp2_tx_time_coal_set() argument
2770 unsigned long freq = port->priv->tclk; in mvpp2_tx_time_coal_set()
2771 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); in mvpp2_tx_time_coal_set()
2774 port->tx_time_coal = in mvpp2_tx_time_coal_set()
2778 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); in mvpp2_tx_time_coal_set()
2781 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); in mvpp2_tx_time_coal_set()
2785 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, in mvpp2_txq_bufs_free() argument
2802 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, in mvpp2_txq_bufs_free()
2817 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, in mvpp2_get_rx_queue() argument
2822 return port->rxqs[queue]; in mvpp2_get_rx_queue()
2825 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, in mvpp2_get_tx_queue() argument
2830 return port->txqs[queue]; in mvpp2_get_tx_queue()
2834 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, in mvpp2_txq_done() argument
2837 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); in mvpp2_txq_done()
2840 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id())) in mvpp2_txq_done()
2841 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); in mvpp2_txq_done()
2843 tx_done = mvpp2_txq_sent_desc_proc(port, txq); in mvpp2_txq_done()
2846 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); in mvpp2_txq_done()
2855 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, in mvpp2_tx_done() argument
2863 txq = mvpp2_get_tx_queue(port, cause); in mvpp2_tx_done()
2870 mvpp2_txq_done(port, txq, txq_pcpu); in mvpp2_tx_done()
2918 static int mvpp2_rxq_init(struct mvpp2_port *port, in mvpp2_rxq_init() argument
2921 struct mvpp2 *priv = port->priv; in mvpp2_rxq_init()
2926 rxq->size = port->rx_ring_size; in mvpp2_rxq_init()
2929 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, in mvpp2_rxq_init()
2938 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_init()
2941 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_rxq_init()
2942 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_init()
2943 if (port->priv->hw_version == MVPP21) in mvpp2_rxq_init()
2947 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); in mvpp2_rxq_init()
2948 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); in mvpp2_rxq_init()
2949 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0); in mvpp2_rxq_init()
2953 mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM); in mvpp2_rxq_init()
2956 mvpp2_rx_pkts_coal_set(port, rxq); in mvpp2_rxq_init()
2957 mvpp2_rx_time_coal_set(port, rxq); in mvpp2_rxq_init()
2960 mvpp2_set_rxq_free_tresh(port, rxq); in mvpp2_rxq_init()
2963 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); in mvpp2_rxq_init()
2966 err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->logic_rxq, 0); in mvpp2_rxq_init()
2970 err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->logic_rxq, 0); in mvpp2_rxq_init()
2984 port->nrxqs]); in mvpp2_rxq_init()
2998 dma_free_coherent(port->dev->dev.parent, in mvpp2_rxq_init()
3005 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, in mvpp2_rxq_drop_pkts() argument
3010 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_rxq_drop_pkts()
3016 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); in mvpp2_rxq_drop_pkts()
3022 mvpp2_bm_pool_put(port, pool, in mvpp2_rxq_drop_pkts()
3023 mvpp2_rxdesc_dma_addr_get(port, rx_desc), in mvpp2_rxq_drop_pkts()
3024 mvpp2_rxdesc_cookie_get(port, rx_desc)); in mvpp2_rxq_drop_pkts()
3026 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); in mvpp2_rxq_drop_pkts()
3030 static void mvpp2_rxq_deinit(struct mvpp2_port *port, in mvpp2_rxq_deinit() argument
3041 mvpp2_rxq_drop_pkts(port, rxq); in mvpp2_rxq_deinit()
3044 dma_free_coherent(port->dev->dev.parent, in mvpp2_rxq_deinit()
3057 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); in mvpp2_rxq_deinit()
3058 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_rxq_deinit()
3059 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); in mvpp2_rxq_deinit()
3060 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0); in mvpp2_rxq_deinit()
3061 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0); in mvpp2_rxq_deinit()
3066 static int mvpp2_txq_init(struct mvpp2_port *port, in mvpp2_txq_init() argument
3074 txq->size = port->tx_ring_size; in mvpp2_txq_init()
3077 txq->descs = dma_alloc_coherent(port->dev->dev.parent, in mvpp2_txq_init()
3086 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_txq_init()
3087 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_init()
3088 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, in mvpp2_txq_init()
3090 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, in mvpp2_txq_init()
3092 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0); in mvpp2_txq_init()
3093 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG, in mvpp2_txq_init()
3095 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG); in mvpp2_txq_init()
3097 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val); in mvpp2_txq_init()
3101 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT in mvpp2_txq_init()
3105 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + in mvpp2_txq_init()
3108 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, in mvpp2_txq_init()
3114 tx_port_num = mvpp2_egress_port(port); in mvpp2_txq_init()
3115 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); in mvpp2_txq_init()
3117 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); in mvpp2_txq_init()
3121 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); in mvpp2_txq_init()
3124 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), in mvpp2_txq_init()
3127 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_txq_init()
3146 dma_alloc_coherent(port->dev->dev.parent, in mvpp2_txq_init()
3158 static void mvpp2_txq_deinit(struct mvpp2_port *port, in mvpp2_txq_deinit() argument
3164 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_txq_deinit()
3169 dma_free_coherent(port->dev->dev.parent, in mvpp2_txq_deinit()
3178 dma_free_coherent(port->dev->dev.parent, in mvpp2_txq_deinit()
3188 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0); in mvpp2_txq_deinit()
3191 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_txq_deinit()
3192 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_deinit()
3193 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0); in mvpp2_txq_deinit()
3194 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0); in mvpp2_txq_deinit()
3199 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) in mvpp2_txq_clean() argument
3203 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); in mvpp2_txq_clean()
3206 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); in mvpp2_txq_clean()
3207 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG); in mvpp2_txq_clean()
3209 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
3217 netdev_warn(port->dev, in mvpp2_txq_clean()
3218 "port %d: cleaning queue %d timed out\n", in mvpp2_txq_clean()
3219 port->id, txq->log_id); in mvpp2_txq_clean()
3225 pending = mvpp2_thread_read(port->priv, thread, in mvpp2_txq_clean()
3231 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); in mvpp2_txq_clean()
3234 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_txq_clean()
3238 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); in mvpp2_txq_clean()
3248 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) in mvpp2_cleanup_txqs() argument
3254 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); in mvpp2_cleanup_txqs()
3257 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
3258 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
3260 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_cleanup_txqs()
3261 txq = port->txqs[queue]; in mvpp2_cleanup_txqs()
3262 mvpp2_txq_clean(port, txq); in mvpp2_cleanup_txqs()
3263 mvpp2_txq_deinit(port, txq); in mvpp2_cleanup_txqs()
3266 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); in mvpp2_cleanup_txqs()
3268 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); in mvpp2_cleanup_txqs()
3269 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); in mvpp2_cleanup_txqs()
3273 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) in mvpp2_cleanup_rxqs() argument
3277 for (queue = 0; queue < port->nrxqs; queue++) in mvpp2_cleanup_rxqs()
3278 mvpp2_rxq_deinit(port, port->rxqs[queue]); in mvpp2_cleanup_rxqs()
3280 if (port->tx_fc) in mvpp2_cleanup_rxqs()
3281 mvpp2_rxq_disable_fc(port); in mvpp2_cleanup_rxqs()
3284 /* Init all Rx queues for port */
3285 static int mvpp2_setup_rxqs(struct mvpp2_port *port) in mvpp2_setup_rxqs() argument
3289 for (queue = 0; queue < port->nrxqs; queue++) { in mvpp2_setup_rxqs()
3290 err = mvpp2_rxq_init(port, port->rxqs[queue]); in mvpp2_setup_rxqs()
3295 if (port->tx_fc) in mvpp2_setup_rxqs()
3296 mvpp2_rxq_enable_fc(port); in mvpp2_setup_rxqs()
3301 mvpp2_cleanup_rxqs(port); in mvpp2_setup_rxqs()
3305 /* Init all tx queues for port */
3306 static int mvpp2_setup_txqs(struct mvpp2_port *port) in mvpp2_setup_txqs() argument
3311 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_setup_txqs()
3312 txq = port->txqs[queue]; in mvpp2_setup_txqs()
3313 err = mvpp2_txq_init(port, txq); in mvpp2_setup_txqs()
3319 netif_set_xps_queue(port->dev, cpumask_of(queue), queue); in mvpp2_setup_txqs()
3322 if (port->has_tx_irqs) { in mvpp2_setup_txqs()
3323 mvpp2_tx_time_coal_set(port); in mvpp2_setup_txqs()
3324 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_setup_txqs()
3325 txq = port->txqs[queue]; in mvpp2_setup_txqs()
3326 mvpp2_tx_pkts_coal_set(port, txq); in mvpp2_setup_txqs()
3330 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); in mvpp2_setup_txqs()
3334 mvpp2_cleanup_txqs(port); in mvpp2_setup_txqs()
3338 /* The callback for per-port interrupt */
3350 static void mvpp2_isr_handle_ptp_queue(struct mvpp2_port *port, int nq) in mvpp2_isr_handle_ptp_queue() argument
3359 ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); in mvpp2_isr_handle_ptp_queue()
3363 queue = &port->tx_hwtstamp_queue[nq]; in mvpp2_isr_handle_ptp_queue()
3380 mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps); in mvpp2_isr_handle_ptp_queue()
3387 static void mvpp2_isr_handle_ptp(struct mvpp2_port *port) in mvpp2_isr_handle_ptp() argument
3392 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); in mvpp2_isr_handle_ptp()
3395 mvpp2_isr_handle_ptp_queue(port, 0); in mvpp2_isr_handle_ptp()
3397 mvpp2_isr_handle_ptp_queue(port, 1); in mvpp2_isr_handle_ptp()
3400 static void mvpp2_isr_handle_link(struct mvpp2_port *port, bool link) in mvpp2_isr_handle_link() argument
3402 struct net_device *dev = port->dev; in mvpp2_isr_handle_link()
3404 if (port->phylink) { in mvpp2_isr_handle_link()
3405 phylink_mac_change(port->phylink, link); in mvpp2_isr_handle_link()
3413 mvpp2_interrupts_enable(port); in mvpp2_isr_handle_link()
3415 mvpp2_egress_enable(port); in mvpp2_isr_handle_link()
3416 mvpp2_ingress_enable(port); in mvpp2_isr_handle_link()
3422 mvpp2_ingress_disable(port); in mvpp2_isr_handle_link()
3423 mvpp2_egress_disable(port); in mvpp2_isr_handle_link()
3425 mvpp2_interrupts_disable(port); in mvpp2_isr_handle_link()
3429 static void mvpp2_isr_handle_xlg(struct mvpp2_port *port) in mvpp2_isr_handle_xlg() argument
3434 val = readl(port->base + MVPP22_XLG_INT_STAT); in mvpp2_isr_handle_xlg()
3436 val = readl(port->base + MVPP22_XLG_STATUS); in mvpp2_isr_handle_xlg()
3438 mvpp2_isr_handle_link(port, link); in mvpp2_isr_handle_xlg()
3442 static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port) in mvpp2_isr_handle_gmac_internal() argument
3447 if (phy_interface_mode_is_rgmii(port->phy_interface) || in mvpp2_isr_handle_gmac_internal()
3448 phy_interface_mode_is_8023z(port->phy_interface) || in mvpp2_isr_handle_gmac_internal()
3449 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { in mvpp2_isr_handle_gmac_internal()
3450 val = readl(port->base + MVPP22_GMAC_INT_STAT); in mvpp2_isr_handle_gmac_internal()
3452 val = readl(port->base + MVPP2_GMAC_STATUS0); in mvpp2_isr_handle_gmac_internal()
3454 mvpp2_isr_handle_link(port, link); in mvpp2_isr_handle_gmac_internal()
3459 /* Per-port interrupt for link status changes */
3462 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; in mvpp2_port_isr() local
3465 mvpp22_gop_mask_irq(port); in mvpp2_port_isr()
3467 if (mvpp2_port_supports_xlg(port) && in mvpp2_port_isr()
3468 mvpp2_is_xlg(port->phy_interface)) { in mvpp2_port_isr()
3470 val = readl(port->base + MVPP22_XLG_EXT_INT_STAT); in mvpp2_port_isr()
3472 mvpp2_isr_handle_xlg(port); in mvpp2_port_isr()
3474 mvpp2_isr_handle_ptp(port); in mvpp2_port_isr()
3479 val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT); in mvpp2_port_isr()
3481 mvpp2_isr_handle_gmac_internal(port); in mvpp2_port_isr()
3483 mvpp2_isr_handle_ptp(port); in mvpp2_port_isr()
3486 mvpp22_gop_unmask_irq(port); in mvpp2_port_isr()
3493 struct mvpp2_port *port; in mvpp2_hr_timer_cb() local
3504 port = netdev_priv(dev); in mvpp2_hr_timer_cb()
3507 cause = (1 << port->ntxqs) - 1; in mvpp2_hr_timer_cb()
3508 tx_todo = mvpp2_tx_done(port, cause, in mvpp2_hr_timer_cb()
3509 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); in mvpp2_hr_timer_cb()
3525 static void mvpp2_rx_error(struct mvpp2_port *port, in mvpp2_rx_error() argument
3528 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); in mvpp2_rx_error()
3529 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); in mvpp2_rx_error()
3544 netdev_err(port->dev, in mvpp2_rx_error()
3550 static int mvpp2_rx_csum(struct mvpp2_port *port, u32 status) in mvpp2_rx_csum() argument
3564 static int mvpp2_rx_refill(struct mvpp2_port *port, in mvpp2_rx_refill() argument
3572 buf = mvpp2_buf_alloc(port, bm_pool, page_pool, in mvpp2_rx_refill()
3577 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); in mvpp2_rx_refill()
3583 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) in mvpp2_skb_tx_csum() argument
3614 static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte) in mvpp2_xdp_finish_tx() argument
3616 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_xdp_finish_tx()
3622 txq = port->txqs[txq_id]; in mvpp2_xdp_finish_tx()
3624 nq = netdev_get_tx_queue(port->dev, txq_id); in mvpp2_xdp_finish_tx()
3625 aggr_txq = &port->priv->aggr_txqs[thread]; in mvpp2_xdp_finish_tx()
3633 mvpp2_aggr_txq_pend_desc_add(port, nxmit); in mvpp2_xdp_finish_tx()
3639 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) in mvpp2_xdp_finish_tx()
3640 mvpp2_txq_done(port, txq, txq_pcpu); in mvpp2_xdp_finish_tx()
3644 mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id, in mvpp2_xdp_submit_frame() argument
3647 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_xdp_submit_frame()
3658 txq = port->txqs[txq_id]; in mvpp2_xdp_submit_frame()
3660 aggr_txq = &port->priv->aggr_txqs[thread]; in mvpp2_xdp_submit_frame()
3663 if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) || in mvpp2_xdp_submit_frame()
3664 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) { in mvpp2_xdp_submit_frame()
3671 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_xdp_submit_frame()
3672 mvpp2_txdesc_size_set(port, tx_desc, xdpf->len); in mvpp2_xdp_submit_frame()
3676 dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data, in mvpp2_xdp_submit_frame()
3679 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { in mvpp2_xdp_submit_frame()
3692 dma_sync_single_for_device(port->dev->dev.parent, dma_addr, in mvpp2_xdp_submit_frame()
3698 mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr); in mvpp2_xdp_submit_frame()
3700 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); in mvpp2_xdp_submit_frame()
3701 mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type); in mvpp2_xdp_submit_frame()
3708 mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp) in mvpp2_xdp_xmit_back() argument
3710 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); in mvpp2_xdp_xmit_back()
3722 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); in mvpp2_xdp_xmit_back()
3724 ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false); in mvpp2_xdp_xmit_back()
3732 mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len); in mvpp2_xdp_xmit_back()
3746 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_xdp_xmit() local
3752 if (unlikely(test_bit(0, &port->state))) in mvpp2_xdp_xmit()
3761 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); in mvpp2_xdp_xmit()
3764 ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true); in mvpp2_xdp_xmit()
3773 mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte); in mvpp2_xdp_xmit()
3775 stats = this_cpu_ptr(port->stats); in mvpp2_xdp_xmit()
3787 mvpp2_run_xdp(struct mvpp2_port *port, struct bpf_prog *prog, in mvpp2_run_xdp() argument
3808 err = xdp_do_redirect(port->dev, xdp, prog); in mvpp2_run_xdp()
3819 ret = mvpp2_xdp_xmit_back(port, xdp); in mvpp2_run_xdp()
3826 bpf_warn_invalid_xdp_action(port->dev, prog, act); in mvpp2_run_xdp()
3829 trace_xdp_exception(port->dev, prog, act); in mvpp2_run_xdp()
3842 static void mvpp2_buff_hdr_pool_put(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc, in mvpp2_buff_hdr_pool_put() argument
3849 phys_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); in mvpp2_buff_hdr_pool_put()
3850 dma_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); in mvpp2_buff_hdr_pool_put()
3858 if (port->priv->hw_version >= MVPP22) { in mvpp2_buff_hdr_pool_put()
3863 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); in mvpp2_buff_hdr_pool_put()
3872 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, in mvpp2_rx() argument
3875 struct net_device *dev = port->dev; in mvpp2_rx()
3884 xdp_prog = READ_ONCE(port->xdp_prog); in mvpp2_rx()
3887 rx_received = mvpp2_rxq_received(port, rxq->id); in mvpp2_rx()
3904 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); in mvpp2_rx()
3910 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); in mvpp2_rx()
3911 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); in mvpp2_rx()
3913 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); in mvpp2_rx()
3917 bm_pool = &port->priv->bm_pools[pool]; in mvpp2_rx()
3919 if (port->priv->percpu_pools) { in mvpp2_rx()
3920 pp = port->priv->page_pool[pool]; in mvpp2_rx()
3963 ret = mvpp2_run_xdp(port, xdp_prog, &xdp, pp, &ps); in mvpp2_rx()
3967 err = mvpp2_rx_refill(port, bm_pool, pp, pool); in mvpp2_rx()
3969 netdev_err(port->dev, "failed to refill BM pools\n"); in mvpp2_rx()
3981 netdev_warn(port->dev, "skb build failed\n"); in mvpp2_rx()
3988 if (mvpp22_rx_hwtstamping(port)) { in mvpp2_rx()
3990 mvpp22_tai_tstamp(port->priv->tai, timestamp, in mvpp2_rx()
3994 err = mvpp2_rx_refill(port, bm_pool, pp, pool); in mvpp2_rx()
3996 netdev_err(port->dev, "failed to refill BM pools\n"); in mvpp2_rx()
4013 skb->ip_summed = mvpp2_rx_csum(port, rx_status); in mvpp2_rx()
4021 mvpp2_rx_error(port, rx_desc); in mvpp2_rx()
4024 mvpp2_buff_hdr_pool_put(port, rx_desc, pool, rx_status); in mvpp2_rx()
4026 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); in mvpp2_rx()
4033 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); in mvpp2_rx()
4047 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); in mvpp2_rx()
4053 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, in tx_desc_unmap_put() argument
4056 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in tx_desc_unmap_put()
4060 mvpp2_txdesc_dma_addr_get(port, desc); in tx_desc_unmap_put()
4062 mvpp2_txdesc_size_get(port, desc); in tx_desc_unmap_put()
4064 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, in tx_desc_unmap_put()
4069 static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port, in mvpp2_txdesc_clear_ptp() argument
4073 if (port->priv->hw_version >= MVPP22) in mvpp2_txdesc_clear_ptp()
4078 static bool mvpp2_tx_hw_tstamp(struct mvpp2_port *port, in mvpp2_tx_hw_tstamp() argument
4087 if (port->priv->hw_version == MVPP21 || in mvpp2_tx_hw_tstamp()
4088 port->tx_hwtstamp_type == HWTSTAMP_TX_OFF) in mvpp2_tx_hw_tstamp()
4103 queue = &port->tx_hwtstamp_queue[0]; in mvpp2_tx_hw_tstamp()
4116 queue = &port->tx_hwtstamp_queue[1]; in mvpp2_tx_hw_tstamp()
4158 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, in mvpp2_tx_frag_process() argument
4162 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_tx_frag_process()
4173 mvpp2_txdesc_clear_ptp(port, tx_desc); in mvpp2_tx_frag_process()
4174 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_tx_frag_process()
4175 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag)); in mvpp2_tx_frag_process()
4177 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, in mvpp2_tx_frag_process()
4180 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { in mvpp2_tx_frag_process()
4185 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); in mvpp2_tx_frag_process()
4189 mvpp2_txdesc_cmd_set(port, tx_desc, in mvpp2_tx_frag_process()
4191 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); in mvpp2_tx_frag_process()
4194 mvpp2_txdesc_cmd_set(port, tx_desc, 0); in mvpp2_tx_frag_process()
4195 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); in mvpp2_tx_frag_process()
4206 tx_desc_unmap_put(port, txq, tx_desc); in mvpp2_tx_frag_process()
4219 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_tso_put_hdr() local
4223 mvpp2_txdesc_clear_ptp(port, tx_desc); in mvpp2_tso_put_hdr()
4224 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_tso_put_hdr()
4225 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); in mvpp2_tso_put_hdr()
4229 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); in mvpp2_tso_put_hdr()
4231 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | in mvpp2_tso_put_hdr()
4234 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); in mvpp2_tso_put_hdr()
4244 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_tso_put_data() local
4248 mvpp2_txdesc_clear_ptp(port, tx_desc); in mvpp2_tso_put_data()
4249 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_tso_put_data()
4250 mvpp2_txdesc_size_set(port, tx_desc, sz); in mvpp2_tso_put_data()
4259 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); in mvpp2_tso_put_data()
4262 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); in mvpp2_tso_put_data()
4264 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); in mvpp2_tso_put_data()
4268 mvpp2_txdesc_cmd_set(port, tx_desc, 0); in mvpp2_tso_put_data()
4271 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); in mvpp2_tso_put_data()
4280 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_tx_tso() local
4285 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) || in mvpp2_tx_tso()
4286 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, in mvpp2_tx_tso()
4321 tx_desc_unmap_put(port, txq, tx_desc); in mvpp2_tx_tso()
4329 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_tx() local
4340 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_tx()
4343 txq = port->txqs[txq_id]; in mvpp2_tx()
4345 aggr_txq = &port->priv->aggr_txqs[thread]; in mvpp2_tx()
4347 if (test_bit(thread, &port->priv->lock_map)) in mvpp2_tx()
4348 spin_lock_irqsave(&port->tx_lock[thread], flags); in mvpp2_tx()
4357 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) || in mvpp2_tx()
4358 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) { in mvpp2_tx()
4366 !mvpp2_tx_hw_tstamp(port, tx_desc, skb)) in mvpp2_tx()
4367 mvpp2_txdesc_clear_ptp(port, tx_desc); in mvpp2_tx()
4368 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); in mvpp2_tx()
4369 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); in mvpp2_tx()
4379 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); in mvpp2_tx()
4381 tx_cmd = mvpp2_skb_tx_csum(port, skb); in mvpp2_tx()
4386 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); in mvpp2_tx()
4387 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); in mvpp2_tx()
4391 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); in mvpp2_tx()
4392 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); in mvpp2_tx()
4395 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { in mvpp2_tx()
4396 tx_desc_unmap_put(port, txq, tx_desc); in mvpp2_tx()
4403 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread); in mvpp2_tx()
4412 mvpp2_aggr_txq_pend_desc_add(port, frags); in mvpp2_tx()
4427 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) in mvpp2_tx()
4428 mvpp2_txq_done(port, txq, txq_pcpu); in mvpp2_tx()
4431 if (!port->has_tx_irqs && txq_pcpu->count <= frags && in mvpp2_tx()
4433 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread); in mvpp2_tx()
4443 if (test_bit(thread, &port->priv->lock_map)) in mvpp2_tx()
4444 spin_unlock_irqrestore(&port->tx_lock[thread], flags); in mvpp2_tx()
4463 struct mvpp2_port *port = netdev_priv(napi->dev); in mvpp2_poll() local
4465 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); in mvpp2_poll()
4479 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id, in mvpp2_poll()
4480 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); in mvpp2_poll()
4484 mvpp2_cause_error(port->dev, cause_misc); in mvpp2_poll()
4487 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); in mvpp2_poll()
4488 mvpp2_thread_write(port->priv, thread, in mvpp2_poll()
4489 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), in mvpp2_poll()
4493 if (port->has_tx_irqs) { in mvpp2_poll()
4497 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); in mvpp2_poll()
4503 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); in mvpp2_poll()
4510 rxq = mvpp2_get_rx_queue(port, cause_rx); in mvpp2_poll()
4514 count = mvpp2_rx(port, napi, budget, rxq); in mvpp2_poll()
4536 static void mvpp22_mode_reconfigure(struct mvpp2_port *port, in mvpp22_mode_reconfigure() argument
4542 mvpp2_mac_reset_assert(port); in mvpp22_mode_reconfigure()
4545 mvpp22_pcs_reset_assert(port); in mvpp22_mode_reconfigure()
4548 mvpp22_comphy_init(port, interface); in mvpp22_mode_reconfigure()
4551 mvpp22_gop_init(port, interface); in mvpp22_mode_reconfigure()
4553 mvpp22_pcs_reset_deassert(port, interface); in mvpp22_mode_reconfigure()
4555 if (mvpp2_port_supports_xlg(port)) { in mvpp22_mode_reconfigure()
4556 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); in mvpp22_mode_reconfigure()
4564 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); in mvpp22_mode_reconfigure()
4567 if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(interface)) in mvpp22_mode_reconfigure()
4568 mvpp2_xlg_max_rx_size_set(port); in mvpp22_mode_reconfigure()
4570 mvpp2_gmac_max_rx_size_set(port); in mvpp22_mode_reconfigure()
4573 /* Set hw internals when starting port */
4574 static void mvpp2_start_dev(struct mvpp2_port *port) in mvpp2_start_dev() argument
4578 mvpp2_txp_max_tx_size_set(port); in mvpp2_start_dev()
4580 for (i = 0; i < port->nqvecs; i++) in mvpp2_start_dev()
4581 napi_enable(&port->qvecs[i].napi); in mvpp2_start_dev()
4584 mvpp2_interrupts_enable(port); in mvpp2_start_dev()
4586 if (port->priv->hw_version >= MVPP22) in mvpp2_start_dev()
4587 mvpp22_mode_reconfigure(port, port->phy_interface); in mvpp2_start_dev()
4589 if (port->phylink) { in mvpp2_start_dev()
4590 phylink_start(port->phylink); in mvpp2_start_dev()
4592 mvpp2_acpi_start(port); in mvpp2_start_dev()
4595 netif_tx_start_all_queues(port->dev); in mvpp2_start_dev()
4597 clear_bit(0, &port->state); in mvpp2_start_dev()
4600 /* Set hw internals when stopping port */
4601 static void mvpp2_stop_dev(struct mvpp2_port *port) in mvpp2_stop_dev() argument
4605 set_bit(0, &port->state); in mvpp2_stop_dev()
4608 mvpp2_interrupts_disable(port); in mvpp2_stop_dev()
4610 for (i = 0; i < port->nqvecs; i++) in mvpp2_stop_dev()
4611 napi_disable(&port->qvecs[i].napi); in mvpp2_stop_dev()
4613 if (port->phylink) in mvpp2_stop_dev()
4614 phylink_stop(port->phylink); in mvpp2_stop_dev()
4615 phy_power_off(port->comphy); in mvpp2_stop_dev()
4660 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) in mvpp21_get_mac_address() argument
4664 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); in mvpp21_get_mac_address()
4665 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); in mvpp21_get_mac_address()
4666 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); in mvpp21_get_mac_address()
4675 static int mvpp2_irqs_init(struct mvpp2_port *port) in mvpp2_irqs_init() argument
4679 for (i = 0; i < port->nqvecs; i++) { in mvpp2_irqs_init()
4680 struct mvpp2_queue_vector *qv = port->qvecs + i; in mvpp2_irqs_init()
4692 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); in mvpp2_irqs_init()
4700 if (mvpp2_cpu_to_thread(port->priv, cpu) == in mvpp2_irqs_init()
4711 for (i = 0; i < port->nqvecs; i++) { in mvpp2_irqs_init()
4712 struct mvpp2_queue_vector *qv = port->qvecs + i; in mvpp2_irqs_init()
4723 static void mvpp2_irqs_deinit(struct mvpp2_port *port) in mvpp2_irqs_deinit() argument
4727 for (i = 0; i < port->nqvecs; i++) { in mvpp2_irqs_deinit()
4728 struct mvpp2_queue_vector *qv = port->qvecs + i; in mvpp2_irqs_deinit()
4738 static bool mvpp22_rss_is_supported(struct mvpp2_port *port) in mvpp22_rss_is_supported() argument
4741 !(port->flags & MVPP2_F_LOOPBACK); in mvpp22_rss_is_supported()
4746 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_open() local
4747 struct mvpp2 *priv = port->priv; in mvpp2_open()
4753 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); in mvpp2_open()
4758 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); in mvpp2_open()
4763 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); in mvpp2_open()
4768 err = mvpp2_prs_def_flow(port); in mvpp2_open()
4775 err = mvpp2_setup_rxqs(port); in mvpp2_open()
4777 netdev_err(port->dev, "cannot allocate Rx queues\n"); in mvpp2_open()
4781 err = mvpp2_setup_txqs(port); in mvpp2_open()
4783 netdev_err(port->dev, "cannot allocate Tx queues\n"); in mvpp2_open()
4787 err = mvpp2_irqs_init(port); in mvpp2_open()
4789 netdev_err(port->dev, "cannot init IRQs\n"); in mvpp2_open()
4793 if (port->phylink) { in mvpp2_open()
4794 err = phylink_fwnode_phy_connect(port->phylink, port->fwnode, 0); in mvpp2_open()
4796 netdev_err(port->dev, "could not attach PHY (%d)\n", in mvpp2_open()
4804 if (priv->hw_version >= MVPP22 && port->port_irq) { in mvpp2_open()
4805 err = request_irq(port->port_irq, mvpp2_port_isr, 0, in mvpp2_open()
4806 dev->name, port); in mvpp2_open()
4808 netdev_err(port->dev, in mvpp2_open()
4809 "cannot request port link/ptp IRQ %d\n", in mvpp2_open()
4810 port->port_irq); in mvpp2_open()
4814 mvpp22_gop_setup_irq(port); in mvpp2_open()
4817 netif_carrier_off(port->dev); in mvpp2_open()
4821 port->port_irq = 0; in mvpp2_open()
4825 netdev_err(port->dev, in mvpp2_open()
4832 on_each_cpu(mvpp2_interrupts_unmask, port, 1); in mvpp2_open()
4833 mvpp2_shared_interrupt_mask_unmask(port, false); in mvpp2_open()
4835 mvpp2_start_dev(port); in mvpp2_open()
4838 queue_delayed_work(priv->stats_queue, &port->stats_work, in mvpp2_open()
4844 mvpp2_irqs_deinit(port); in mvpp2_open()
4846 mvpp2_cleanup_txqs(port); in mvpp2_open()
4848 mvpp2_cleanup_rxqs(port); in mvpp2_open()
4854 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_stop() local
4858 mvpp2_stop_dev(port); in mvpp2_stop()
4861 on_each_cpu(mvpp2_interrupts_mask, port, 1); in mvpp2_stop()
4862 mvpp2_shared_interrupt_mask_unmask(port, true); in mvpp2_stop()
4864 if (port->phylink) in mvpp2_stop()
4865 phylink_disconnect_phy(port->phylink); in mvpp2_stop()
4866 if (port->port_irq) in mvpp2_stop()
4867 free_irq(port->port_irq, port); in mvpp2_stop()
4869 mvpp2_irqs_deinit(port); in mvpp2_stop()
4870 if (!port->has_tx_irqs) { in mvpp2_stop()
4871 for (thread = 0; thread < port->priv->nthreads; thread++) { in mvpp2_stop()
4872 port_pcpu = per_cpu_ptr(port->pcpu, thread); in mvpp2_stop()
4878 mvpp2_cleanup_rxqs(port); in mvpp2_stop()
4879 mvpp2_cleanup_txqs(port); in mvpp2_stop()
4881 cancel_delayed_work_sync(&port->stats_work); in mvpp2_stop()
4883 mvpp2_mac_reset_assert(port); in mvpp2_stop()
4884 mvpp22_pcs_reset_assert(port); in mvpp2_stop()
4889 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, in mvpp2_prs_mac_da_accept_list() argument
4896 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); in mvpp2_prs_mac_da_accept_list()
4904 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) in mvpp2_set_rx_promisc() argument
4906 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) in mvpp2_set_rx_promisc()
4907 mvpp2_prs_vid_enable_filtering(port); in mvpp2_set_rx_promisc()
4909 mvpp2_prs_vid_disable_filtering(port); in mvpp2_set_rx_promisc()
4911 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_promisc()
4914 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_promisc()
4920 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_set_rx_mode() local
4923 mvpp2_prs_mac_del_all(port); in mvpp2_set_rx_mode()
4926 mvpp2_set_rx_promisc(port, true); in mvpp2_set_rx_mode()
4930 mvpp2_set_rx_promisc(port, false); in mvpp2_set_rx_mode()
4933 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) in mvpp2_set_rx_mode()
4934 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_mode()
4938 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_mode()
4944 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) in mvpp2_set_rx_mode()
4945 mvpp2_prs_mac_promisc_set(port->priv, port->id, in mvpp2_set_rx_mode()
4973 struct mvpp2_port *port = NULL; in mvpp2_bm_switch_buffers() local
4977 port = priv->port_list[i]; in mvpp2_bm_switch_buffers()
4978 status[i] = netif_running(port->dev); in mvpp2_bm_switch_buffers()
4980 mvpp2_stop(port->dev); in mvpp2_bm_switch_buffers()
4985 numbufs = port->nrxqs * 2; in mvpp2_bm_switch_buffers()
4991 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]); in mvpp2_bm_switch_buffers()
4993 devm_kfree(port->dev->dev.parent, priv->bm_pools); in mvpp2_bm_switch_buffers()
4995 mvpp2_bm_init(port->dev->dev.parent, priv); in mvpp2_bm_switch_buffers()
4998 port = priv->port_list[i]; in mvpp2_bm_switch_buffers()
4999 mvpp2_swf_bm_pool_init(port); in mvpp2_bm_switch_buffers()
5001 mvpp2_open(port->dev); in mvpp2_bm_switch_buffers()
5012 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_change_mtu() local
5014 struct mvpp2 *priv = port->priv; in mvpp2_change_mtu()
5023 if (port->xdp_prog && mtu > MVPP2_MAX_RX_BUF_SIZE) { in mvpp2_change_mtu()
5039 if (priv->port_list[i] != port && in mvpp2_change_mtu()
5046 /* No port is using jumbo frames */ in mvpp2_change_mtu()
5048 dev_info(port->dev->dev.parent, in mvpp2_change_mtu()
5055 mvpp2_stop_dev(port); in mvpp2_change_mtu()
5063 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); in mvpp2_change_mtu()
5067 mvpp2_start_dev(port); in mvpp2_change_mtu()
5068 mvpp2_egress_enable(port); in mvpp2_change_mtu()
5069 mvpp2_ingress_enable(port); in mvpp2_change_mtu()
5075 static int mvpp2_check_pagepool_dma(struct mvpp2_port *port) in mvpp2_check_pagepool_dma() argument
5078 struct mvpp2 *priv = port->priv; in mvpp2_check_pagepool_dma()
5088 port = priv->port_list[i]; in mvpp2_check_pagepool_dma()
5089 if (port->xdp_prog) { in mvpp2_check_pagepool_dma()
5105 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_get_stats64() local
5116 cpu_stats = per_cpu_ptr(port->stats, cpu); in mvpp2_get_stats64()
5136 static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr) in mvpp2_set_ts_config() argument
5149 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); in mvpp2_set_ts_config()
5164 mvpp22_tai_start(port->priv->tai); in mvpp2_set_ts_config()
5172 port->rx_hwtstamp = true; in mvpp2_set_ts_config()
5174 port->rx_hwtstamp = false; in mvpp2_set_ts_config()
5186 mvpp22_tai_stop(port->priv->tai); in mvpp2_set_ts_config()
5188 port->tx_hwtstamp_type = config.tx_type; in mvpp2_set_ts_config()
5196 static int mvpp2_get_ts_config(struct mvpp2_port *port, struct ifreq *ifr) in mvpp2_get_ts_config() argument
5202 config.tx_type = port->tx_hwtstamp_type; in mvpp2_get_ts_config()
5203 config.rx_filter = port->rx_hwtstamp ? in mvpp2_get_ts_config()
5215 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_ts_info() local
5217 if (!port->hwtstamp) in mvpp2_ethtool_get_ts_info()
5220 info->phc_index = mvpp22_tai_ptp_clock_index(port->priv->tai); in mvpp2_ethtool_get_ts_info()
5237 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ioctl() local
5241 if (port->hwtstamp) in mvpp2_ioctl()
5242 return mvpp2_set_ts_config(port, ifr); in mvpp2_ioctl()
5246 if (port->hwtstamp) in mvpp2_ioctl()
5247 return mvpp2_get_ts_config(port, ifr); in mvpp2_ioctl()
5251 if (!port->phylink) in mvpp2_ioctl()
5254 return phylink_mii_ioctl(port->phylink, ifr, cmd); in mvpp2_ioctl()
5259 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_vlan_rx_add_vid() local
5262 ret = mvpp2_prs_vid_entry_add(port, vid); in mvpp2_vlan_rx_add_vid()
5264 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", in mvpp2_vlan_rx_add_vid()
5271 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_vlan_rx_kill_vid() local
5273 mvpp2_prs_vid_entry_remove(port, vid); in mvpp2_vlan_rx_kill_vid()
5281 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_set_features() local
5285 mvpp2_prs_vid_enable_filtering(port); in mvpp2_set_features()
5288 * port in mvpp2_set_features()
5290 mvpp2_prs_vid_remove_all(port); in mvpp2_set_features()
5292 mvpp2_prs_vid_disable_filtering(port); in mvpp2_set_features()
5298 mvpp22_port_rss_enable(port); in mvpp2_set_features()
5300 mvpp22_port_rss_disable(port); in mvpp2_set_features()
5306 static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf) in mvpp2_xdp_setup() argument
5309 bool running = netif_running(port->dev); in mvpp2_xdp_setup()
5310 bool reset = !prog != !port->xdp_prog; in mvpp2_xdp_setup()
5312 if (port->dev->mtu > MVPP2_MAX_RX_BUF_SIZE) { in mvpp2_xdp_setup()
5317 if (!port->priv->percpu_pools) { in mvpp2_xdp_setup()
5322 if (port->ntxqs < num_possible_cpus() * 2) { in mvpp2_xdp_setup()
5329 mvpp2_stop(port->dev); in mvpp2_xdp_setup()
5331 old_prog = xchg(&port->xdp_prog, prog); in mvpp2_xdp_setup()
5341 mvpp2_open(port->dev); in mvpp2_xdp_setup()
5344 mvpp2_check_pagepool_dma(port); in mvpp2_xdp_setup()
5351 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_xdp() local
5355 return mvpp2_xdp_setup(port, xdp); in mvpp2_xdp()
5365 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_nway_reset() local
5367 if (!port->phylink) in mvpp2_ethtool_nway_reset()
5370 return phylink_ethtool_nway_reset(port->phylink); in mvpp2_ethtool_nway_reset()
5380 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_coalesce() local
5383 for (queue = 0; queue < port->nrxqs; queue++) { in mvpp2_ethtool_set_coalesce()
5384 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; in mvpp2_ethtool_set_coalesce()
5388 mvpp2_rx_pkts_coal_set(port, rxq); in mvpp2_ethtool_set_coalesce()
5389 mvpp2_rx_time_coal_set(port, rxq); in mvpp2_ethtool_set_coalesce()
5392 if (port->has_tx_irqs) { in mvpp2_ethtool_set_coalesce()
5393 port->tx_time_coal = c->tx_coalesce_usecs; in mvpp2_ethtool_set_coalesce()
5394 mvpp2_tx_time_coal_set(port); in mvpp2_ethtool_set_coalesce()
5397 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_ethtool_set_coalesce()
5398 struct mvpp2_tx_queue *txq = port->txqs[queue]; in mvpp2_ethtool_set_coalesce()
5402 if (port->has_tx_irqs) in mvpp2_ethtool_set_coalesce()
5403 mvpp2_tx_pkts_coal_set(port, txq); in mvpp2_ethtool_set_coalesce()
5416 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_coalesce() local
5418 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; in mvpp2_ethtool_get_coalesce()
5419 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; in mvpp2_ethtool_get_coalesce()
5420 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; in mvpp2_ethtool_get_coalesce()
5421 c->tx_coalesce_usecs = port->tx_time_coal; in mvpp2_ethtool_get_coalesce()
5442 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_ringparam() local
5446 ring->rx_pending = port->rx_ring_size; in mvpp2_ethtool_get_ringparam()
5447 ring->tx_pending = port->tx_ring_size; in mvpp2_ethtool_get_ringparam()
5456 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_ringparam() local
5457 u16 prev_rx_ring_size = port->rx_ring_size; in mvpp2_ethtool_set_ringparam()
5458 u16 prev_tx_ring_size = port->tx_ring_size; in mvpp2_ethtool_set_ringparam()
5466 port->rx_ring_size = ring->rx_pending; in mvpp2_ethtool_set_ringparam()
5467 port->tx_ring_size = ring->tx_pending; in mvpp2_ethtool_set_ringparam()
5474 mvpp2_stop_dev(port); in mvpp2_ethtool_set_ringparam()
5475 mvpp2_cleanup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5476 mvpp2_cleanup_txqs(port); in mvpp2_ethtool_set_ringparam()
5478 port->rx_ring_size = ring->rx_pending; in mvpp2_ethtool_set_ringparam()
5479 port->tx_ring_size = ring->tx_pending; in mvpp2_ethtool_set_ringparam()
5481 err = mvpp2_setup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5484 port->rx_ring_size = prev_rx_ring_size; in mvpp2_ethtool_set_ringparam()
5486 err = mvpp2_setup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5490 err = mvpp2_setup_txqs(port); in mvpp2_ethtool_set_ringparam()
5493 port->tx_ring_size = prev_tx_ring_size; in mvpp2_ethtool_set_ringparam()
5495 err = mvpp2_setup_txqs(port); in mvpp2_ethtool_set_ringparam()
5500 mvpp2_start_dev(port); in mvpp2_ethtool_set_ringparam()
5501 mvpp2_egress_enable(port); in mvpp2_ethtool_set_ringparam()
5502 mvpp2_ingress_enable(port); in mvpp2_ethtool_set_ringparam()
5507 mvpp2_cleanup_rxqs(port); in mvpp2_ethtool_set_ringparam()
5516 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_pause_param() local
5518 if (!port->phylink) in mvpp2_ethtool_get_pause_param()
5521 phylink_ethtool_get_pauseparam(port->phylink, pause); in mvpp2_ethtool_get_pause_param()
5527 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_pause_param() local
5529 if (!port->phylink) in mvpp2_ethtool_set_pause_param()
5532 return phylink_ethtool_set_pauseparam(port->phylink, pause); in mvpp2_ethtool_set_pause_param()
5538 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_link_ksettings() local
5540 if (!port->phylink) in mvpp2_ethtool_get_link_ksettings()
5543 return phylink_ethtool_ksettings_get(port->phylink, cmd); in mvpp2_ethtool_get_link_ksettings()
5549 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_link_ksettings() local
5551 if (!port->phylink) in mvpp2_ethtool_set_link_ksettings()
5554 return phylink_ethtool_ksettings_set(port->phylink, cmd); in mvpp2_ethtool_set_link_ksettings()
5560 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_rxnfc() local
5563 if (!mvpp22_rss_is_supported(port)) in mvpp2_ethtool_get_rxnfc()
5568 ret = mvpp2_ethtool_rxfh_get(port, info); in mvpp2_ethtool_get_rxnfc()
5571 info->data = port->nrxqs; in mvpp2_ethtool_get_rxnfc()
5574 info->rule_cnt = port->n_rfs_rules; in mvpp2_ethtool_get_rxnfc()
5577 ret = mvpp2_ethtool_cls_rule_get(port, info); in mvpp2_ethtool_get_rxnfc()
5581 if (port->rfs_rules[i]) in mvpp2_ethtool_get_rxnfc()
5595 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_rxnfc() local
5598 if (!mvpp22_rss_is_supported(port)) in mvpp2_ethtool_set_rxnfc()
5603 ret = mvpp2_ethtool_rxfh_set(port, info); in mvpp2_ethtool_set_rxnfc()
5606 ret = mvpp2_ethtool_cls_rule_ins(port, info); in mvpp2_ethtool_set_rxnfc()
5609 ret = mvpp2_ethtool_cls_rule_del(port, info); in mvpp2_ethtool_set_rxnfc()
5619 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_rxfh_indir_size() local
5621 return mvpp22_rss_is_supported(port) ? MVPP22_RSS_TABLE_ENTRIES : 0; in mvpp2_ethtool_get_rxfh_indir_size()
5627 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_rxfh() local
5630 if (!mvpp22_rss_is_supported(port)) in mvpp2_ethtool_get_rxfh()
5634 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir); in mvpp2_ethtool_get_rxfh()
5645 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_rxfh() local
5648 if (!mvpp22_rss_is_supported(port)) in mvpp2_ethtool_set_rxfh()
5658 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir); in mvpp2_ethtool_set_rxfh()
5666 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_get_rxfh_context() local
5669 if (!mvpp22_rss_is_supported(port)) in mvpp2_ethtool_get_rxfh_context()
5678 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir); in mvpp2_ethtool_get_rxfh_context()
5688 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_ethtool_set_rxfh_context() local
5691 if (!mvpp22_rss_is_supported(port)) in mvpp2_ethtool_set_rxfh_context()
5701 return mvpp22_port_rss_ctx_delete(port, *rss_context); in mvpp2_ethtool_set_rxfh_context()
5704 ret = mvpp22_port_rss_ctx_create(port, rss_context); in mvpp2_ethtool_set_rxfh_context()
5709 return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir); in mvpp2_ethtool_set_rxfh_context()
5757 * had a single IRQ defined per-port.
5759 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, in mvpp2_simple_queue_vectors_init() argument
5762 struct mvpp2_queue_vector *v = &port->qvecs[0]; in mvpp2_simple_queue_vectors_init()
5765 v->nrxqs = port->nrxqs; in mvpp2_simple_queue_vectors_init()
5769 v->port = port; in mvpp2_simple_queue_vectors_init()
5773 netif_napi_add(port->dev, &v->napi, mvpp2_poll); in mvpp2_simple_queue_vectors_init()
5775 port->nqvecs = 1; in mvpp2_simple_queue_vectors_init()
5780 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, in mvpp2_multi_queue_vectors_init() argument
5783 struct mvpp2 *priv = port->priv; in mvpp2_multi_queue_vectors_init()
5789 port->nqvecs = priv->nthreads + 1; in mvpp2_multi_queue_vectors_init()
5792 port->nqvecs = priv->nthreads; in mvpp2_multi_queue_vectors_init()
5796 for (i = 0; i < port->nqvecs; i++) { in mvpp2_multi_queue_vectors_init()
5799 v = port->qvecs + i; in mvpp2_multi_queue_vectors_init()
5801 v->port = port; in mvpp2_multi_queue_vectors_init()
5806 if (port->flags & MVPP2_F_DT_COMPAT) in mvpp2_multi_queue_vectors_init()
5815 i == (port->nqvecs - 1)) { in mvpp2_multi_queue_vectors_init()
5817 v->nrxqs = port->nrxqs; in mvpp2_multi_queue_vectors_init()
5820 if (port->flags & MVPP2_F_DT_COMPAT) in mvpp2_multi_queue_vectors_init()
5827 v->irq = fwnode_irq_get(port->fwnode, i); in mvpp2_multi_queue_vectors_init()
5833 netif_napi_add(port->dev, &v->napi, mvpp2_poll); in mvpp2_multi_queue_vectors_init()
5839 for (i = 0; i < port->nqvecs; i++) in mvpp2_multi_queue_vectors_init()
5840 irq_dispose_mapping(port->qvecs[i].irq); in mvpp2_multi_queue_vectors_init()
5844 static int mvpp2_queue_vectors_init(struct mvpp2_port *port, in mvpp2_queue_vectors_init() argument
5847 if (port->has_tx_irqs) in mvpp2_queue_vectors_init()
5848 return mvpp2_multi_queue_vectors_init(port, port_node); in mvpp2_queue_vectors_init()
5850 return mvpp2_simple_queue_vectors_init(port, port_node); in mvpp2_queue_vectors_init()
5853 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) in mvpp2_queue_vectors_deinit() argument
5857 for (i = 0; i < port->nqvecs; i++) in mvpp2_queue_vectors_deinit()
5858 irq_dispose_mapping(port->qvecs[i].irq); in mvpp2_queue_vectors_deinit()
5861 /* Configure Rx queue group interrupt for this port */
5862 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) in mvpp2_rx_irqs_setup() argument
5864 struct mvpp2 *priv = port->priv; in mvpp2_rx_irqs_setup()
5869 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), in mvpp2_rx_irqs_setup()
5870 port->nrxqs); in mvpp2_rx_irqs_setup()
5875 for (i = 0; i < port->nqvecs; i++) { in mvpp2_rx_irqs_setup()
5876 struct mvpp2_queue_vector *qv = port->qvecs + i; in mvpp2_rx_irqs_setup()
5882 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; in mvpp2_rx_irqs_setup()
5891 /* Initialize port HW */
5892 static int mvpp2_port_init(struct mvpp2_port *port) in mvpp2_port_init() argument
5894 struct device *dev = port->dev->dev.parent; in mvpp2_port_init()
5895 struct mvpp2 *priv = port->priv; in mvpp2_port_init()
5901 if (port->first_rxq + port->nrxqs > in mvpp2_port_init()
5905 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ) in mvpp2_port_init()
5908 /* Disable port */ in mvpp2_port_init()
5909 mvpp2_egress_disable(port); in mvpp2_port_init()
5910 mvpp2_port_disable(port); in mvpp2_port_init()
5912 if (mvpp2_is_xlg(port->phy_interface)) { in mvpp2_port_init()
5913 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_init()
5916 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_init()
5918 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_init()
5921 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_port_init()
5924 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; in mvpp2_port_init()
5926 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), in mvpp2_port_init()
5928 if (!port->txqs) in mvpp2_port_init()
5931 /* Associate physical Tx queues to this port and initialize. in mvpp2_port_init()
5934 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_port_init()
5935 int queue_phy_id = mvpp2_txq_phys(port->id, queue); in mvpp2_port_init()
5958 port->txqs[queue] = txq; in mvpp2_port_init()
5961 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), in mvpp2_port_init()
5963 if (!port->rxqs) { in mvpp2_port_init()
5968 /* Allocate and initialize Rx queue for this port */ in mvpp2_port_init()
5969 for (queue = 0; queue < port->nrxqs; queue++) { in mvpp2_port_init()
5972 /* Map physical Rx queue to port's logical Rx queue */ in mvpp2_port_init()
5979 rxq->id = port->first_rxq + queue; in mvpp2_port_init()
5980 rxq->port = port->id; in mvpp2_port_init()
5983 port->rxqs[queue] = rxq; in mvpp2_port_init()
5986 mvpp2_rx_irqs_setup(port); in mvpp2_port_init()
5989 for (queue = 0; queue < port->nrxqs; queue++) { in mvpp2_port_init()
5990 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; in mvpp2_port_init()
5992 rxq->size = port->rx_ring_size; in mvpp2_port_init()
5997 mvpp2_ingress_disable(port); in mvpp2_port_init()
5999 /* Port default configuration */ in mvpp2_port_init()
6000 mvpp2_defaults_set(port); in mvpp2_port_init()
6002 /* Port's classifier configuration */ in mvpp2_port_init()
6003 mvpp2_cls_oversize_rxq_set(port); in mvpp2_port_init()
6004 mvpp2_cls_port_config(port); in mvpp2_port_init()
6006 if (mvpp22_rss_is_supported(port)) in mvpp2_port_init()
6007 mvpp22_port_rss_init(port); in mvpp2_port_init()
6010 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); in mvpp2_port_init()
6013 err = mvpp2_swf_bm_pool_init(port); in mvpp2_port_init()
6017 /* Clear all port stats */ in mvpp2_port_init()
6018 mvpp2_read_stats(port); in mvpp2_port_init()
6019 memset(port->ethtool_stats, 0, in mvpp2_port_init()
6020 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64)); in mvpp2_port_init()
6025 for (queue = 0; queue < port->ntxqs; queue++) { in mvpp2_port_init()
6026 if (!port->txqs[queue]) in mvpp2_port_init()
6028 free_percpu(port->txqs[queue]->pcpu); in mvpp2_port_init()
6049 /* Checks if the port dt description has the required Tx interrupts:
6088 struct mvpp2_port *port = netdev_priv(dev); in mvpp2_port_copy_mac_addr() local
6099 mvpp21_get_mac_address(port, hw_mac_addr); in mvpp2_port_copy_mac_addr()
6129 struct mvpp2_port *port = mvpp2_pcs_xlg_to_port(pcs); in mvpp2_xlg_pcs_get_state() local
6132 if (port->phy_interface == PHY_INTERFACE_MODE_5GBASER) in mvpp2_xlg_pcs_get_state()
6139 val = readl(port->base + MVPP22_XLG_STATUS); in mvpp2_xlg_pcs_get_state()
6143 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_pcs_get_state()
6182 struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs); in mvpp2_gmac_pcs_get_state() local
6185 val = readl(port->base + MVPP2_GMAC_STATUS0); in mvpp2_gmac_pcs_get_state()
6191 switch (port->phy_interface) { in mvpp2_gmac_pcs_get_state()
6219 struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs); in mvpp2_gmac_pcs_config() local
6261 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_config()
6265 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_config()
6273 struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs); in mvpp2_gmac_pcs_an_restart() local
6274 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_an_restart()
6277 port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_an_restart()
6279 port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_gmac_pcs_an_restart()
6289 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, in mvpp2_xlg_config() argument
6294 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_xlg_config()
6297 mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG, in mvpp2_xlg_config()
6305 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_config()
6309 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, in mvpp2_gmac_config() argument
6316 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_config()
6317 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_gmac_config()
6318 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); in mvpp2_gmac_config()
6323 /* Configure port type */ in mvpp2_gmac_config()
6361 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); in mvpp2_gmac_config()
6363 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); in mvpp2_gmac_config()
6365 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); in mvpp2_gmac_config()
6371 struct mvpp2_port *port = mvpp2_phylink_to_port(config); in mvpp2_select_pcs() local
6378 return &port->pcs_xlg; in mvpp2_select_pcs()
6380 return &port->pcs_gmac; in mvpp2_select_pcs()
6386 struct mvpp2_port *port = mvpp2_phylink_to_port(config); in mvpp2_mac_prepare() local
6389 if (mvpp2_is_xlg(interface) && port->gop_id != 0) { in mvpp2_mac_prepare()
6390 netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name); in mvpp2_mac_prepare()
6394 if (port->phy_interface != interface || in mvpp2_mac_prepare()
6402 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, in mvpp2_mac_prepare()
6407 if (mvpp2_port_supports_xlg(port)) in mvpp2_mac_prepare()
6408 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_mac_prepare()
6414 /* Make sure the port is disabled when reconfiguring the mode */ in mvpp2_mac_prepare()
6415 mvpp2_port_disable(port); in mvpp2_mac_prepare()
6417 if (port->phy_interface != interface) { in mvpp2_mac_prepare()
6419 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, in mvpp2_mac_prepare()
6423 if (port->priv->hw_version >= MVPP22) { in mvpp2_mac_prepare()
6424 mvpp22_gop_mask_irq(port); in mvpp2_mac_prepare()
6426 phy_power_off(port->comphy); in mvpp2_mac_prepare()
6429 mvpp22_mode_reconfigure(port, interface); in mvpp2_mac_prepare()
6439 struct mvpp2_port *port = mvpp2_phylink_to_port(config); in mvpp2_mac_config() local
6443 mvpp2_xlg_config(port, mode, state); in mvpp2_mac_config()
6447 mvpp2_gmac_config(port, mode, state); in mvpp2_mac_config()
6449 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) in mvpp2_mac_config()
6450 mvpp2_port_loopback_set(port, state); in mvpp2_mac_config()
6456 struct mvpp2_port *port = mvpp2_phylink_to_port(config); in mvpp2_mac_finish() local
6458 if (port->priv->hw_version >= MVPP22 && in mvpp2_mac_finish()
6459 port->phy_interface != interface) { in mvpp2_mac_finish()
6460 port->phy_interface = interface; in mvpp2_mac_finish()
6463 mvpp22_gop_unmask_irq(port); in mvpp2_mac_finish()
6468 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, in mvpp2_mac_finish()
6471 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & in mvpp2_mac_finish()
6476 mvpp2_port_enable(port); in mvpp2_mac_finish()
6483 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_mac_finish()
6487 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, in mvpp2_mac_finish()
6501 struct mvpp2_port *port = mvpp2_phylink_to_port(config); in mvpp2_mac_link_up() local
6513 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_mac_link_up()
6531 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, in mvpp2_mac_link_up()
6549 mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG, in mvpp2_mac_link_up()
6554 if (port->priv->global_tx_fc) { in mvpp2_mac_link_up()
6555 port->tx_fc = tx_pause; in mvpp2_mac_link_up()
6557 mvpp2_rxq_enable_fc(port); in mvpp2_mac_link_up()
6559 mvpp2_rxq_disable_fc(port); in mvpp2_mac_link_up()
6560 if (port->priv->percpu_pools) { in mvpp2_mac_link_up()
6561 for (i = 0; i < port->nrxqs; i++) in mvpp2_mac_link_up()
6562 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], tx_pause); in mvpp2_mac_link_up()
6564 mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause); in mvpp2_mac_link_up()
6565 mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause); in mvpp2_mac_link_up()
6567 if (port->priv->hw_version == MVPP23) in mvpp2_mac_link_up()
6568 mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause); in mvpp2_mac_link_up()
6571 mvpp2_port_enable(port); in mvpp2_mac_link_up()
6573 mvpp2_egress_enable(port); in mvpp2_mac_link_up()
6574 mvpp2_ingress_enable(port); in mvpp2_mac_link_up()
6575 netif_tx_wake_all_queues(port->dev); in mvpp2_mac_link_up()
6581 struct mvpp2_port *port = mvpp2_phylink_to_port(config); in mvpp2_mac_link_down() local
6586 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_mac_link_down()
6589 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_mac_link_down()
6591 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_mac_link_down()
6594 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); in mvpp2_mac_link_down()
6598 netif_tx_stop_all_queues(port->dev); in mvpp2_mac_link_down()
6599 mvpp2_egress_disable(port); in mvpp2_mac_link_down()
6600 mvpp2_ingress_disable(port); in mvpp2_mac_link_down()
6602 mvpp2_port_disable(port); in mvpp2_mac_link_down()
6616 static void mvpp2_acpi_start(struct mvpp2_port *port) in mvpp2_acpi_start() argument
6623 .interface = port->phy_interface, in mvpp2_acpi_start()
6627 pcs = mvpp2_select_pcs(&port->phylink_config, port->phy_interface); in mvpp2_acpi_start()
6629 mvpp2_mac_prepare(&port->phylink_config, MLO_AN_INBAND, in mvpp2_acpi_start()
6630 port->phy_interface); in mvpp2_acpi_start()
6631 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state); in mvpp2_acpi_start()
6632 pcs->ops->pcs_config(pcs, MLO_AN_INBAND, port->phy_interface, in mvpp2_acpi_start()
6634 mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND, in mvpp2_acpi_start()
6635 port->phy_interface); in mvpp2_acpi_start()
6636 mvpp2_mac_link_up(&port->phylink_config, NULL, in mvpp2_acpi_start()
6637 MLO_AN_INBAND, port->phy_interface, in mvpp2_acpi_start()
6641 /* In order to ensure backward compatibility for ACPI, check if the port
6660 struct mvpp2_port *port; in mvpp2_port_probe() local
6684 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); in mvpp2_port_probe()
6715 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { in mvpp2_port_probe()
6717 dev_err(&pdev->dev, "missing port-id value\n"); in mvpp2_port_probe()
6726 port = netdev_priv(dev); in mvpp2_port_probe()
6727 port->dev = dev; in mvpp2_port_probe()
6728 port->fwnode = port_fwnode; in mvpp2_port_probe()
6729 port->ntxqs = ntxqs; in mvpp2_port_probe()
6730 port->nrxqs = nrxqs; in mvpp2_port_probe()
6731 port->priv = priv; in mvpp2_port_probe()
6732 port->has_tx_irqs = has_tx_irqs; in mvpp2_port_probe()
6733 port->flags = flags; in mvpp2_port_probe()
6735 err = mvpp2_queue_vectors_init(port, port_node); in mvpp2_port_probe()
6740 port->port_irq = of_irq_get_byname(port_node, "link"); in mvpp2_port_probe()
6742 port->port_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); in mvpp2_port_probe()
6743 if (port->port_irq == -EPROBE_DEFER) { in mvpp2_port_probe()
6747 if (port->port_irq <= 0) in mvpp2_port_probe()
6749 port->port_irq = 0; in mvpp2_port_probe()
6752 port->flags |= MVPP2_F_LOOPBACK; in mvpp2_port_probe()
6754 port->id = id; in mvpp2_port_probe()
6756 port->first_rxq = port->id * port->nrxqs; in mvpp2_port_probe()
6758 port->first_rxq = port->id * priv->max_port_rxqs; in mvpp2_port_probe()
6760 port->of_node = port_node; in mvpp2_port_probe()
6761 port->phy_interface = phy_mode; in mvpp2_port_probe()
6762 port->comphy = comphy; in mvpp2_port_probe()
6765 port->base = devm_platform_ioremap_resource(pdev, 2 + id); in mvpp2_port_probe()
6766 if (IS_ERR(port->base)) { in mvpp2_port_probe()
6767 err = PTR_ERR(port->base); in mvpp2_port_probe()
6771 port->stats_base = port->priv->lms_base + in mvpp2_port_probe()
6773 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; in mvpp2_port_probe()
6775 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", in mvpp2_port_probe()
6776 &port->gop_id)) { in mvpp2_port_probe()
6778 dev_err(&pdev->dev, "missing gop-port-id value\n"); in mvpp2_port_probe()
6782 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); in mvpp2_port_probe()
6783 port->stats_base = port->priv->iface_base + in mvpp2_port_probe()
6785 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; in mvpp2_port_probe()
6791 port->hwtstamp = true; in mvpp2_port_probe()
6795 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); in mvpp2_port_probe()
6796 if (!port->stats) { in mvpp2_port_probe()
6801 port->ethtool_stats = devm_kcalloc(&pdev->dev, in mvpp2_port_probe()
6804 if (!port->ethtool_stats) { in mvpp2_port_probe()
6809 mutex_init(&port->gather_stats_lock); in mvpp2_port_probe()
6810 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); in mvpp2_port_probe()
6814 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; in mvpp2_port_probe()
6815 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; in mvpp2_port_probe()
6818 err = mvpp2_port_init(port); in mvpp2_port_probe()
6820 dev_err(&pdev->dev, "failed to init port %d\n", id); in mvpp2_port_probe()
6824 mvpp2_port_periodic_xon_disable(port); in mvpp2_port_probe()
6826 mvpp2_mac_reset_assert(port); in mvpp2_port_probe()
6827 mvpp22_pcs_reset_assert(port); in mvpp2_port_probe()
6829 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); in mvpp2_port_probe()
6830 if (!port->pcpu) { in mvpp2_port_probe()
6835 if (!port->has_tx_irqs) { in mvpp2_port_probe()
6837 port_pcpu = per_cpu_ptr(port->pcpu, thread); in mvpp2_port_probe()
6853 if (mvpp22_rss_is_supported(port)) { in mvpp2_port_probe()
6858 if (!port->priv->percpu_pools) in mvpp2_port_probe()
6859 mvpp2_set_hw_csum(port, port->pool_long->id); in mvpp2_port_probe()
6871 port->pcs_gmac.ops = &mvpp2_phylink_gmac_pcs_ops; in mvpp2_port_probe()
6872 port->pcs_xlg.ops = &mvpp2_phylink_xlg_pcs_ops; in mvpp2_port_probe()
6875 port->phylink_config.dev = &dev->dev; in mvpp2_port_probe()
6876 port->phylink_config.type = PHYLINK_NETDEV; in mvpp2_port_probe()
6877 port->phylink_config.mac_capabilities = in mvpp2_port_probe()
6880 if (port->priv->global_tx_fc) in mvpp2_port_probe()
6881 port->phylink_config.mac_capabilities |= in mvpp2_port_probe()
6884 if (mvpp2_port_supports_xlg(port)) { in mvpp2_port_probe()
6890 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6892 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6894 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6897 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6900 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6903 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6907 port->phylink_config.mac_capabilities |= in mvpp2_port_probe()
6910 port->phylink_config.mac_capabilities |= in mvpp2_port_probe()
6913 port->phylink_config.mac_capabilities |= in mvpp2_port_probe()
6917 if (mvpp2_port_supports_rgmii(port)) in mvpp2_port_probe()
6918 phy_interface_set_rgmii(port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6925 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6927 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6929 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6933 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6939 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6941 port->phylink_config.supported_interfaces); in mvpp2_port_probe()
6944 phylink = phylink_create(&port->phylink_config, port_fwnode, in mvpp2_port_probe()
6950 port->phylink = phylink; in mvpp2_port_probe()
6952 dev_warn(&pdev->dev, "Use link irqs for port#%d. FW update required\n", port->id); in mvpp2_port_probe()
6953 port->phylink = NULL; in mvpp2_port_probe()
6956 /* Cycle the comphy to power it down, saving 270mW per port - in mvpp2_port_probe()
6960 if (port->comphy) { in mvpp2_port_probe()
6961 err = mvpp22_comphy_init(port, port->phy_interface); in mvpp2_port_probe()
6963 phy_power_off(port->comphy); in mvpp2_port_probe()
6973 priv->port_list[priv->port_count++] = port; in mvpp2_port_probe()
6978 if (port->phylink) in mvpp2_port_probe()
6979 phylink_destroy(port->phylink); in mvpp2_port_probe()
6981 free_percpu(port->pcpu); in mvpp2_port_probe()
6983 for (i = 0; i < port->ntxqs; i++) in mvpp2_port_probe()
6984 free_percpu(port->txqs[i]->pcpu); in mvpp2_port_probe()
6986 free_percpu(port->stats); in mvpp2_port_probe()
6988 if (port->port_irq) in mvpp2_port_probe()
6989 irq_dispose_mapping(port->port_irq); in mvpp2_port_probe()
6991 mvpp2_queue_vectors_deinit(port); in mvpp2_port_probe()
6998 static void mvpp2_port_remove(struct mvpp2_port *port) in mvpp2_port_remove() argument
7002 unregister_netdev(port->dev); in mvpp2_port_remove()
7003 if (port->phylink) in mvpp2_port_remove()
7004 phylink_destroy(port->phylink); in mvpp2_port_remove()
7005 free_percpu(port->pcpu); in mvpp2_port_remove()
7006 free_percpu(port->stats); in mvpp2_port_remove()
7007 for (i = 0; i < port->ntxqs; i++) in mvpp2_port_remove()
7008 free_percpu(port->txqs[i]->pcpu); in mvpp2_port_remove()
7009 mvpp2_queue_vectors_deinit(port); in mvpp2_port_remove()
7010 if (port->port_irq) in mvpp2_port_remove()
7011 irq_dispose_mapping(port->port_irq); in mvpp2_port_remove()
7012 free_netdev(port->dev); in mvpp2_port_remove()
7051 int port; in mvpp2_rx_fifo_init() local
7053 for (port = 0; port < MVPP2_MAX_PORTS; port++) { in mvpp2_rx_fifo_init()
7054 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
7056 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), in mvpp2_rx_fifo_init()
7065 static void mvpp22_rx_fifo_set_hw(struct mvpp2 *priv, int port, int data_size) in mvpp22_rx_fifo_set_hw() argument
7069 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), data_size); in mvpp22_rx_fifo_set_hw()
7070 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), attr_size); in mvpp22_rx_fifo_set_hw()
7074 * 4kB fixed space must be assigned for the loopback port.
7076 * Guarantee minimum 32kB for 10G port and 8kB for port 1, capable of 2.5G
7084 int port, size; in mvpp22_rx_fifo_init() local
7092 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) in mvpp22_rx_fifo_init()
7093 mvpp22_rx_fifo_set_hw(priv, port, 0); in mvpp22_rx_fifo_init()
7099 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) { in mvpp22_rx_fifo_init()
7102 else if (port == 0) in mvpp22_rx_fifo_init()
7105 else if (port == 1) in mvpp22_rx_fifo_init()
7114 mvpp22_rx_fifo_set_hw(priv, port, size); in mvpp22_rx_fifo_init()
7125 int port, val; in mvpp23_rx_fifo_fc_set_tresh() local
7127 /* Port 0: maximum speed -10Gb/s port in mvpp23_rx_fifo_fc_set_tresh()
7129 * Port 1: maximum speed -5Gb/s port in mvpp23_rx_fifo_fc_set_tresh()
7131 * Port 2: maximum speed -1Gb/s port in mvpp23_rx_fifo_fc_set_tresh()
7135 /* Without loopback port */ in mvpp23_rx_fifo_fc_set_tresh()
7136 for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) { in mvpp23_rx_fifo_fc_set_tresh()
7137 if (port == 0) { in mvpp23_rx_fifo_fc_set_tresh()
7141 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); in mvpp23_rx_fifo_fc_set_tresh()
7142 } else if (port == 1) { in mvpp23_rx_fifo_fc_set_tresh()
7146 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); in mvpp23_rx_fifo_fc_set_tresh()
7151 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); in mvpp23_rx_fifo_fc_set_tresh()
7157 void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en) in mvpp23_rx_fifo_fc_en() argument
7161 val = mvpp2_read(priv, MVPP2_RX_FC_REG(port)); in mvpp23_rx_fifo_fc_en()
7168 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); in mvpp23_rx_fifo_fc_en()
7171 static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size) in mvpp22_tx_fifo_set_hw() argument
7175 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); in mvpp22_tx_fifo_set_hw()
7176 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), threshold); in mvpp22_tx_fifo_set_hw()
7180 * 1kB fixed space must be assigned for the loopback port.
7183 * per single port).
7190 int port, size; in mvpp22_tx_fifo_init() local
7198 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) in mvpp22_tx_fifo_init()
7199 mvpp22_tx_fifo_set_hw(priv, port, 0); in mvpp22_tx_fifo_init()
7205 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) { in mvpp22_tx_fifo_init()
7209 else if (port == 0) in mvpp22_tx_fifo_init()
7217 mvpp22_tx_fifo_set_hw(priv, port, size); in mvpp22_tx_fifo_init()
7549 if (!fwnode_property_read_u32(port_fwnode, "port-id", &i)) in mvpp2_probe()