Lines Matching +full:0 +full:x1ff00000
13 ixgb_mac_unknown = 0,
20 ixgb_phy_type_unknown = 0,
36 ixgb_media_type_unknown = 0,
44 ixgb_fc_none = 0,
48 ixgb_fc_default = 0xFF
53 ixgb_bus_type_unknown = 0,
60 ixgb_bus_speed_unknown = 0,
70 ixgb_bus_width_unknown = 0,
81 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 /* 13 bits in RDLEN/TDLEN, 128B aligned */
92 #define IXGB_CTRL0 0x00000 /* Device Control Register 0 - RW */
93 #define IXGB_CTRL1 0x00008 /* Device Control Register 1 - RW */
94 #define IXGB_STATUS 0x00010 /* Device Status Register - RO */
95 #define IXGB_EECD 0x00018 /* EEPROM/Flash Control/Data Register - RW */
96 #define IXGB_MFS 0x00020 /* Maximum Frame Size - RW */
99 #define IXGB_ICR 0x00080 /* Interrupt Cause Read - R/clr */
100 #define IXGB_ICS 0x00088 /* Interrupt Cause Set - RW */
101 #define IXGB_IMS 0x00090 /* Interrupt Mask Set/Read - RW */
102 #define IXGB_IMC 0x00098 /* Interrupt Mask Clear - WO */
105 #define IXGB_RCTL 0x00100 /* RX Control - RW */
106 #define IXGB_FCRTL 0x00108 /* Flow Control Receive Threshold Low - RW */
107 #define IXGB_FCRTH 0x00110 /* Flow Control Receive Threshold High - RW */
108 #define IXGB_RDBAL 0x00118 /* RX Descriptor Base Low - RW */
109 #define IXGB_RDBAH 0x0011C /* RX Descriptor Base High - RW */
110 #define IXGB_RDLEN 0x00120 /* RX Descriptor Length - RW */
111 #define IXGB_RDH 0x00128 /* RX Descriptor Head - RW */
112 #define IXGB_RDT 0x00130 /* RX Descriptor Tail - RW */
113 #define IXGB_RDTR 0x00138 /* RX Delay Timer Ring - RW */
114 #define IXGB_RXDCTL 0x00140 /* Receive Descriptor Control - RW */
115 #define IXGB_RAIDC 0x00148 /* Receive Adaptive Interrupt Delay Control - RW */
116 #define IXGB_RXCSUM 0x00158 /* Receive Checksum Control - RW */
117 #define IXGB_RA 0x00180 /* Receive Address Array Base - RW */
118 #define IXGB_RAL 0x00180 /* Receive Address Low [0:15] - RW */
119 #define IXGB_RAH 0x00184 /* Receive Address High [0:15] - RW */
120 #define IXGB_MTA 0x00200 /* Multicast Table Array [0:127] - RW */
121 #define IXGB_VFTA 0x00400 /* VLAN Filter Table Array [0:127] - RW */
125 #define IXGB_TCTL 0x00600 /* TX Control - RW */
126 #define IXGB_TDBAL 0x00608 /* TX Descriptor Base Low - RW */
127 #define IXGB_TDBAH 0x0060C /* TX Descriptor Base High - RW */
128 #define IXGB_TDLEN 0x00610 /* TX Descriptor Length - RW */
129 #define IXGB_TDH 0x00618 /* TX Descriptor Head - RW */
130 #define IXGB_TDT 0x00620 /* TX Descriptor Tail - RW */
131 #define IXGB_TIDV 0x00628 /* TX Interrupt Delay Value - RW */
132 #define IXGB_TXDCTL 0x00630 /* Transmit Descriptor Control - RW */
133 #define IXGB_TSPMT 0x00638 /* TCP Segmentation PAD & Min Threshold - RW */
134 #define IXGB_PAP 0x00640 /* Pause and Pace - RW */
138 #define IXGB_PCSC1 0x00700 /* PCS Control 1 - RW */
139 #define IXGB_PCSC2 0x00708 /* PCS Control 2 - RW */
140 #define IXGB_PCSS1 0x00710 /* PCS Status 1 - RO */
141 #define IXGB_PCSS2 0x00718 /* PCS Status 2 - RO */
142 #define IXGB_XPCSS 0x00720 /* 10GBASE-X PCS Status (or XGXS Lane Status) - RO */
143 #define IXGB_UCCR 0x00728 /* Unilink Circuit Control Register */
144 #define IXGB_XPCSTC 0x00730 /* 10GBASE-X PCS Test Control */
145 #define IXGB_MACA 0x00738 /* MDI Autoscan Command and Address - RW */
146 #define IXGB_APAE 0x00740 /* Autoscan PHY Address Enable - RW */
147 #define IXGB_ARD 0x00748 /* Autoscan Read Data - RO */
148 #define IXGB_AIS 0x00750 /* Autoscan Interrupt Status - RO */
149 #define IXGB_MSCA 0x00758 /* MDI Single Command and Address - RW */
150 #define IXGB_MSRWD 0x00760 /* MDI Single Read and Write Data - RW, RO */
153 #define IXGB_WUFC 0x00808 /* Wake Up Filter Control - RW */
154 #define IXGB_WUS 0x00810 /* Wake Up Status - RO */
155 #define IXGB_FFLT 0x01000 /* Flexible Filter Length Table - RW */
156 #define IXGB_FFMT 0x01020 /* Flexible Filter Mask Table - RW */
157 #define IXGB_FTVT 0x01420 /* Flexible Filter Value Table - RW */
160 #define IXGB_TPRL 0x02000 /* Total Packets Received (Low) */
161 #define IXGB_TPRH 0x02004 /* Total Packets Received (High) */
162 #define IXGB_GPRCL 0x02008 /* Good Packets Received Count (Low) */
163 #define IXGB_GPRCH 0x0200C /* Good Packets Received Count (High) */
164 #define IXGB_BPRCL 0x02010 /* Broadcast Packets Received Count (Low) */
165 #define IXGB_BPRCH 0x02014 /* Broadcast Packets Received Count (High) */
166 #define IXGB_MPRCL 0x02018 /* Multicast Packets Received Count (Low) */
167 #define IXGB_MPRCH 0x0201C /* Multicast Packets Received Count (High) */
168 #define IXGB_UPRCL 0x02020 /* Unicast Packets Received Count (Low) */
169 #define IXGB_UPRCH 0x02024 /* Unicast Packets Received Count (High) */
170 #define IXGB_VPRCL 0x02028 /* VLAN Packets Received Count (Low) */
171 #define IXGB_VPRCH 0x0202C /* VLAN Packets Received Count (High) */
172 #define IXGB_JPRCL 0x02030 /* Jumbo Packets Received Count (Low) */
173 #define IXGB_JPRCH 0x02034 /* Jumbo Packets Received Count (High) */
174 #define IXGB_GORCL 0x02038 /* Good Octets Received Count (Low) */
175 #define IXGB_GORCH 0x0203C /* Good Octets Received Count (High) */
176 #define IXGB_TORL 0x02040 /* Total Octets Received (Low) */
177 #define IXGB_TORH 0x02044 /* Total Octets Received (High) */
178 #define IXGB_RNBC 0x02048 /* Receive No Buffers Count */
179 #define IXGB_RUC 0x02050 /* Receive Undersize Count */
180 #define IXGB_ROC 0x02058 /* Receive Oversize Count */
181 #define IXGB_RLEC 0x02060 /* Receive Length Error Count */
182 #define IXGB_CRCERRS 0x02068 /* CRC Error Count */
183 #define IXGB_ICBC 0x02070 /* Illegal control byte in mid-packet Count */
184 #define IXGB_ECBC 0x02078 /* Error Control byte in mid-packet Count */
185 #define IXGB_MPC 0x02080 /* Missed Packets Count */
186 #define IXGB_TPTL 0x02100 /* Total Packets Transmitted (Low) */
187 #define IXGB_TPTH 0x02104 /* Total Packets Transmitted (High) */
188 #define IXGB_GPTCL 0x02108 /* Good Packets Transmitted Count (Low) */
189 #define IXGB_GPTCH 0x0210C /* Good Packets Transmitted Count (High) */
190 #define IXGB_BPTCL 0x02110 /* Broadcast Packets Transmitted Count (Low) */
191 #define IXGB_BPTCH 0x02114 /* Broadcast Packets Transmitted Count (High) */
192 #define IXGB_MPTCL 0x02118 /* Multicast Packets Transmitted Count (Low) */
193 #define IXGB_MPTCH 0x0211C /* Multicast Packets Transmitted Count (High) */
194 #define IXGB_UPTCL 0x02120 /* Unicast Packets Transmitted Count (Low) */
195 #define IXGB_UPTCH 0x02124 /* Unicast Packets Transmitted Count (High) */
196 #define IXGB_VPTCL 0x02128 /* VLAN Packets Transmitted Count (Low) */
197 #define IXGB_VPTCH 0x0212C /* VLAN Packets Transmitted Count (High) */
198 #define IXGB_JPTCL 0x02130 /* Jumbo Packets Transmitted Count (Low) */
199 #define IXGB_JPTCH 0x02134 /* Jumbo Packets Transmitted Count (High) */
200 #define IXGB_GOTCL 0x02138 /* Good Octets Transmitted Count (Low) */
201 #define IXGB_GOTCH 0x0213C /* Good Octets Transmitted Count (High) */
202 #define IXGB_TOTL 0x02140 /* Total Octets Transmitted Count (Low) */
203 #define IXGB_TOTH 0x02144 /* Total Octets Transmitted Count (High) */
204 #define IXGB_DC 0x02148 /* Defer Count */
205 #define IXGB_PLT64C 0x02150 /* Packet Transmitted was less than 64 bytes Count */
206 #define IXGB_TSCTC 0x02170 /* TCP Segmentation Context Transmitted Count */
207 #define IXGB_TSCTFC 0x02178 /* TCP Segmentation Context Tx Fail Count */
208 #define IXGB_IBIC 0x02180 /* Illegal byte during Idle stream count */
209 #define IXGB_RFC 0x02188 /* Remote Fault Count */
210 #define IXGB_LFC 0x02190 /* Local Fault Count */
211 #define IXGB_PFRC 0x02198 /* Pause Frame Receive Count */
212 #define IXGB_PFTC 0x021A0 /* Pause Frame Transmit Count */
213 #define IXGB_MCFRC 0x021A8 /* MAC Control Frames (non-Pause) Received Count */
214 #define IXGB_MCFTC 0x021B0 /* MAC Control Frames (non-Pause) Transmitted Count */
215 #define IXGB_XONRXC 0x021B8 /* XON Received Count */
216 #define IXGB_XONTXC 0x021C0 /* XON Transmitted Count */
217 #define IXGB_XOFFRXC 0x021C8 /* XOFF Received Count */
218 #define IXGB_XOFFTXC 0x021D0 /* XOFF Transmitted Count */
219 #define IXGB_RJC 0x021D8 /* Receive Jabber Count */
222 #define IXGB_CTRL0_LRST 0x00000008
223 #define IXGB_CTRL0_JFE 0x00000010
224 #define IXGB_CTRL0_XLE 0x00000020
225 #define IXGB_CTRL0_MDCS 0x00000040
226 #define IXGB_CTRL0_CMDC 0x00000080
227 #define IXGB_CTRL0_SDP0 0x00040000
228 #define IXGB_CTRL0_SDP1 0x00080000
229 #define IXGB_CTRL0_SDP2 0x00100000
230 #define IXGB_CTRL0_SDP3 0x00200000
231 #define IXGB_CTRL0_SDP0_DIR 0x00400000
232 #define IXGB_CTRL0_SDP1_DIR 0x00800000
233 #define IXGB_CTRL0_SDP2_DIR 0x01000000
234 #define IXGB_CTRL0_SDP3_DIR 0x02000000
235 #define IXGB_CTRL0_RST 0x04000000
236 #define IXGB_CTRL0_RPE 0x08000000
237 #define IXGB_CTRL0_TPE 0x10000000
238 #define IXGB_CTRL0_VME 0x40000000
241 #define IXGB_CTRL1_GPI0_EN 0x00000001
242 #define IXGB_CTRL1_GPI1_EN 0x00000002
243 #define IXGB_CTRL1_GPI2_EN 0x00000004
244 #define IXGB_CTRL1_GPI3_EN 0x00000008
245 #define IXGB_CTRL1_SDP4 0x00000010
246 #define IXGB_CTRL1_SDP5 0x00000020
247 #define IXGB_CTRL1_SDP6 0x00000040
248 #define IXGB_CTRL1_SDP7 0x00000080
249 #define IXGB_CTRL1_SDP4_DIR 0x00000100
250 #define IXGB_CTRL1_SDP5_DIR 0x00000200
251 #define IXGB_CTRL1_SDP6_DIR 0x00000400
252 #define IXGB_CTRL1_SDP7_DIR 0x00000800
253 #define IXGB_CTRL1_EE_RST 0x00002000
254 #define IXGB_CTRL1_RO_DIS 0x00020000
255 #define IXGB_CTRL1_PCIXHM_MASK 0x00C00000
256 #define IXGB_CTRL1_PCIXHM_1_2 0x00000000
257 #define IXGB_CTRL1_PCIXHM_5_8 0x00400000
258 #define IXGB_CTRL1_PCIXHM_3_4 0x00800000
259 #define IXGB_CTRL1_PCIXHM_7_8 0x00C00000
262 #define IXGB_STATUS_LU 0x00000002
263 #define IXGB_STATUS_AIP 0x00000004
264 #define IXGB_STATUS_TXOFF 0x00000010
265 #define IXGB_STATUS_XAUIME 0x00000020
266 #define IXGB_STATUS_RES 0x00000040
267 #define IXGB_STATUS_RIS 0x00000080
268 #define IXGB_STATUS_RIE 0x00000100
269 #define IXGB_STATUS_RLF 0x00000200
270 #define IXGB_STATUS_RRF 0x00000400
271 #define IXGB_STATUS_PCI_SPD 0x00000800
272 #define IXGB_STATUS_BUS64 0x00001000
273 #define IXGB_STATUS_PCIX_MODE 0x00002000
274 #define IXGB_STATUS_PCIX_SPD_MASK 0x0000C000
275 #define IXGB_STATUS_PCIX_SPD_66 0x00000000
276 #define IXGB_STATUS_PCIX_SPD_100 0x00004000
277 #define IXGB_STATUS_PCIX_SPD_133 0x00008000
278 #define IXGB_STATUS_REV_ID_MASK 0x000F0000
282 #define IXGB_EECD_SK 0x00000001
283 #define IXGB_EECD_CS 0x00000002
284 #define IXGB_EECD_DI 0x00000004
285 #define IXGB_EECD_DO 0x00000008
286 #define IXGB_EECD_FWE_MASK 0x00000030
287 #define IXGB_EECD_FWE_DIS 0x00000010
288 #define IXGB_EECD_FWE_EN 0x00000020
294 #define IXGB_INT_TXDW 0x00000001
295 #define IXGB_INT_TXQE 0x00000002
296 #define IXGB_INT_LSC 0x00000004
297 #define IXGB_INT_RXSEQ 0x00000008
298 #define IXGB_INT_RXDMT0 0x00000010
299 #define IXGB_INT_RXO 0x00000040
300 #define IXGB_INT_RXT0 0x00000080
301 #define IXGB_INT_AUTOSCAN 0x00000200
302 #define IXGB_INT_GPI0 0x00000800
303 #define IXGB_INT_GPI1 0x00001000
304 #define IXGB_INT_GPI2 0x00002000
305 #define IXGB_INT_GPI3 0x00004000
308 #define IXGB_RCTL_RXEN 0x00000002
309 #define IXGB_RCTL_SBP 0x00000004
310 #define IXGB_RCTL_UPE 0x00000008
311 #define IXGB_RCTL_MPE 0x00000010
312 #define IXGB_RCTL_RDMTS_MASK 0x00000300
313 #define IXGB_RCTL_RDMTS_1_2 0x00000000
314 #define IXGB_RCTL_RDMTS_1_4 0x00000100
315 #define IXGB_RCTL_RDMTS_1_8 0x00000200
316 #define IXGB_RCTL_MO_MASK 0x00003000
317 #define IXGB_RCTL_MO_47_36 0x00000000
318 #define IXGB_RCTL_MO_46_35 0x00001000
319 #define IXGB_RCTL_MO_45_34 0x00002000
320 #define IXGB_RCTL_MO_43_32 0x00003000
322 #define IXGB_RCTL_BAM 0x00008000
323 #define IXGB_RCTL_BSIZE_MASK 0x00030000
324 #define IXGB_RCTL_BSIZE_2048 0x00000000
325 #define IXGB_RCTL_BSIZE_4096 0x00010000
326 #define IXGB_RCTL_BSIZE_8192 0x00020000
327 #define IXGB_RCTL_BSIZE_16384 0x00030000
328 #define IXGB_RCTL_VFE 0x00040000
329 #define IXGB_RCTL_CFIEN 0x00080000
330 #define IXGB_RCTL_CFI 0x00100000
331 #define IXGB_RCTL_RPDA_MASK 0x00600000
332 #define IXGB_RCTL_RPDA_MC_MAC 0x00000000
333 #define IXGB_RCTL_MC_ONLY 0x00400000
334 #define IXGB_RCTL_CFF 0x00800000
335 #define IXGB_RCTL_SECRC 0x04000000
336 #define IXGB_RDT_FPDB 0x80000000
338 #define IXGB_RCTL_IDLE_RX_UNIT 0
341 #define IXGB_FCRTL_XONE 0x80000000
344 #define IXGB_RXDCTL_PTHRESH_MASK 0x000001FF
345 #define IXGB_RXDCTL_PTHRESH_SHIFT 0
346 #define IXGB_RXDCTL_HTHRESH_MASK 0x0003FE00
348 #define IXGB_RXDCTL_WTHRESH_MASK 0x07FC0000
352 #define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F
353 #define IXGB_RAIDC_DELAY_MASK 0x000FF800
355 #define IXGB_RAIDC_POLL_MASK 0x1FF00000
357 #define IXGB_RAIDC_RXT_GATE 0x40000000
358 #define IXGB_RAIDC_EN 0x80000000
366 #define IXGB_RXCSUM_IPOFL 0x00000100
367 #define IXGB_RXCSUM_TUOFL 0x00000200
370 #define IXGB_RAH_ASEL_MASK 0x00030000
371 #define IXGB_RAH_ASEL_DEST 0x00000000
372 #define IXGB_RAH_ASEL_SRC 0x00010000
373 #define IXGB_RAH_AV 0x80000000
376 #define IXGB_TCTL_TCE 0x00000001
377 #define IXGB_TCTL_TXEN 0x00000002
378 #define IXGB_TCTL_TPDE 0x00000004
380 #define IXGB_TCTL_IDLE_TX_UNIT 0
383 #define IXGB_TXDCTL_PTHRESH_MASK 0x0000007F
384 #define IXGB_TXDCTL_HTHRESH_MASK 0x00007F00
386 #define IXGB_TXDCTL_WTHRESH_MASK 0x007F0000
390 #define IXGB_TSPMT_TSMT_MASK 0x0000FFFF
391 #define IXGB_TSPMT_TSPBP_MASK 0xFFFF0000
395 #define IXGB_PAP_TXPC_MASK 0x0000FFFF
396 #define IXGB_PAP_TXPV_MASK 0x000F0000
397 #define IXGB_PAP_TXPV_10G 0x00000000
398 #define IXGB_PAP_TXPV_1G 0x00010000
399 #define IXGB_PAP_TXPV_2G 0x00020000
400 #define IXGB_PAP_TXPV_3G 0x00030000
401 #define IXGB_PAP_TXPV_4G 0x00040000
402 #define IXGB_PAP_TXPV_5G 0x00050000
403 #define IXGB_PAP_TXPV_6G 0x00060000
404 #define IXGB_PAP_TXPV_7G 0x00070000
405 #define IXGB_PAP_TXPV_8G 0x00080000
406 #define IXGB_PAP_TXPV_9G 0x00090000
407 #define IXGB_PAP_TXPV_WAN 0x000F0000
410 #define IXGB_PCSC1_LOOPBACK 0x00004000
413 #define IXGB_PCSC2_PCS_TYPE_MASK 0x00000003
414 #define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001
417 #define IXGB_PCSS1_LOCAL_FAULT 0x00000080
418 #define IXGB_PCSS1_RX_LINK_STATUS 0x00000004
421 #define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000
422 #define IXGB_PCSS2_DEV_PRES 0x00004000
423 #define IXGB_PCSS2_TX_LF 0x00000800
424 #define IXGB_PCSS2_RX_LF 0x00000400
425 #define IXGB_PCSS2_10GBW 0x00000004
426 #define IXGB_PCSS2_10GBX 0x00000002
427 #define IXGB_PCSS2_10GBR 0x00000001
430 #define IXGB_XPCSS_ALIGN_STATUS 0x00001000
431 #define IXGB_XPCSS_PATTERN_TEST 0x00000800
432 #define IXGB_XPCSS_LANE_3_SYNC 0x00000008
433 #define IXGB_XPCSS_LANE_2_SYNC 0x00000004
434 #define IXGB_XPCSS_LANE_1_SYNC 0x00000002
435 #define IXGB_XPCSS_LANE_0_SYNC 0x00000001
438 #define IXGB_XPCSTC_BERT_TRIG 0x00200000
439 #define IXGB_XPCSTC_BERT_SST 0x00100000
440 #define IXGB_XPCSTC_BERT_PSZ_MASK 0x000C0000
442 #define IXGB_XPCSTC_BERT_PSZ_INF 0x00000003
443 #define IXGB_XPCSTC_BERT_PSZ_68 0x00000001
444 #define IXGB_XPCSTC_BERT_PSZ_1028 0x00000000
448 #define IXGB_MSCA_NP_ADDR_MASK 0x0000FFFF
449 #define IXGB_MSCA_NP_ADDR_SHIFT 0
451 #define IXGB_MSCA_DEV_TYPE_MASK 0x001F0000
453 #define IXGB_MSCA_PHY_ADDR_MASK 0x03E00000
455 #define IXGB_MSCA_OP_CODE_MASK 0x0C000000
460 #define IXGB_MSCA_ADDR_CYCLE 0x00000000
461 #define IXGB_MSCA_WRITE 0x04000000
462 #define IXGB_MSCA_READ 0x08000000
463 #define IXGB_MSCA_READ_AUTOINC 0x0C000000
465 #define IXGB_MSCA_ST_CODE_MASK 0x30000000
468 #define IXGB_MSCA_NEW_PROTOCOL 0x00000000
469 #define IXGB_MSCA_OLD_PROTOCOL 0x10000000
472 #define IXGB_MSCA_MDI_COMMAND 0x40000000
474 #define IXGB_MSCA_MDI_IN_PROG_EN 0x80000000
477 #define IXGB_MSRWD_WRITE_DATA_MASK 0x0000FFFF
478 #define IXGB_MSRWD_WRITE_DATA_SHIFT 0
479 #define IXGB_MSRWD_READ_DATA_MASK 0xFFFF0000
483 #define IXGB_PHY_ADDRESS 0x0 /* Single PHY, multiple "Devices" */
485 #define MDIO_PMA_PMD_XPAK_VENDOR_NAME 0x803A /* XPAK/XENPAK devices only */
488 #define G6XXX_PMA_PMD_VS1 0xC001 /* Vendor-specific register */
489 #define G6XXX_XGXS_XAUI_VS2 0x18 /* Vendor-specific register */
491 #define G6XXX_PMA_PMD_VS1_PLL_RESET 0x80
492 #define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET 0x00
493 #define G6XXX_XGXS_XAUI_VS2_INPUT_MASK 0x0F /* XAUI lanes synchronized */
509 #define IXGB_RX_DESC_STATUS_DD 0x01
510 #define IXGB_RX_DESC_STATUS_EOP 0x02
511 #define IXGB_RX_DESC_STATUS_IXSM 0x04
512 #define IXGB_RX_DESC_STATUS_VP 0x08
513 #define IXGB_RX_DESC_STATUS_TCPCS 0x20
514 #define IXGB_RX_DESC_STATUS_IPCS 0x40
515 #define IXGB_RX_DESC_STATUS_PIF 0x80
517 #define IXGB_RX_DESC_ERRORS_CE 0x01
518 #define IXGB_RX_DESC_ERRORS_SE 0x02
519 #define IXGB_RX_DESC_ERRORS_P 0x08
520 #define IXGB_RX_DESC_ERRORS_TCPE 0x20
521 #define IXGB_RX_DESC_ERRORS_IPE 0x40
522 #define IXGB_RX_DESC_ERRORS_RXE 0x80
524 #define IXGB_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
525 #define IXGB_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
526 #define IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
541 #define IXGB_TX_DESC_LENGTH_MASK 0x000FFFFF
542 #define IXGB_TX_DESC_TYPE_MASK 0x00F00000
544 #define IXGB_TX_DESC_CMD_MASK 0xFF000000
546 #define IXGB_TX_DESC_CMD_EOP 0x01000000
547 #define IXGB_TX_DESC_CMD_TSE 0x04000000
548 #define IXGB_TX_DESC_CMD_RS 0x08000000
549 #define IXGB_TX_DESC_CMD_VLE 0x40000000
550 #define IXGB_TX_DESC_CMD_IDE 0x80000000
552 #define IXGB_TX_DESC_TYPE 0x00100000
554 #define IXGB_TX_DESC_STATUS_DD 0x01
556 #define IXGB_TX_DESC_POPTS_IXSM 0x01
557 #define IXGB_TX_DESC_POPTS_TXSM 0x02
573 #define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000
574 #define IXGB_CONTEXT_DESC_CMD_IP 0x02000000
575 #define IXGB_CONTEXT_DESC_CMD_TSE 0x04000000
576 #define IXGB_CONTEXT_DESC_CMD_RS 0x08000000
577 #define IXGB_CONTEXT_DESC_CMD_IDE 0x80000000
579 #define IXGB_CONTEXT_DESC_TYPE 0x00000000
581 #define IXGB_CONTEXT_DESC_STATUS_DD 0x01
588 #define IXGB_MEMORY_REGISTER_BASE_ADDRESS 0
594 #define IXGB_MAX_JUMBO_FRAME_SIZE 0x3F00
597 #define IXGB_OPTICAL_PHY_ADDR 0x0 /* Optical Module phy address */
598 #define IXGB_XAUII_PHY_ADDR 0x1 /* Xauii transceiver phy address */
599 #define IXGB_DIAG_PHY_ADDR 0x1F /* Diagnostic Device phy address */
605 u8 filler1[0x2AA8];
607 u8 filler2[0x2AAA];
609 u8 filler3[0xAAAA];
622 #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
623 #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
624 #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
627 #define IXGB_MAX_PHY_REG_ADDRESS 0xFFFF