Lines Matching +full:sync +full:- +full:freq
1 /* SPDX-License-Identifier: GPL-2.0 */
88 /* Loop limit on how long we wait for auto-negotiation to complete */
170 /* 1000BASE-T Control Register */
174 /* 1000BASE-T Status Register */
238 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
262 #define IGC_ICR_TS BIT(19) /* Time Sync Interrupt */
281 #define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */
285 #define IGC_IMS_TS IGC_ICR_TS /* Time Sync Interrupt */
287 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
294 #define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
329 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
401 #define IGC_DTXMXPKTSZ_DEFAULT 0x98 /* 9728-byte Jumbo frames */
403 /* Time Sync Interrupt Causes */
418 /* Time Sync Receive Control bit definitions */
429 /* Time Sync Receive Configuration */
444 /* Time Sync Transmit Control bit definitions */
448 #define IGC_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */
449 #define IGC_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */
450 #define IGC_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */
492 #define IGC_TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
493 #define IGC_TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
497 #define IGC_TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
498 #define IGC_TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
502 #define IGC_TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
503 #define IGC_TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
507 #define IGC_TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
508 #define IGC_TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
556 #define IGC_PTM_STAT_ADJUST_CYC BIT(5) /* 1588 timer adjusted during non-1st PTM cycle */
562 /* GPY211 - I225 defines */
575 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
576 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
580 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
601 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
602 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
615 #define IGC_N0_QUEUE -1
646 /* Minimum time for 100BASE-T where no data will be transmit following move out